SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 D D D D D D D Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock 2048 Words by 9 Bits Low-Power Advanced CMOS Technology Programmable Almost-Full/Almost-Empty Flag D D D D D D Input-Ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 12 ns With a 50-pF Load Data Rates up to 67 MHz 3-State Outputs Package Options Include 44-Pin Plastic Leaded Chip Carrier (FN) and 64-Pin Thin Quad Flat (PAG, PM) Packages description The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9, WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ACT7807 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 VCC HF AF/AE GND PEN RESET VCC NC OE GND Q0 FN PACKAGE (TOP VIEW) 6 5 7 4 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 Q1 VCC Q2 Q3 GND Q4 VCC Q5 Q6 GND Q7 Q8 29 17 18 19 20 21 22 23 24 25 26 27 28 GND WRTCLK WRTEN1/DP9 WRTEN2 IR OR RDEN2 RDEN1 RDCLK VCC D0 D1 D2 GND D3 D4 D5 VCC D6 D7 D8 Q7 NC Q5 Q6 GND GND GND Q4 VCC VCC Q2 Q3 GND Q1 VCC VCC PAG OR PM PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC Q0 GND GND OE NC VCC VCC RESET PEN GND GND AF/AE HF VCC VCC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 NC D0 D1 D2 GND GND D3 D4 NC D5 VCC VCC D6 D7 D8 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NC Q8 VCC VCC RDCLK RDEN1 NC RDEN2 OR IR WRTEN2 WRTEN1/DP9 WRTCLK GND GND NC SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 logic symbol† RESET WRTCLK WRTEN1/DP9 WRTEN2 RDCLK OE RDEN1 1 Φ FIFO 2048 × 9 SN74ACT7807 RESET 19 WRTCLK 20 & IN RDY WRTEN 21 HALF FULL 26 42 RDCLK ALMOST FULL/EMPTY OUT RDY EN1 25 22 5 4 23 IR HF AF/AE OR & RDEN RDEN2 PEN D0 D1 D2 D3 D4 D5 D6 D7 D8 24 2 7 PROGRAM ENABLE 0 0 40 8 39 9 37 11 36 12 Data Data 34 1 13 32 15 31 16 29 17 28 8 8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 functional block diagram OE D0–D8 Location 1 RDCLK RDEN1 RDEN2 Synchronous Read Control Location 2 Read Pointer 2048 × 9 RAM WRTCLK WRTEN1/DP9 WRTEN2 Synchronous Write Control Write Pointer Location 2047 Location 2048 Register RESET StatusFlag Logic Reset Logic Q0 – Q8 OR IR HF PEN AF/AE 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 Terminal Functions TERMINAL NAME I/O DESCRIPTION O Almost-full/almost-empty flag. Depth offset values can be programmed for AF/AE or the default value of 256 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer words or (2048 – Y) or more words. AF/AE is high after reset. D0–D8 I Nine-bit data input port HF O Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset. IR O Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after reset. OE I Output enable. When OE, RDEN1, RDEN2 and OR are high, data is read from the FIFO on a low-to-high transition of RDCLK. When OE is low, reads are disabled and the data outputs are in the high-impedance state. OR O Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory. PEN I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D8 and DP9 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. Q0–Q8 O Nine-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q8 on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When OR is low, the last word read from the FIFO is present on Q0–Q8. RDCLK I Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high transition of RDCLK reads data from memory when RDEN1, RDEN2, OE, and OR are high. OR is synchronous to the low-to-high transition of RDCLK. RDEN1 RDEN2 I Read enables. When RDEN1, RDEN2, OE, and OR are high, data is read from the FIFO on the low-to-high transition of RDCLK. RESET I Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. WRTCLK I Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high transition of WRTCLK writes data to memory when WRTEN1/DP9, WRTEN2, and IR are high. IR is synchronous to the low-to-high transition of WRTCLK. WRTEN1/DP9 I Write enable/data pin 9. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-to-high transition of WRTCLK. When programming an AF/AE offset value, WRTEN1/DP9 is used as the most-significant data bit. WRTEN2 I Write enable. When WRTEN1/DP9, WRTEN2, and IR are high, data is written to the FIFO on a low-to-high transition of WRTCLK. AF/AE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 offset values for AF/AE The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the offsets are not programmed, the default values of X = Y = 256 are used. The AF/AE flag is high when the FIFO contains X or fewer words or (2048 – Y) or more words. Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on D0–D8 and WRTEN1/DP9 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D8 and WRTEN1/DP9 at the time of the second WRTCLK low-to-high transition. While the offsets are programmed, data is not written to the FIFO memory, regardless of the state of the write enables (WRTEN1/DP9, WRTEN2). A maximum value of 1023 can be programmed for either X or Y (see Figure 1). To use the default values of X = Y = 256, PEN must be held high. RESET WRTCLK 3 4 PEN D0–D8 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ X and Y Y ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÎÎÎÎÎ ÎÎÎÎÎ Word 1 IR ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ X and Y MSB WRTEN1/DP9 YMSB WRTEN2 Figure 1. Programming X and Y Separately 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 RESET 1 0 PEN 1 WRTCLK 2 3 4 1 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ WRTEN1/DP9 Don’t Care WRTEN2 Don’t Care Don’t Care D0–D8 1 RDCLK 2 3 4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ RDEN1 Don’t Care RDEN2 Don’t Care 1 0 OE Q0–Q8 Invalid OR Don’t Care AF/AE Don’t Care HF Don’t Care IR Don’t Care Define the AF/AE Flag Using the Default Value of X = Y = 256 Figure 2. Reset Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 1 RESET 0 1 PEN 0 WRTCLK 1 0 WRTEN1/DP9 WRTEN2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D0–D8 RDCLK W1 W2 W3 W4 1 2 3 W(X+2) W1025 W(2049–Y) W2049 1 0 RDEN1 RDEN2 1 0 OE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Q0–Q8 Invalid W1 OR AF/AE HF IR Figure 3. Write Cycle 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 1 0 RESET 1 PEN 0 WRTCLK 1 2 WRTEN1/ DP9 WRTEN2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D0–D8 W2049 RDCLK RDEN1 RDEN2 1 OE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Q0–Q8 W1 W2 W3 W(Y+1) W(Y+2) W1025 W1026 W(2048–X) W(2049–X) W2048 0 W2049 OR AF/AE HF IR Figure 4. Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PAG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions ’ACT7807-15 VCC VIH Supply voltage VIL IOH Low-level input voltage IOL Low level output current Low-level TA Operating free-air temperature ’ACT7807-25 ’ACT7807-40 MAX MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 High-level input voltage High-level output current ’ACT7807-20 MIN 2 2 2 2 UNIT V V 0.8 0.8 0.8 0.8 V Q outputs, flags –8 –8 –8 –8 mA Q outputs 16 16 16 16 8 8 8 8 Flags 0 70 0 70 0 70 0 70 mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL Flags Q outputs II IOZ ICC ∆ICC§ Ci Co WRTEN1/DP9 Other inputs TEST CONDITIONS TYP‡ MAX 2.4 UNIT VCC = 4.5 V, VCC = 4.5 V, IOH = –8 mA IOL = 8 mA V VCC = 4.5 V, VCC = 5.5 V, IOL = 16 mA VI = VCC or 0 0.5 ±5 µA VCC = 5.5 V, VCC = 5.5 V, VO = VCC or 0 VI = VCC – 0.2 V or 0 ±5 µA 400 µA 0.5 2 Other inputs at VCC or GND V 5V VCC = 5 5.5 V, 4V One input at 3 3.4 V, VI = 0, VO = 0, f = 1 MHz 4 pF f = 1 MHz 8 pF ‡ All typical values are at VCC = 5 V, TA = 25°C. § This is the supply current for each input that is at one of the specified TTL voltage levels rather 0 V or VCC. 10 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 mA SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 5) ’ACT7807-15 MIN fclock tw Clock frequency Pulse duration tsu Setup time th Hold time MAX ’ACT7807-20 MIN MAX 67 ’ACT7807-25 MIN 50 MAX ’ACT7807-40 MIN 40 MAX 25 WRTCLK high or low 6 8 9 13 RDCLK high or low 6 8 9 13 PEN low 6 9 9 13 D0–D8 before WRTCLK↑ 4 5 5 5 WRTEN1, WRTEN2 before WRTCLK↑ 4 5 5 5 OE, RDEN1, RDEN2 before RDCLK↑ 5 6 6 6.5 Reset: RESET low before first WRTCLK↑ and RDCLK↑† 7 8 8 8 PEN before WRTCLK↑ 4 5 5 5 D0–D8 after WRTCLK↑ 0 0 0 0 WRTEN1, WRTEN2 after WRTCLK↑ 0 0 0 0 OE, RDEN1, RDEN2 after RDCLK↑ 0 0 0 0 Reset: RESET low after fourth WRTCLK↑ and RDCLK↑† 5 5 5 5 PEN high after WRTCLK↓ 0 0 0 0 PEN low after WRTCLK↑ 3 3 3 3 UNIT MHz ns ns ns † To permit the clock pulse to be utilized for reset purposes switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 5) PARAMETER FROM (INPUT) fmax WRTCLK or RDCLK tpd tpd§ tpd d TO (OUTPUT) RDCLK↑ Any Q ’ACT7807-15 TYP‡ MAX ’ACT7807-20 MIN MIN 67 50 3 9 MAX ’ACT7807-25 MIN MAX 40 ’ACT7807-40 MIN MAX 25 MHz 12 3 13 3 18 3 25 9 1 12 1 14 1 16 RDCLK↑ Any Q WRTCLK↑ IR 1 RDCLK↑ OR 1 9 2 12 2 14 2 16 2 16 2 20 2 25 2 30 2 17 2 20 2 25 2 30 WRTCLK↑ RDCLK↑ 8 AF/AE UNIT ns ns ns tPLH tPHL WRTCLK↑ HF 2 19 2 21 2 23 2 25 ns RDCLK↑ HF 2 16 2 18 2 20 2 22 ns tPLH RESET low AF/AE 1 12 1 18 1 22 1 24 ns tPHL RESET low HF 2 12 2 18 2 22 2 24 ns OE Any Q 2 10 2 13 2 15 2 18 ns OE Any Q 1 11 1 13 1 15 1 18 ns ten tdis ‡ All typical values are at VCC = 5 V, TA = 25°C. § This parameter is measured with CL = 30 pF (see Figure 6). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, TYP f = 5 MHz 91 UNIT pF PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 500 Ω ten From Output Under Test Test Point CL = 50 pF (see Note A) tdis 500 Ω tpd S1 tPZH tPZL tPHZ tPLZ tPLH tPHL Open Closed Open Closed Open Open tw LOAD CIRCUIT 3V Input 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control tPZL 3V 1.5 V 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V tPZH 1.5 V VOL Output Waveform 2 S1 at Open VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE A: CL includes probe and jig capacitance. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 tPLZ ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL VOH 12 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 3V Timing Input Input 1.5 V • DALLAS, TEXAS 75265 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE ACTIVE ICC vs FREQUENCY 200 VCC = 5 V RL = 500 Ω TA = 25°C TA = 25°C 180 VCC = 5.5 V 160 I CC(f) – Active I CC – mA typ + 6 typ + 4 typ + 2 140 VCC = 5 V 120 100 80 VCC = 4.5 V 60 typ 40 20 typ – 2 0 0 50 100 150 200 250 0 300 10 20 CL – Load Capacitance – pF 30 40 50 60 70 f – Frequency – MHz Figure 7 Figure 6 6 VCC = 4.5 V VCC = 5 V VCC = 5.5 V 5 TA = 25° I CC(I) – Idle ICC – mA t pd – Propagation Delay Time – ns typ + 8 4 3 Slope = 0.07 2 1 0 0 10 20 30 40 50 60 70 f – Frequency – MHz Figure 8. SN74ACT7807 Idle ICC With WRTCLK Switching, Other Inputs at 0 or VCC – 0.2 V and Outputs Disconnected POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74ACT7807 2048 × 9 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS200D – JANUARY 1991 – REVISED APRIL 1998 APPLICATION INFORMATION CLOCK SN74ACT7807 RDCLK SN74ACT7807 RDCLK WRTCLK WRTCLK OR WRTEN1 WRTEN1/DP9 WRTEN2 WRTEN2 RDEN1 IR RDEN2 IR OE D0–D8 D0–D8 WRTCLK RDEN1 RDEN1 WRTEN2 RDEN2 RDEN2 IR 5V Q0–Q8 RDCLK WRTEN1/DP9 D0–D8 OR OR OE OE Q0–Q8 Q0–Q8 Figure 9. Word-Depth Expansion: 4096 × 9 Bits WRTCLK WRTEN SN74ACT7807 RDCLK WRTCLK WRTEN1/DP9 RDEN1 WRTEN2 RDEN2 IR RDEN OR OE D9–D17 RDCLK Q0–Q8 D0–D8 OE Q9–Q17 OR IR SN74ACT7807 RDCLK WRTCLK WRTEN1/DP9 RDEN1 WRTEN2 RDEN2 IR OR OE D0–D8 D0–D8 Q0–Q8 Figure 10. Word-Width Expansion: 2048 × 18 Bits 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0–Q8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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