HIP9021 PRELIMINARY Portable Battery Drive/Torque Controller for N-Channel MOSFETs in Motor Control Systems August 1996 Features Description • MOSFET Driver and DC Motor Controller The HIP9021IB is a dedicated Power MOSFET driver which drives a DC motor. As a system, motor speed is controlled while controlling torque. The primary application is drive control for portable drills while providing overload protection. • Torque Control and Overload Protection • Battery Power Supply . . . . . . . . . . . . . . . . +5V to +15V • BiMOS IC with Low Operating Current The main function of the HIP9021IB is to produce a pulse width modulated square wave signal which drives the gate of an N-Channel Power MOSFET. The duty-cycle is determined by the setting of an external potentiometer at the TRIGGER (speed control) input. As the TRIGGER voltage level is decreased the duty-cycle of the square wave and the speed of the motor is increased. - Maximum Supply Current . . . . . . . . . . . . . . . . .1.5mA - Maximum Input Leakage Currents . . . . . . . . . . 1.5µA • 500µA Maximum Supply Current • 1µA Maximum Input Leakage Currents • Typical Oscillator Frequency . . . . . . . . . . . . . . . . . 5kHz • Power-On-Reset Control The torque of the motor is limited by the voltage level sensed at the drain of the external Power MOSFET. When the current reaches an adjustable limit set at the TORQUE input, the drive of the Power MOSFET is disabled. • 10mA Drive Capability for Gate Output • Operating Temperature . . . . . . . -40oC to +85oC Range Applications The system control components include 2 adjustable potentiometer controls and 2 capacitors for the operating frequency and torque delay control. A fixed or battery supply voltage in the range of 5V to 15V may be used. • Portable Battery Operated Electric Drills • Controller for Small DC Electric Motors • Torque/Drive Controller for Inductive Loads The HIP9021IB is provided in a small outline plastic package for a compact surface mount to a ceramic substrate. The surface mount assembly can be fit directly into the trigger of a portable electric drill. • Intelligent MOSFET Drive Ordering Information PART NUMBER HIP9021IB TEMP. RANGE (oC) -40 to +85 PKG. NO. PACKAGE 8 Ld SOIC M8.15 Pinout HIP9021IB (SOIC) TOP VIEW DRAIN 1 8 VDD TRIGGER 2 7 GATE GND 3 6 DELAY OSC 4 5 TORQUE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 4055 HIP9021 Block Diagram VBATT VDD DRAIN + + CONTROL & LOGIC - DELAY TORQUE GC TORQUE LEVEL SET + TRIGGER GATE SPEED CONTROL OSC OSCILLATOR HIP9021 GND 2 HIP9021 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16V Input Voltage. . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to VCC +0.3V Maximum Current, IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Maximum Transient Reverse Current, IR (10s). . . . . . . . . . . . -50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Typical Power Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +5V to +15V Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to 150oC Typical Oscillator Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 5kHz CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications PARAMETER VDD = 7.5V, Figure 1 Test Circuit, Table 1 Conditions, TA = +25oC Unless Otherwise Specified MIN TYP MAX UNITS IDD 0.1 1.2 3.1 mA OSC Source Current +IOSC 19 25 32 µA OSC Sink Current -IOSC -32 -25 -19 µA OSC Threshold Voltage VOSC(TH) 4.75 4.95 5.25 V OSC Trigger Voltage VOSC(TR) 2.30 2.45 2.65 V TRIGGER Input Leak Current ITRIGGER - 0.02 1.5 µA TORQUE Input Leak Current ITORQUE - 0.02 1.5 µA DELAY Current at 1V IDELAY1 1.5 3.4 6 µA DELAY Current at 2V IDELAY2 1 32 50 mA VDELAY(TH) 1.8 1.9 2 V DRAIN Input Resistance RDRAIN 150 260 350 kΩ DRAIN Current IDRAIN 1 1.7 4.6 mA GATE Output Source Current IGATE 10 18 - mA GATE Output Voltage VGATE 6.5 7.4 - V - 10 - V/µs - 44 - % - 3 - % TA = 25oC - 5 - kHz TA = -40oC - 7.2 - kHz TA = 85oC - 3.6 - kHz DC Supply Current DELAY Threshold Voltage GATE Output Slew Rate SYMBOL TEST CONDITIONS VGATE(S/R) Measured in Typical Application Circuit, Duty Cycle = 50%, See Figure 2 DELAY Output Framed Pulse Duty Cycle FP/DC DELAY Output Framed Pulse Delay, VGATE to VDELAY FP/DLY Gate Duty Cycle = 50%; VTORQUE = GND; VDRAIN = VGATE; DELAY =10kΩ to GND, Refer to Figure 1 for the Test circuit and Timing Diagram of the DELAY Output Pulse Frame. Typical Oscillator Frequency fOSC NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 3 HIP9021 VDD 15KΩ 2V 1V 2V 5V 1nF 2V 5V 5V 7.5V VTRIGGER 22nF 8 0.01µF 10µF + DRAIN VTORQUE 1nF VDD 1 VDRAIN 5 6 CONTROL & LOGIC + - TORQUE 1V 2V VDELAY DELAY 10K RD GC 2 TRIGGER VGATE 7 + GATE 4 OSC 10nF VOSC OSC HIP9021 GND 3.75V 2.5V 5V 1nF 3 VDD VGATE GND GATE PULSE WIDTH 1V VDELAY GND FRAMED PULSE WIDTH FRAMED PULSE DELAY NOTE: The timing diagrams relate to the delay output framed pulse and show the time duration of the delay pulse “framed” inside of the gate pulse. The framed pulse duty cycle and delay, in percent, are measured in reference to the gate pulse which is set at 50% duty cycle. The Delay output framed pulse delay is one-half of the difference of the gate pulse width minus delay output framed pulse width. FIGURE 1. ELECTRICAL CHARACTERISTICS TEST CIRCUIT FOR SIGNAL FUNCTIONS OF THE HIP9021 TABLE 1. SWITCH POSITIONS OF FIGURE 1 FOR ELECTRICAL CHARACTERISTIC TESTING SYMBOL DRAIN TRIGGER OSC TORQUE DELAY GATE MEASURE IDD 15KΩ to 2V GND 3.75V 2V Open Open +IOSC 15KΩ to 2V GND 2.5V 2V Open Open IDD Current Into VDD Pin Source Current From OSC Pin -IOSC 15KΩ to 2V GND 5V 2V Open Open Sink Current Into OSC Pin VOSC(TH) 1V Open 1nF 2V Open Open Positive Peak OSC Voltage VOSC(TG) 1V Open 1nF 2V Open Open Negative Peak OSC Voltage ITRIGGER 15KΩ to 2V 5V 5V 2V Open Open TRIGGER Leakage Current ITORQUE 15KΩ to 2V Open 5V 5V Open Open TORQUE Leakage Current IDELAY1 15KΩ to 2V 7.5V 1nF Open 1V Open Current to DELAY Pin IDELAY2 15KΩ to 2V 7.5V 1nF Open 2V Open VDELAY(TH) 1V Ramp Up 1nF 2V GND Read VGATE Measure VTRIGGER When VGATE Less Than 0.5V RDRAIN 5V GND 1nF 2V GND Open DRAIN Current; Calculate RDRAIN = 5V/IDRAIN IDRAIN 1V 7.5V 5V 2V Open Open DRAIN Current VGATE 5V GND 1nF 2V Open Open Measure VGATE = VOUT IGATE 2V GND 1nF 2V GND Set to VOUT -0.5V VGATE(S/R) Refer to Figure 2 Application Circuit, 50% GATE Output Duty Cycle Current to DELAY Pin Measure IGATE Source Current with VGATE = VOUT -0.5V GATE Output Slew Rate FP/DC Reference Figure 1 Waveforms FP/DLY Reference Figure 1 Waveforms fOSC 1V VOSC(TH) -1V 1nF 2V GND 4 25KΩ Load GATE Output Timing HIP9021 Pin Descriptions NAME NUMBER DESCRIPTION DRAIN 1 The input to the DRAIN pin senses the drain of a power MOSFET Output Motor Driver. The DRAIN voltage is an image of the current flowing through the power MOSFET. By limiting this voltage, the torque of the motor can be controlled. TRIGGER 2 The TRIGGER input is an analog voltage control level used to fix the duty-cycle at the DRAIN Output. A voltage level here is determined by a potentiometer adjustment. The TRIGGER voltage level is compared with the triangle signal from the internal oscillator to produce a pulse-width modulated signal. GND 3 Negative pole of the battery or system ground reference. OSC 4 Oscillator output normally terminated in a charge/discharge capacitor. A constant current is flowing in and out to charge and discharge the external capacitor. TORQUE 5 The TORQUE input is a reference level adjustment for torque control. The voltage reference is compared with DRAIN input. If VDRAIN > VTORQUE, the GATE output pulse drive must be disabled. DELAY 6 An external capacitor at the DELAY output is used to delay the torque control action. The external capacitor at the DELAY pin will start to be charged if a MOSFET output over-current condition is detected. The purpose of the capacitor is to delay the disabling action of the signal GATE drive. GATE 7 The GATE output drives the Gate of the Power MOSFET. VDD 8 Positive pole of the battery or Power Supply Voltage, nominally 7.5V. VBATT SW 7.5V 330Ω VDD 1µF 15K + DRAIN 180K + - TORQUE TORQUE LEVEL SET 470K 100K CONTROL & LOGIC 3.3µF PORTABLE ELECTRIC DRILL MOTOR DELAY GC TRIGGER 200K + 5.6K 270K GATE 1nF OSC OSCILLATOR SPEED CONTROL RFP45N03L N-CHANNEL POWER MOSFET 1nF HIP9021 GND NOTE: The value chosen for the torque level set pot is dependent on the type of power MOSFET and motor characteristics. The TRIGGER is a combined SW/Speed Control function. Motor speed increases as the TRIGGER voltage decreases. Speed control range: 2.35V (Min) < VTRIGGER < 5.25V (Max) FIGURE 2. TYPICAL OPERATING CIRCUIT SHOWING THE HIP9021IB AS AN N-CHANNEL MOSFET DRIVER IN A PORTABLE BATTERY ELECTRIC DRILL APPLICATION 5 HIP9021 Functional Description A torque effect condition exists when 80% of the DRAIN signal is higher than the TORQUE input level set voltage of the potentiometer. During this time, the external delay capacitor of 3.3µF is charged through an internal 100K resistor. When the voltage at the DELAY pin reaches 0.25 x VDD, the RS flip-flop is then set and the Gate Control (GC) signal shown in Figure 3 goes to low. The Output GATE drive signal is then disabled. This situation remains even if the voltage on the DELAY pin stays under 0.25 x VDD for a sustained period of time. Oscillator The Oscillator triangle waveform is generated by the charge and discharge of a 1nF external capacitor connected to the OSC pin. The OSC terminal has a source and sink drive from a current mirror which delivers ±25µA. The charge and discharge of the external capacitor is controlled by 2 comparators which compare respectively VOSC with 2/3 VDD and VOSC with 1/3 VDD. The period of the triangle wave is nominally 200µs. At the same time, when the RS flip-flop is set, the external capacitor at the DELAY pin is discharged via the nMOS device, Q2 which is driven by the Q output of the flip-flop. Gate Driver The TRIGGER input signal is compared from the triangle waveform of the oscillator to produce a square wave signal. The duty cycle of the GATE drive signal is increased as the TRIGGER input level increases. The output of the comparator is then NANDed with a GATE Control signal which can enable or disable the GATE output. The NAND gate output is buffered to deliver 18mA typical GATE drive current. Power-On Reset (POR) Torque Effect In reference to Figure 3, the power on of the chip will cause the reset of the RS Gate Control flip-flop when Q1 is switched low. As an initial condition, the Gate Control (GC) signal is reset high. Since power on is the only way to reset the RS flip-flop, a disabled GATE drive signal due to a torque effect condition requires a switched (trigger) reset. The triangle signal, after going through a divider, is also compared with TRIGGER input level. This produces another square wave of the same period but with a duty-cycle that is smaller than the GATE by ~5%. This square wave is used to enable the comparison between DRAIN and TORQUE inputs while the MOSFET is conducting. The POR (power on reset) threshold requires that VDD be less than 2V to initiate a reset. The POR circuit is based on the behavior of the voltage reference cell that produces a constant 1.15V (REF. BIAS) when VDD is over 2V. When Q1 is forward biased, the Q1 drain voltage goes low to reset the input of the RS flip-flop. VDD TORQUE + φ PULL DOWN φ DELAY 100K LOAD COMP 3.3µF 330K φ 50K φ 200K REF. BIAS 1.15V 150K R Q VBATT Q2 POR Q1 MOTOR 6K + - 2K DELAY COMP S Q GATE CONTROL (GC) DRAIN 15K POWER MOSFET OSC TRIGGER GATE + - OSC 1nF 2K BUF φ + φ 40K FIGURE 3. DETAILED LOGIC DIAGRAM OF THE PORTABLE DRIVE/TORQUE CONTROLLER FOR N-CHANNEL POWER MOSFETS SHOWING THE DRAIN AND TORQUE, THE GATE CONTROL LOGIC AND THE TRIGGER (SPEED) CONTROL. 6 HIP9021 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MILLIMETERS MAX A1 e α MIN 8 0o 8 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 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