EN6347QI

Enpirion® Power Datasheet
EN6347QI 4A PowerSoC
Voltage Mode Synchronous
PWM Buck with Integrated Inductor
Description
Features
The EN6347QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal circuits, compensation, and the
inductor in an advanced 4mm x 7mm QFN package.
The EN6347QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architecture.
The device’s advanced circuit techniques, ultra high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
The Altera Enpirion power solution significantly helps
in system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings.
All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible.
•
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•
•
•
•
•
•
•
•
•
90
RA
CA
47µF
1206
PGND
LLM/
SS
AGND SYNC
EFFICIENCY (%)
VFB
80
1206
PGND
100
VOUT
ENABLE
22µF
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Low Voltage, Distributed Power Architectures
• High Efficiency 12V Intermediate Bus Architectures
• Blade Servers, RAID Storage, Industrial
Automation, Embedded Computing, Wireless
Communications
• Beat Frequency/Noise Sensitive Applications
VOUT
VIN
AVIN
Applications
Efficiency vs. Output Current
EN6347QI
PVIN
Integrated Inductor, MOSFETs, Controller
1.5% V OUT Accuracy (Over Load and Temperature)
Up to 4A Continuous Operating Current
3 MHz Operating Frequency with Ext Clock Sync
High Efficiency (Up to 95%)
Frequency Synchronization to External Clock
Input Voltage Range (2.5V to 6.6V)
Programmable Light Load Mode
Output Enable Pin and Power OK
Programmable Soft-Start
Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
• RoHS Compliant, MSL Level 3, 260°C Reflow
RB
CSS
70
60
50
40
30
20
VOUT = 3.3V LLM
10
VOUT = 3.3V PWM
0
0.01
Figure 1. Simplified Applications Circuit
CONDITIONS
VIN = 5V
0.1
1
OUTPUT CURRENT (A)
75mm2
10
Figure 2. Highest Efficiency in Smallest Solution Size
www.altera.com/enpirion
05991
September 1, 2015
Rev H
EN6347QI
Ordering Information
Part Number
EN6347QI
EVB-EN6347QI
Package Markings
EN6347
EN6347
T A (°C)
-40 to +85
Package Description
38-pin (4mm x 7mm x 1.85mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
NC(SW)
NC(SW)
NC(SW)
NC(SW)
AVIN
AGND
VFB
SS
RLLM
POK
ENABLE
LLM / SYNC
37
36
35
34
33
32
31
30
29
28
27
26
KEEP OUT
NC(SW)
12
13
14
15
16
17
18
19
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
6
NC(SW)
VOUT
11
5
VOUT
VOUT
10
4
VOUT
NC
39
PGND
KEEP OUT
9
3
VOUT
NC
8
2
VOUT
NC(SW)
7
1
VOUT
NC(SW)
38
Pin Assignments (Top View)
25
NC
24
NC
23
NC
22
NC
21
PVIN
20
PVIN
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 10 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
NAME
1-2, 12,
34-38
NC(SW)
3-4,
22-25
NC
5-11
VOUT
13-18
PGND
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground, or
voltage. Failure to follow this guideline may result in damage to the device.
NO CONNECT – These pins may be internally connected. Do not connect to each other or to
any other electrical signal. Failure to follow this guideline may result in device damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 13-15.
Input/Output power ground. Connect these pins to the ground electrode of the input and output
filter capacitors. See VOUT and PVIN pin descriptions for more details.
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05991
September 1, 2015
Rev H
EN6347QI
PIN
NAME
19-21
PVIN
26
LLM/
SYNC
27
ENABLE
28
POK
29
RLLM
30
SS
31
VFB
32
AGND
33
AVIN
39
PGND
FUNCTION
Input power supply. Connect to input power supply. Decouple with input capacitor to PGND
pins 16-18.
Dual function pin providing LLM Enable and External Clock Synchronization (see Application
Section). At static Logic HIGH, device will allow automatic engagement of light load mode. At
static logic LOW, the device is forced into PWM only. A clocked input to this pin will
synchronize the internal switching frequency to the external signal. If this pin is left floating, it
will pull to a static logic high, enabling LLM.
Input Enable. Applying logic high enables the output and initiates a soft-start. Applying logic
low discharges the output through a soft-shutdown.
Power OK is an open drain transistor used for power system state indication. POK is logic high
when VOUT is within -10% of VOUT nominal.
Programmable LLM engage resistor to AGND allows for adjustment of load current at which
Light-Load Mode engages. Can be left open for PWM only operation.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value
of this capacitor determines the startup time.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
Analog Ground. This is the controller ground return. Connect to a quiet ground.
Input power supply for the controller. Connect to input voltage at a quiet point.
Device thermal pad to be connected to the system GND plane. See Layout Recommendations
section.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVIN, AVIN, VOUT
-0.3
7.0
V
Voltages on: ENABLE, POK, LLM/SYNC, PG
-0.3
V IN +0.3
V
Voltages on: VFB, SS, RLLM, VDDB
-0.3
2.5
V
-65
150
°C
150
°C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Storage Temperature Range
T STG
Maximum Operating Junction Temperature
T J-ABS Max
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
V IN
2.5
6.6
V
Output Voltage Range (Note 1)
V OUT
0.75
V IN – V DO
V
Output Current
I OUT
4
A
Input Voltage Range
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
Thermal Shutdown
SYMBOL
TYP
UNITS
T SD
160
°C
www.altera.com/enpirion, Page 3
05991
September 1, 2015
Rev H
EN6347QI
Thermal Shutdown Hysteresis
T SDH
35
°C
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
θ JA
30
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θ JC
3
°C/W
Note 1: V DO (dropout voltage) is defined as (I LOAD x Dropout Resistance). Please refer to Electrical Characteristics Table.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
Electrical Characteristics
NOTE: V IN =6.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at T A = 25°C.
PARAMETER
SYMBOL
Operating Input
Voltage
V IN
Under Voltage Lockout – V IN Rising
V UVLOR
Voltage above which UVLO is not
asserted
Under Voltage Lockout – V IN Falling
V UVLOF
Voltage below which UVLO is
asserted
Shut-Down Supply
Current
IS
Operating Quiescent
Current
IQ
Feedback Pin Voltage
V FB
TEST CONDITIONS
MIN
TYP
2.5
MAX
UNITS
6.6
V
2.3
V
2.075
V
ENABLE=0V
100
µA
LLM/SYNC = High
650
µA
Feedback node voltage at:
VIN = 5V, ILOAD = 0, TA = 25°C
(Note 6)
Feedback node voltage at:
0A ≤ ILOAD ≤ 4A
Starting Date Code: X501 or greater
Feedback node voltage at:
3.0V ≤ VIN ≤ 6.0V
0A ≤ ILOAD ≤ 4A
0.7425
0.75
0.7575
V
0.739
0.75
0.761
V
0.735
0.75
0.765
V
5
nA
Feedback Pin Voltage
(Load, Temperature)
V FB
Feedback Pin Voltage
(Line, Load,
Temperature)
V FB
Feedback pin Input
Leakage Current
(Note 3)
I FB
VFB pin input leakage current
-5
V OUT Rise Time
(Note 3)
t RISE
Measured from when V IN > V UVLOR
& ENABLE pin voltage crosses its
logic high threshold to when V OUT
reaches its final value. C SS = 15 nF
0.9
1.2
1.5
ms
Soft Start Capacitor
Range
C SS_RANGE
10
47
68
nF
Output Drop Out
Voltage Resistance
(Note 3)
V DO
R DO
V INMIN - V OUT at Full load
Input to Output Resistance
210
70
315
105
mV
mΩ
Continuous Output
Current
I OUT
PWM mode
LLM mode (Note 4)
4
4
A
Over Current Trip
Level
I OCP
V IN = 5V, V OUT = 1.2V
Disable Threshold
V DISABLE
ENABLE pin logic low.
0.0
0.6
V
ENABLE Threshold
V ENABLE
ENABLE pin logic high
2.5V ≤ V IN ≤ 6.6V
1.8
V IN
V
0
0.002
5
A
www.altera.com/enpirion, Page 4
05991
September 1, 2015
Rev H
EN6347QI
PARAMETER
SYMBOL
ENABLE Lockout Time
T ENLOCKOUT
ENABLE pin Input
Current (Note 3)
I ENABLE
Switching Frequency
(Free Running)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3.2
ms
ENABLE pin has ~180kΩ pull down
40
µA
F SW
Free Running frequency of
oscillator
3
MHz
External SYNC Clock
Frequency Lock
Range
F PLL_LOCK
Range of SYNC clock frequency
SYNC Input Threshold
– Low (LLM/SYNC
PIN)
V SYNC_LO
SYNC Clock Logic Level
SYNC Input Threshold
– High (LLM/SYNC
PIN)
(Note 5)
V SYNC_HI
SYNC Clock Logic Level
POK Lower Threshold
POK LT
Output voltage as a fraction of
expected output voltage
POK Output low
Voltage
V POKL
With 4mA current sink into POK
0.4
V
POK Output Hi Voltage
V POKH
2.5V ≤ V IN ≤ 6.6V
V IN
V
POK pin V OH leakage
current (Note 3)
I POKL
POK high
1
µA
1.8
LLM Logic Low
(LLM/SYNC PIN)
V LLM_LO
LLM Static Logic Level
LLM Logic High
(LLM/SYNC PIN)
V LLM_HI
LLM Static Logic Level
LLM/SYNC Pin is <2.5V
3.5
MHz
0.8
V
2.5
V
90
Minimum VIN-VOUT to ensure proper
LLM operation
LLM Engage
Headroom
LLM/SYNC Pin
Current
2.5
%
800
mV
0.3
1.5
V
V
<100
nA
Note 3: Parameter not production tested but is guaranteed by design.
Note 4: LLM operation is normally only guaranteed above the minimum specified output current.
Note 5: For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be
above 2.5V.
Note 6: The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.
www.altera.com/enpirion, Page 5
05991
September 1, 2015
Rev H
EN6347QI
Typical Performance Curves
PWM Efficiency vs. IOUT (VIN = 3.3V)
100
90
90
80
EFFICIENCY (%)
EFFICIENCY (%)
80
70
60
50
VOUT = 2.5V
40
VOUT = 1.8V
30
VOUT = 1.5V
20
CONDITIONS
VIN = 3.3V
10
0
0.5
1
VOUT = 1.2V
3.5
60
80
EFFICIENCY (%)
90
80
70
60
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
CONDITIONS
VIN = 3.3V
10
0
0.01
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
60
3.5
4
VOUT = 3.3V
50
VOUT = 2.5V
40
VOUT = 1.8V
30
20
VOUT = 1.0V
10
VOUT = 1.5V
10
VOUT = 1.2V
CONDITIONS
VIN = 5V
0
0.01
VOUT = 1.0V
0.1
1
OUTPUT CURRENT (A)
10
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.220
1.015
VIN = 3.3V
1.010
VIN = 5.0V
OUTPUT VOLTAGE (V)
1.020
OUTPUT VOLTAGE (V)
VOUT = 1.0V
70
VOUT = 1.2V
0.1
1
OUTPUT CURRENT (A)
VOUT = 1.2V
LLM Efficiency vs. IOUT (VIN = 5.0V)
90
20
VOUT = 1.5V
CONDITIONS
VIN = 5V
0
4
100
30
VOUT = 1.8V
30
0
LLM Efficiency vs. IOUT (VIN = 3.3V)
40
VOUT = 2.5V
40
100
50
VOUT = 3.3V
50
10
VOUT = 1.0V
1.5
2
2.5
3
OUTPUT CURRENT (A)
70
20
0
EFFICIENCY (%)
PWM Efficiency vs. IOUT (VIN = 5.0V)
100
1.005
1.000
0.995
0.990
CONDITIONS
VOUT = 1.0V
0.985
1.215
VIN = 3.3V
1.210
VIN = 5.0V
1.205
1.200
1.195
1.190
CONDITIONS
VOUT = 1.2V
1.185
0.980
1.180
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
3.5
4
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
3.5
4
www.altera.com/enpirion, Page 6
05991
September 1, 2015
Rev H
EN6347QI
Typical Performance Curves (Continued)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.820
1.515
VIN = 3.3V
1.510
VIN = 5.0V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.520
1.505
1.500
1.495
1.490
CONDITIONS
VOUT = 1.5V
1.485
1.815
VIN = 3.3V
1.810
VIN = 5.0V
1.805
1.800
1.795
1.790
1.780
1.480
0
0.5
1.5
2
2.5
3
1
OUTPUT CURRENT (A)
3.5
0
4
Output Voltage vs. Output Current
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
3.5
4
3.320
2.515
VIN = 3.3V
2.510
VIN = 5.0V
3.315
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.5
Output Voltage vs. Output Current
2.520
2.505
2.500
2.495
2.490
CONDITIONS
VOUT = 2.5V
2.485
VIN = 5.0V
3.310
3.305
3.300
3.295
3.290
CONDITIONS
VOUT = 3.3V
3.285
2.480
3.280
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
3.5
4
0
1.820
1.815
1.815
OUTPUT VOLTAGE (V)
1.820
1.810
1.805
1.800
1.795
1.790
CONDITIONS
VOUT_NOM = 1.8V
Load = 0A
1.785
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
3.5
4
Output Voltage vs. Input Voltage
Output Voltage vs. Input Voltage
OUTPUT VOLTAGE (V)
CONDITIONS
VOUT = 1.8V
1.785
1.810
1.805
1.800
1.795
1.790
CONDITIONS
VOUT_NOM = 1.8V
Load = 1A
1.785
1.780
1.780
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (V)
5.5
6
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (V)
5.5
6
www.altera.com/enpirion, Page 7
05991
September 1, 2015
Rev H
EN6347QI
Typical Performance Curves (Continued)
Output Voltage vs. Input Voltage
1.820
1.815
1.815
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
1.820
1.810
1.805
1.800
1.795
CONDITIONS
VOUT_NOM = 1.8V
Load = 2A
1.790
1.785
1.810
1.805
1.800
1.795
CONDITIONS
CONDITIONS
VOUT_NOM
= 1.8V
LoadLoad
= 3A= A
1.790
1.785
1.780
1.780
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (V)
5.5
2.5
6
5.5
6
1.830
1.815
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.5
4
4.5
5
INPUT VOLTAGE (V)
Output Voltage vs. Temperature
Output Voltage vs. Input Voltage
1.820
1.810
1.805
1.800
1.795
CONDITIONS
CONDITIONS
VOUT_NOM
= 1.8V
Load
=A
Load
= 4A
1.790
1.785
CONDITIONS
VIN = 3.3V
VOUT_NOM = 1.8V
1.820
LOAD = 4A
LOAD = 3A
LOAD = 2A
LOAD = 1A
1.810
LOAD = 0A
1.800
1.790
1.780
1.780
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (V)
5.5
6
-40
Output Voltage vs. Temperature
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
Output Voltage vs. Temperature
1.830
1.830
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.8V
1.820
LOAD = 4A
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3
LOAD = 3A
LOAD = 2A
LOAD = 1A
1.810
LOAD = 0A
1.800
1.790
CONDITIONS
VIN = 6.0V
VOUT_NOM = 1.8V
1.820
LOAD = 4A
LOAD = 3A
LOAD = 2A
LOAD = 1A
1.810
LOAD = 0A
1.800
1.790
1.780
1.780
-40
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
-40
-15
10
35
60
AMBIENT TEMPERATURE (°C)
85
www.altera.com/enpirion, Page 8
05991
September 1, 2015
Rev H
EN6347QI
Typical Performance Curves (Continued)
EMI Performance (Horizontal Scan)
100.0
3.5
90.0
3.0
80.0
2.5
2.0
1.5
VOUT = 1.8V
1.0
VOUT = 2.5V
0.5
VOUT = 3.3V
CONDITIONS
VIN = 5.0V
TJMAX = 125°C
θJA = 30°C/W
No Air Flow
LEVEL (dBµV/m)
MAXIMUM OUTPUT CURRENT (A)
Output Current De-rating
4.0
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.5V
LOAD = 0.5Ω
70.0
60.0
50.0
CISPR 22 Class B 3m
40.0
30.0
20.0
10.0
0.0
55
60
65 70 75 80 85 90 95 100 105
AMBIENT TEMPERATURE (°C)
30
300
FREQUENCY (MHz)
EMI Performance (Vertical Scan)
100.0
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.5V
LOAD = 0.5Ω
90.0
LEVEL (dBµV/m)
80.0
70.0
60.0
50.0
CISPR 22 Class B 3m
40.0
30.0
20.0
10.0
30
300
FREQUENCY (MHz)
www.altera.com/enpirion, Page 9
05991
September 1, 2015
Rev H
EN6347QI
Typical Performance Characteristics
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1V
IOUT = 4A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 4A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(AC Coupled)
LLM Output Ripple at 100mA
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 100mA
CIN = 22µF (1206)
COUT = 2 x 47 µF (1210)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1V
IOUT = 4A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(AC Coupled)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 5.0V
VOUT = 1V
IOUT = 4A
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
VOUT
(AC Coupled)
LLM Output Ripple at 100mA
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 3V
IOUT = 100mA
CIN = 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(AC Coupled)
www.altera.com/enpirion, Page 10
05991
September 1, 2015
Rev H
EN6347QI
Typical Performance Characteristics (Continued)
Enable Power Up/Down
Enable Power Up/Down
ENABLE
ENABLE
VOUT
VOUT
POK
POK
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
NO LOAD, Css = 47nF
CIN = 22µF (1206)
COUT = 47 µF (1206)
LOAD
LOAD
CONDITIONS
VIN = 5.0V, VOUT = 3.3V, LOAD=0.825Ω, Css = 47nF
CIN = 22µF (1206), COUT = 47 µF (1206)
LLM Load Transient from 0.01 to 4A
VOUT
(AC Coupled)
LOAD
VOUT
(AC Coupled)
CONDITIONS
LLM = ENABLED
VIN = 5V
VOUT = 1V
CIN = 22µF (1206)
COUT = 2 x 47µF (1206)
CONDITIONS
LLM = ENABLED
VIN = 5V
VOUT = 3V
CIN = 22µF (1206)
COUT = 2 x 47µF (1206)
LOAD
PWM Load Transient from 0 to 4A
VOUT
(AC Coupled)
LOAD
LLM Load Transient from 0.01 to 4A
PWM Load Transient from 0 to 4A
VOUT
(AC Coupled)
CONDITIONS
LLM = DISABLED
VIN = 5V
VOUT = 1V
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
LOAD
CONDITIONS
LLM = DISABLED
VIN = 5V
VOUT = 3V
CIN = 22µF (1206)
COUT = 47 µF (1206) + 10µF (0805)
www.altera.com/enpirion, Page 11
05991
September 1, 2015
Rev H
EN6347QI
Functional Block Diagram
RLLM
PVIN
UVLO
Thermal Limit
P-Drive
Current Limit
NC(SW)
VOUT
Mode
Logic
N-Drive
(-)
PWM
Comp
(+)
LLM/SYNC
PGND
Compensation
Network
PLL/Sawtooth
Generator
(-)
Error
Amp
(+)
ENABLE
SS
VFB
Power
Good
Logic
POK
AVIN
Soft Start
Voltage
Reference
Regulated
Voltage
AGND
Figure 4: Functional Block Diagram
www.altera.com/enpirion, Page 12
05991
September 1, 2015
Rev H
EN6347QI
Functional Description
Synchronous Buck Converter
Enable Operation
The EN6347QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal input
voltage range is 2.5V to 6.6V. The output voltage is
programmed using an external resistor divider
network. The control loop is voltage-mode with a
type III compensation network. Much of the
compensation circuitry is internal to the device.
However, a phase lead capacitor is required along
with the output voltage feedback resistor divider to
complete the type III compensation network. The
device uses a low-noise PWM topology and also
integrates a unique light-load mode (LLM) to
improve efficiency at light output load currents.
LLM can be disabled with a logic pin. Up to 4A of
continuous output current can be drawn from this
converter. The 3 MHz switching frequency allows
the use of small size input / output capacitors, and
enables wide loop bandwidth within a small foot
print.
The ENABLE pin provides a means to enable
normal operation or to shut down the device. When
the ENABLE pin is asserted (high) the device will
undergo a normal soft-start. A logic low on this pin
will power the device down in a controlled manner.
From the moment ENABLE goes low, there is a
fixed lock out time before the output will respond to
the ENABLE pin re-asserted (high). This lock out is
activated for even very short logic low pulses on the
ENABLE pin. The ENABLE signal must be pulled
high at a slew rate faster than 1V/5µs in order to
meet startup time specifications; otherwise, the
device may experience a delay of 4.2ms (lock-out
time) before startup occurs. See the Electrical
Characteristics Table for technical specifications for
this pin.
Protection Features:
The power supply has the following protection
features:
•
Over-current protection (to protect the IC from
excessive load current)
•
Thermal shutdown with hysteresis.
•
Under-voltage lockout circuit to keep the
converter output off while the input voltage is
less than 2.3V.
Additional Features:
•
The switching frequency can be phase-locked
to an external clock to eliminate or move beat
frequency tones out of band.
•
Soft-start circuit allowing controlled startup
when the converter is initially powered up. The
soft start time is programmable with an
appropriate choice of soft start capacitor.
•
Power good circuit indicating the output voltage
is greater than 90% of programmed value as
long as feedback loop is closed.
•
To maintain high efficiency at low output
current, the device incorporates automatic light
load mode operation.
LLM/SYNC Pin
This is a dual function pin providing LLM Enable
and External Clock Synchronization. At static Logic
HIGH, device will allow automatic engagement of
light load mode. At static logic LOW, the device is
forced into PWM only. A clocked input to this pin
will synchronize the internal switching frequency –
LLM mode is not available if this input is clocked. If
this pin is left floating, it will pull to a static logic
high, enabling LLM.
Frequency Synchronization
The switching frequency of the DC/DC converter
can be phase-locked to an external clock source to
move unwanted beat frequencies out of band. To
avail this feature, the clock source should be
connected to the LLM/SYNC pin. An activity
detector recognizes the presence of an external
clock signal and automatically phase-locks the
internal oscillator to this external clock. Phase-lock
will occur as long as the clock frequency is in the
range specified in the Electrical Characteristics
Table. For proper operation of the synchronization
circuit, the high-level amplitude of the SYNC signal
should not be above 2.5V. Please note LLM is not
available when synchronizing to an external
frequency.
Spread Spectrum Mode
The external clock frequency may be swept
between the limits specified in the Electrical
Characteristics Table at repetition rates of up to 10
kHz in order to reduce EMI frequency components.
www.altera.com/enpirion, Page 13
05991
September 1, 2015
Rev H
EN6347QI
LLM
Ripple
Soft-Start Operation
VMAX
During Soft-start, the output voltage is ramped up
gradually upon start-up. The output rise time is
controlled by the choice of soft-start capacitor,
which is placed between the SS pin (30) and the
AGND pin (32).
PWM
Ripple
VNOM
VOUT
VMIN
Rise Time: T R ≈ (C SS * 80kΩ) ± 25%
Load
Step
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to V IN or similar voltage) from the
converter indicating the output voltage is within the
specified range. The POK signal will be logic high
(V IN ) when the output voltage is above 90% of
programmed V OUT . If the output voltage goes below
this threshold, the POK signal will be logic low.
Light Load Mode (LLM) Operation
The EN6347QI uses a proprietary light load mode
to provide high efficiency at low output currents.
When the LLM/SYNC pin is high, the device is in
automatic LLM “Detection” mode.
When the
LLM/SYNC pin is low, the device is forced into
PWM mode. In automatic LLM “Detection” mode
(LLM connected to AVIN with 50kΩ), when a light
load condition is detected, the device will:
(1) Step V OUT up by approximately 1.0% above the
nominal operating output voltage setting, V NOM
and as low as -0.5% below V NOM , and then
(2) Shut down unnecessary circuitry, and then
(3) Monitor V OUT .
IOUT
Figure 5: V OUT behavior in LLM operation.
Many multi-mode DCDC converters suffer from a
condition that occurs when the load current
increases only slowly so that there is no load
transient driving V OUT below the V MIN threshold. In
this condition, the device would never exit LLM
operation. This could adversely affect efficiency
and cause unwanted ripple. To prevent this from
occurring, the EN6347QI periodically exits LLM
mode into PWM mode and measures the load
current. If the load current is above the LLM
threshold current, the device will remain in PWM
mode. If the load current is below the LLM
threshold, the device will re-enter LLM operation.
There may be a small overshoot or undershoot in
V OUT when the device exits and re-enters LLM.
The load current at which the device will enter LLM
mode is a function of input and output voltage,
inductance variation and the RLLM pin resistor. The
lower the RLLM resistor value, the lower the current
when the device transitions from LLM into PWM
mode. A 60kΩ resistor from RLLM to ground is
recommended for most applications. For PWM only
operation, the RLLM pin can be left open.
When V OUT falls below V NOM , the device will repeat
(1), (2), and (3). The voltage step up, or prepositioning, improves transient droop when a load
transient causes a transition from LLM mode to
PWM mode. If a load transient occurs, causing
V OUT to fall below the threshold V MIN , the device will
exit LLM operation and begin normal PWM
operation. Figure 5 demonstrates V OUT behavior
during transition into and out of LLM operation.
LLM to PWM Current vs. RLLM
2.000
LLM TO PWM CURRENT (A)
During start-up of the converter, the reference
voltage to the error amplifier is linearly increased to
its final level by an internal current source of
approximately 10uA. Typical soft-start rise time is
~3.8ms with SS capacitor value of 47nF. The rise
time is measured from when V IN > V UVLOR and
ENABLE pin voltage crosses its logic high
threshold to when V OUT reaches its programmed
value. Please note LLM function is disabled during
the soft-start ramp-up time.
VIN = 5V, VOUT = 3.3V
1.800
VIN = 3.3V, VOUT = 2.5V
1.600
VIN = 5V, VOUT = 1V
1.400
VIN = 3.3V, VOUT = 1V
1.200
CONDITIONS
TA = 25°C
Typical Values
1.000
0.800
0.600
0.400
0.200
0.000
0
10
20
30 40 50 60 70
RLLM RESISTOR (kΩ)
80
90 100
Figure 6. Typical LLM to PWM Current vs. RLLM
www.altera.com/enpirion, Page 14
05991
September 1, 2015
Rev H
EN6347QI
To ensure normal LLM operation, LLM mode
should be enabled and disabled with specific
sequencing. For applications with explicit LLM pin
control, enable LLM after V IN ramp up is complete.
For applications with only ENABLE controlled, tie
LLM to ENABLE. Enable the device after VIN
ramps up into regulation and disable the device
before VIN ramps. For designs with ENABLE and
LLM tied to V IN , make sure the device soft-start
time is longer than the V IN ramp-up time. LLM will
start operating after the soft-start time is completed.
NOTE: For proper LLM operation the EN6347QI
requires a minimum difference between V IN and
V OUT , and a minimum LLM load requirement as
specified in the Electrical Characteristics Table.
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through the Power PFET. When
the sensed current exceeds the over current trip
point, both power FETs are turned off for the
remainder of the switching cycle. If the over-current
condition is removed, the over-current protection
circuit will enable normal PWM operation. If the
over-current condition persists, the soft start
capacitor will gradually discharge causing the
output voltage to fall. When the OCP fault is
removed, the output voltage will ramp back up to
the desired voltage. This circuit is designed to
provide high noise immunity.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the Junction temperature exceeds
approximately 150ºC. After a thermal shutdown
event, when the junction temperature drops by
approximately 20ºC, the converter will re-start with
a normal soft-start.
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will not
start switching until the input voltage is above the
specified minimum voltage. Hysteresis and input
de-glitch circuits ensure high noise immunity and
prevent false UVLO triggers.
Compensation
The EN6347QI uses a Type III voltage mode
control compensation network. As noted earlier, a
piece of the compensation network is the phase
lead capacitor CA equal 10pF in Figure 6. This
network is optimized for use with about 50-100μF.
The EN6347QI output voltage is programmed using
a simple resistor divider network. Since VFB is a
sensitive node, do not touch the VFB node while
the device is in operation as doing so may
introduce parasitic capacitance into the control loop
that causes the device to behave abnormally and
damage may occur. Figure 6 shows the resistor
divider configuration. An additional compensation
capacitor C A is also required in parallel with the
upper resistor
www.altera.com/enpirion, Page 15
05991
September 1, 2015
Rev H
EN6347QI
Application Information
≤ 1.2V
VOUT
RA
CA = 10 pF
RA = 200 kΩ
RB =
15
18
27
Input Capacitor Selection
VFB
RB
6.6V
5.0V
≤ 3.3V
0.75 * RA
(VOUT − 0.75 V )
Figure 6: V OUT Resistor Divider & Compensation
Capacitor
Best Performance Solution
Cout= 47µF 1206, Cin= 22µF 10V 1206,
Ra= 200kΩ
V out (V)
V in (V)
C a (pF)
6.6V
18
3.3V
≤ 5.0V
22
6.6V
22
2.5V
≤ 5.0V
33
6.6V
27
5.0V
33
1.8V
3.3V
39
2.5V
47
6.6V
27
1.5V
5.0V
33
≤ 3.3V
47
6.6V
27
≤ 1.2V
5.0V
39
≤ 3.3V
47
The EN6347QI requires at least a 22µF X5R/X7R
ceramic input capacitor. Additional input capacitors
may be used in parallel to reduce input voltage
spikes caused by parasitic line inductance. For
applications where the input of the EN6347QI is far
from the input power source, be sure to use
sufficient bulk capacitors to mitigate the extra line
inductance. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R/X7R rated.
Y5V or equivalent dielectric formulations must not
be used as these lose too much capacitance with
frequency, temperature and bias voltage. In some
applications, lower value capacitors are needed in
parallel with the larger, capacitors in order to
provide high frequency decoupling.
Recommended Input Capacitors
Description
22µF, 10V,
X7R, 1206
22µF, 10V,
X5R, 1206
22µF, 16V,
X5R, 0805
MFG
Murata
Taiyo
Yuden
AVX
Murata
Taiyo
Yuden
Murata
Taiyo
Yuden
P/N
GRM31CR71A226ME15
LMK316AB7226KL-TR
1206ZC226KAT2A
GRM31CR61A226ME19L
LMK316BJ226ML-T
GRM21BR61C226ME44L
EMK212BBJ226MG-T
Output Capacitor Selection
Small Foot Print Solution
Cout= 22µF 10V 0805, Cin= 22µF 16V 0805,
Ra= 200kΩ
V out (V)
V in (V)
C a (pF)
3.3V
ALL V in
10
> 5.0V
12
2.5V
≤ 5.0V
15
6.6V
12
5.0V
15
1.8V
3.3V
22
2.5V
27
> 3.3V
15
1.5V
≤ 3.3V
27
The EN6347QI requires at least one 22µF 0805
case size ceramic output capacitor. Additional
output capacitors may be used in parallel near the
load (>4mΩ away) to improve transient response
as well as lower output ripple. In some cases
modifications to the compensation or output filter
capacitance may be required to optimize device
performance such as transient response, ripple, or
hold-up time. The EN6347QI provides the capability
to modify the control loop response to allow for
customization for such applications. Note that in
Type III Voltage Mode Control, the double pole of
the output filter is around 1/2π�LO ∙ Cout , where
C out is the equivalent capacitance of all the output
capacitors including the minimum required output
capacitors that Altera recommended and the extra
www.altera.com/enpirion, Page 16
05991
September 1, 2015
Rev H
EN6347QI
bulk capacitors customers added based on their
design requirement. While the compensation
network was designed based on the capacitors that
Altera recommended, increasing the output
capacitance will shift the double pole to the
direction of lower frequency, which will lower the
loop bandwidth and phase margin. In most cases,
this will not cause the instability due to adequate
phase margin already in the design. In order to
maintain a higher bandwidth as well as adequate
phase margin, a slight modification of the external
compensation is necessary. This can be easily
implemented by increasing the leading capacitor
value, Ca. In addition the ESR of the output
capacitors also helps since the ESR and output
capacitance forms a zero which also helps to boost
the phase
Total COUT Range
Recommended C A
Min ESR
100µF to 250µF
27pF
0
250µF to 450µF
33pF
0
450µF to 1000µF
47pF
>4mΩ
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
impedance, denoted as Z, is comprised of effective
series resistance, ESR, and effective series
inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces the
impedance and will hence result in lower PWM
ripple voltage.
In addition, higher output
capacitance will improve overall regulation and
ripple in light-load mode.
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
(as measured on EN6347QI
Evaluation Board)*
1 x 47 µF
25
47 µF + 10 µF
14
* Note: 20 MHz BW limit
Recommended Output Capacitors
Description
47µF, 6.3V,
X7R, 1210
47uF, 6.3V,
X5R, 1206
22µF, 10V,
X7R, 1206
Low ESR ceramic capacitors are required with
X5R/X7R rated dielectric formulation. Y5V or
equivalent dielectric formulations must not be used
as these lose too much capacitance with frequency,
temperature and bias voltage.
1
Typical PWM Ripple Voltages
22 µF, 10V,
X5R, 1206
22 µF, 10V,
X5R, 0805
10µF, 10V,
X7R, 0805
MFG
Murata
Taiyo
Yuden
Murata
Taiyo
Yuden
Murata
Taiyo
Yuden
AVX
Murata
Taiyo
Yuden
Murata
Taiyo
Yuden
Murata
Taiyo
Yuden
AVX
P/N
GRM32ER70J476ME20
LMK325B7476KM-TR
GRM31CR60J476ME19L
JMK316BJ476ML-T
GRM31CR71A226ME15
LMK316AB7226KL-TR
1206ZC226KAT2A
GRM31CR61A226ME19L
LMK316BJ226ML-T
GRM219R61A226MEA0D
LMK212BJ226MG-T
GRM21BR71A106KE51
LMK212AB7106MG-T
0805ZC106KAT2A
For best LLM performance, we recommend using
just 2x47µF capacitors mentioned in the above
table, and no 10µF capacitor.
The V OUT sense point should be just after the last
output filter capacitor right next to the device.
Additional bulk output capacitance beyond the
above recommendations can be used on the output
node of the EN6347QI as long as the bulk
capacitors are far enough from the V OUT sense
point such that they don’t interfere with the control
loop operation.
Power-Up Sequencing
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements.
www.altera.com/enpirion, Page 17
05991
September 1, 2015
Rev H
EN6347QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Enpirion
PowerSoC helps alleviate some of those concerns.
The Enpirion EN6347QI DC-DC converter is
packaged in a 4x7x3mm 38-pin QFN package. The
QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
The following example and calculations illustrate
the thermal performance of the EN6347QI.
Example:
For V IN = 5V, V OUT = 3.3V at 4A, η ≈ 92%
η = P OUT / P IN = 92% = 0.92
P IN = P OUT / η
P IN ≈ 13.2W / 0.92 ≈ 14.35W
The power dissipation (P D ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
P D = P IN – P OUT
≈ 14.35W – 13.2W ≈ 1.148W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θ JA ). The θ JA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN6347QI has
a θ JA value of 30 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on P D and θ JA .
ΔT = P D x θ JA
ΔT ≈ 1.148W x 30°C/W = 34.43°C ≈ 35°C
V OUT = 3.3V
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A ) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
I OUT = 4A
T J = T A + ΔT
First calculate the output power.
T J ≈ 25°C + 35°C ≈ 60°C
P OUT = 3.3V x 4A = 13.2W
The maximum operating junction temperature
(T JMAX ) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX ) allowed can
be calculated.
V IN = 5V
Next, determine the input power based on the
efficiency (η) shown in Figure 7.
T AMAX = T JMAX – P D x θ JA
PWM Efficiency vs. IOUT (VIN = 5.0V)
100
≈ 125°C – 35°C ≈ 90°C
90
The maximum ambient temperature (before derating) the device can reach is 90°C given the input
and output conditions. Note that the efficiency will
be slightly lower at higher temperatures and this
calculation is an estimate.
EFFICIENCY (%)
80
~92%
70
60
50
40
30
CONDITIONS
VIN = 5V
20
10
VOUT = 3.3V
0
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
3.5
4
Figure 7: Efficiency vs. Output Current
www.altera.com/enpirion, Page 18
05991
September 1, 2015
Rev H
EN6347QI
Engineering Schematic
Figure 8: Engineering Schematic with Engineering Notes
www.altera.com/enpirion, Page 19
05991
September 1, 2015
Rev H
EN6347QI
Layout Recommendation
Figure 9 shows critical components and layer 1
traces of a typical EN6347QI layout with
ENABLE tied to V IN in PWM mode. Alternate
ENABLE configurations, and other small signal
pins need to be connected and routed
according to specific customer application.
Please see the Gerber files on the Altera
website www.altera.com/enpirion for exact
dimensions and other layers. Please refer to
this Figure while reading the layout
recommendations in this section.
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EN6347QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EN6347QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: Three PGND pins are
dedicated to the input circuit, and three to the
output circuit. The slit in Figure 9 separating
the input and output GND circuits helps
minimize noise coupling between the converter
input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Recommendation 4: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible.
Figure 9: Top PCB Layer Critical Components and
Copper for Minimum Footprint
The drill diameter of the vias should be
0.33mm, and the vias must have at least 1 oz.
copper plating on the inside wall, making the
finished hole size around 0.20-0.26mm. Do not
use thermal reliefs or spokes to connect the
vias to the ground plane. This connection
provides the path for heat dissipation from the
converter.
Recommendation 5: Multiple small vias (the
same size as the thermal vias discussed in
recommendation 4 should be used to connect
ground terminal of the input capacitor and
output capacitors to the system ground plane.
It is preferred to put these vias under the
capacitors along the edge of the GND copper
closest to the +V copper. Please see Figure 9.
These vias connect the input/output filter
capacitors to the GND plane, and help reduce
parasitic inductances in the input and output
current loops. If the vias cannot be placed
under C IN and C OUT , then put them just outside
the capacitors along the GND slit separating
the two components. Do not use thermal reliefs
or spokes to connect these vias to the ground
plane.
Recommendation 6: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 9 this connection is made
at the input capacitor close to the V IN
connection.
www.altera.com/enpirion, Page 20
05991
September 1, 2015
Rev H
EN6347QI
Recommendation 7: The layer 1 metal under
the device must not be more than shown in
Figure 9. See the section regarding exposed
metal on bottom of package. As with any
switch-mode DC/DC converter, try not to run
sensitive signal or control lines underneath the
converter package on other layers.
Recommendation 8: The V OUT sense point
should be just after the last output filter
capacitor. Keep the sense trace as short as
possible in order to avoid noise coupling into
the control loop.
Recommendation 9: Keep R A , C A , and R B
close to the VFB pin (see Figures 6). The VFB
pin is a high-impedance, sensitive node. Keep
the trace to this pin as short as possible.
Whenever possible, connect R B directly to the
AGND pin instead of going through the GND
plane.
www.altera.com/enpirion, Page 21
05991
September 1, 2015
Rev H
EN6347QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 10.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN6347QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 10 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package.
Figure 10: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Recommended PCB Footprint
Figure 11: EN6347QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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September 1, 2015
Rev H
EN6347QI
Package and Mechanical
Figure 12: EN6347QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2014 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
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September 1, 2015
Rev H