DATASHEET

EL5120, EL5220, EL5420
Data Sheet
October 15, 2015
12MHz Rail-to-Rail Input-Output Op Amps
Features
The EL5120, EL5220, and EL5420 are low power, high
voltage, rail-to-rail input-output amplifiers. The EL5120
contains a single amplifier, the EL5220 contains two
amplifiers, and the EL5420 contains four amplifiers.
Operating on supplies ranging from 5V to 15V, while
consuming only 500µA per amplifier, the EL5120, EL5220,
and EL5420 have a bandwidth of 12MHz (-3dB). They also
provide common mode input ability beyond the supply rails,
as well as rail-to-rail output capability. This enables these
amplifiers to offer maximum dynamic range at any supply
voltage.
• 12MHz -3dB Bandwidth
The EL5120, EL5220, and EL5420 also feature fast slewing
and settling times, as well as a high output drive capability of
30mA (sink and source). These features make these
amplifiers ideal for use as voltage reference buffers in Thin
Film Transistor Liquid Crystal Displays (TFT-LCD). Other
applications include battery power, portable devices, and
anywhere low power consumption is important.
• Pb-Free Available (RoHS Compliant)
The EL5420 is available in the space-saving 14 Ld TSSOP
package, the industry-standard 14 Ld SOIC package, as well
as the 16 Ld QFN package. The EL5220 is available in the
8 Ld MSOP package and the 8Ld DFN package. The
EL5120 is available in the 5 Ld TSOT package. All feature a
standard operational amplifier pin out. These amplifiers are
specified for operation with an ambient and junction
temperature range of -40°C to +125°C.
• Touch-Screen Displays
FN7186.8
• Supply Voltage = 4.5V to 16.5V
• Low Supply Current (per Amplifier) = 500µA
• High Slew Rate = 10V/µs
• Unity-Gain Stable
• Beyond the Rails Input Capability
• Rail-to-Rail Output Swing
• Ultra-Small Package
Applications
• TFT-LCD Drive Circuits
• Electronics Notebooks
• Electronics Games
• Personal Communication Devices
• Personal Digital Assistants (PDA)
• Portable Instrumentation
• Sampling ADC Amplifiers
• Wireless LANs
• Office Automation
• Active Filters
• ADC/DAC Buffer
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC 2004, 2005, 2007-2009, 2011, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5120, EL5220, EL5420
Ordering Information
PART NUMBER
(Note 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
EL5120IWT-T7 (Notes 1, 4) (No longer K
available or supported)
-40 to +125
5 Ld TSOT Tape and Reel
MDP0049
EL5220ILZ-T13 (Notes 1, 2, 4) (No
longer available or supported)
20Z
-40 to +125
8 Ld DFN Tape and Reel (Pb-Free)
L8.2x3
EL5220CYZ (Note 2)
BBAAA
-40 to +125
8 Ld MSOP (Pb-Free)
MDP0043
EL5220CYZ-T7 (Notes 1, 2)
BBAAA
-40 to +125
8 Ld MSOP Tape and Reel (Pb-Free)
MDP0043
EL5220CYZ-T13 (Notes 1, 2)
BBAAA
-40 to +125
8 Ld MSOP Tape and Reel (Pb-Free)
MDP0043
EL5420CLZ (Note 2) (No longer
available or supported)
5420CLZ
-40 to +125
16 Ld QFN (Pb-Free)
MDP0046
EL5420CSZ (Note 2)
5420CSZ
-40 to +125
14 Ld SOIC (Pb-Free)
MDP0027
EL5420CSZ-T7 (Notes 1, 2)
5420CSZ
-40 to +125
14 Ld SOIC Tape and Reel (Pb-Free)
MDP0027
EL5420CSZ-T13 (Notes 1, 2)
5420CSZ
-40 to +125
14 Ld SOIC Tape and Reel (Pb-Free)
MDP0027
EL5420CR (Note 4) (No longer
available or supported)
5420CR
-40 to +125
14 Ld TSSOP
MDP0044
EL5420CRZ (Note 2)
5420CRZ
-40 to +125
14 Ld TSSOP (Pb-Free)
M14.173
EL5420CRZ-T7 (Notes 1, 2)
5420CRZ
-40 to +125
14 Ld TSSOP Tape and Reel (Pb-Free) M14.173
EL5420CRZ-T13 (Notes 1, 2)
5420CRZ
-40 to +125
14 Ld TSSOP Tape and Reel (Pb-Free) M14.173
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5120, EL5220, EL5420. For more information on MSL please
see tech brief TB363.
4. Not recommended for new designs. Refer to EL5x20T for possible substitutions.
2
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Pinouts
EL5220
(8 LD DFN)
TOP VIEW
EL5220
(8 LD MSOP)
TOP VIEW
8 VS+
VOUTA 1
7 VOUTB
VA
VIN+ 3 A
ER
NG
LO
NO
P
SU 5 VS+
LE
AB
IL + -
5 VINB+
EL5420
(14 LD TSSOP, SOIC)
TOP VIEW
VOUTA 1
VINA- 2
4 VIN-
14 VOUTD
- +
+ -
VINA+ 3
11 VS-
VINB+ 5
VOUTB 7
13 VIND12 VIND+
VS+ 4
VINB- 6
EL5420
(16 LD QFN)
TOP VIEW
10 VINC+
- +
+ -
9 VINC8 VOUTC
VINA- 1
VINA+ 2
VS+ 3
ER
VINB+ 4NG
O
L
NO
R
O
E
THERMAL
L
AB
LPAD
AI
V
A
13 NC
VS- 2
R
O
6 VINB-
VS- 4 ER
5 VINB+
NG
O
L
THERMAL PAD
NO
CONNECTS TO VS-
SU
ED
RT
O
PP 12 VIND-
11 VIND+
10 VS9 VINC+
VINC- 8
VOUT 1
ED
RT
O
P
VINA+ 3
14 VOUTD
EL5120
(5 LD TSOT)
TOP VIEW
+
7 VOUTB
VOUTC 7
VS- 4
6 VINB-
R
O
E
THERMAL
L
B
LAPAD
AI
V
A
15 VOUTA
VINA+ 3
VINA- 2
VOUTB 6
+
16 NC
VINA- 2
ED
RT
O
PP 8 VS+
SU
VINB- 5
VOUTA 1
THERMAL PAD
CONNECTS TO VS-
3
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Thermal Resistance (Typical)
JA (°C/W)
5 Ld TSOT (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . .
214
8 Ld DFN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . .
55
8 Ld MSOP (Note 5). . . . . . . . . . . . . . . . . . . . . . . . .
115
16 Ld QFN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . .
44
14 Ld SOIC (Note 5) . . . . . . . . . . . . . . . . . . . . . . . .
82
14 Ld TSSOP (Note 5) . . . . . . . . . . . . . . . . . . . . . . .
93
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature Range . . . . . . . . . . -40°C to +125°
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
12
UNIT
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
2
TCVOS
Average Offset Voltage Drift
(Note 7)
5
IB
Input Bias Current
VCM = 0V
RIN
Input Impedance
2
mV
µV/°C
50
1
nA
G
CIN
Input Capacitance
CMIR
Common-Mode Input Range
1.35
CMRR
Common-Mode Rejection Ratio
for VIN from -5.5V to +5.5V
50
70
dB
AVOL
Open Loop Gain
-4.5V VOUT 4.5V
75
95
dB
-5.5
pF
+5.5
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
-4.92
VOH
Output Swing High
IL = 5mA
4.92
V
ISC
Short Circuit Current
±120
mA
IOUT
Output Current
±30
mA
4.85
-4.85
V
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from ±2.25V to ±7.75V
IS
Supply Current (Per Amplifier)
No load
60
500
80
-4.0V VOUT 4.0V, 20% to 80%
10
dB
750
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 8)
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
500
ns
BW
-3dB Bandwidth
RL = 10k, CL = 10pF
12
MHz
GBWP
Gain-Bandwidth Product
RL = 10k, CL = 10pF
8
MHz
PM
Phase Margin
RL = 10k, CL = 10pF
50
°
CS
Channel Separation
f = 5MHz (EL5220 and EL5420 only)
75
dB
NOTES:
7. Measured over operating temperature range.
8. Slew rate is measured on rising and falling edges.
4
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
10
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 2.5V
2
TCVOS
Average Offset Voltage Drift
(Note 9)
5
IB
Input Bias Current
VCM = 2.5V
2
RIN
Input Impedance
1
G
CIN
Input Capacitance
1.35
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -0.5V to +5.5V
45
66
dB
AVOL
Open Loop Gain
0.5V VOUT 4.5V
75
95
dB
-0.5
µV/°C
50
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
IOUT
80
4.85
150
mV
4.92
V
Short Circuit Current
±120
mA
Output Current
±30
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current (Per Amplifier)
No load
500
60
750
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 10)
1V VOUT 4V, 20% to 80%
10
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
500
ns
BW
-3dB Bandwidth
RL = 10k, CL = 10pF
12
MHz
GBWP
Gain-Bandwidth Product
RL = 10k, CL = 10pF
8
MHz
PM
Phase Margin
RL = 10k, CL = 10pF
50
°
CS
Channel Separation
f = 5MHz (EL5220 and EL5420 only)
75
dB
NOTES:
9. Measured over operating temperature range.
10. Slew rate is measured on rising and falling edges.
5
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25°C, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
14
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 7.5V
2
TCVOS
Average Offset Voltage Drift
(Note 11)
5
IB
Input Bias Current
VCM = 7.5V
2
RIN
Input Impedance
1
G
CIN
Input Capacitance
1.35
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -0.5V to +15.5V
53
72
dB
AVOL
Open Loop Gain
0.5V VOUT 14.5V
75
95
dB
-0.5
µV/°C
50
+15.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = +5mA
ISC
IOUT
80
14.85
150
mV
14.92
V
Short Circuit Current
±120
mA
Output Current
±30
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
IS
Supply Current (Per Amplifier)
No load
500
60
750
µA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 12)
1V VOUT 14V, 20% to 80%
10
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
500
ns
BW
-3dB Bandwidth
RL = 10k, CL = 10pF
12
MHz
GBWP
Gain-Bandwidth Product
RL = 10k, CL = 10pF
8
MHz
PM
Phase Margin
RL = 10k, CL = 10pF
50
°
CS
Channel Separation
f = 5MHz (EL5220 and EL5420 only)
75
dB
NOTES:
11. Measured over operating temperature range
12. Slew rate is measured on rising and falling edges
6
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Typical Performance Curves
1600
TYPICAL
PRODUCTION
DISTRIBUTION
1400
1200
1000
800
600
400
200
50
40
30
20
10
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (mV)
5
0
-5
50
100
2.0
-50
4.95
4.94
50
100
150
TEMPERATURE (°C)
FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE
7
0
50
100
21
19
150
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
-4.91
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
4.96
0
17
-2.0
TEMPERATURE (°C)
VS = ±5V
IOUT = 5mA
-50
15
0.0
150
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
4.93
13
VS = ±5V
TEMPERATURE (°C)
4.97
11
FIGURE 2. EL5420 INPUT OFFSET VOLTAGE DRIFT
VS = ±5V
0
9
INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
FIGURE 1. EL5420 INPUT OFFSET VOLTAGE DISTRIBUTION
-50
7
1
12
8
10
6
4
2
-0
-2
-4
-6
-8
-10
-12
INPUT OFFSET VOLTAGE (mV)
5
0
0
10
TYPICAL
PRODUCTION
DISTRIBUTION
VS = ±5V
60
3
QUANTITY (AMPLIFIERS)
VS = ±5V
TA = +25°C
QUANTITY (AMPLIFIERS)
70
1800
-4.92
VS = ±5V
IOUT = -5mA
-4.93
-4.94
-4.95
-4.96
-4.97
-50
0
50
100
150
TEMPERATURE (°C)
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Typical Performance Curves
VS = ±5V
RL = 10k
10.40
SLEW RATE (V/µs)
100
OPEN LOOP GAIN (dB)
(Continued)
90
80
VS = ±5V
10.35
10.30
10.25
-50
0
50
100
-50
150
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 8. SLEW RATE vs TEMPERATURE
FIGURE 7. OPEN LOOP GAIN vs TEMPERATURE
700
VS = ±5V
TA = +25°C
0.55
SUPPLY CURRENT (µA)
SUPPLY CURRENT (mA)
50
0
0.5
600
500
400
0.45
-50
0
50
100
300
150
5
0
TEMPERATURE (°C)
FIGURE 9. EL5420 SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
5
-30
100
-80
-130
50
-50
10
100
1k
10k
PHASE (°)
GAIN (dB)
PHASE
-180
GAIN
-230
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY
8
MAGNITUDE (NORMALIZED) (dB)
150
VS = ±5V, TA = +25°C
RL = 10k to GND
CL = 12pF to GND
20
15
FIGURE 10. EL5420 SUPPLY CURRENT PER AMPLIFIER vs
SUPPLY VOLTAGE
20
200
0
10
SUPPLY VOLTAGE (V)
10k
0
1k
560
-5
-10
150
CL = 10pF
AV = 1
VS = ±5V
-15
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS RL
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Typical Performance Curves
(Continued)
200
RL = 10k
AV = 1
10 VS = ±5V
OUTPUT IMPEDANCE ()
MAGNITUDE (NORMALIZED) (dB)
20
12pF
0
50pF
-10
100pF
1000pF
-20
-30
100k
1M
160
120
80
40
0
10k
100M
10M
AV = 1
VS = ±5V
TA = +25°C
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 14. CLOSED LOOP OUTPUT IMPEDANCE vs
FREQUENCY
80
12
10
60
8
CMRR (dB)
MAXIMUM OUTPUT SWING (VP-P)
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
6
VS = ±5V
TA = +25°C
AV = 1
RL = 10k
CL = 12pF
Distortion <1%
4
2
0
10k
40
20
VS = ±5V
TA = +25°C
100k
1M
0
100
10M
1k
FIGURE 15. MAXIMUM OUTPUT SWING vs FREQUENCY
100k
1M
10M
FIGURE 16. CMRR vs FREQUENCY
600
PSRR+
VOLTAGE NOISE (nV/Hz)
80
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
PSRR-
60
PSRR (dB)
1M
100k
40
20
VS = ±5V
TA = +25°C
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 17. PSRR vs FREQUENCY
9
10M
100
10
1
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 18. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Typical Performance Curves
(Continued)
-60
0.010
DUAL MEASURED CHANNEL A TO B
QUAD MEASURED CHANNEL A TO D
OR B TO C
OTHER COMBINATIONS YIELD
IMPROVED REJECTION
0.009
0.008
-80
X-TALK (dB)
THD+ N (%)
0.007
0.006
0.005
0.004
VS = ±5V
0.003 RL = 10k
AV = 1
0.002 V = 1V
IN
RMS
-100
VS = ±5V
RL = 10k
AV = 1
VIN = 220mVRMS
-120
-140
0.001
1k
10k
1k
100k
10k
FIGURE 19. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
1M
6M
V = ±5V
90 AS = 1
V
RL = 10k
VIN = ±50mV
70 T = +25°C
A
FIGURE 20. CHANNEL SEPARATION vs FREQUENCY
RESPONSE
VS = ±5V
AV = 1
RL = 10k
CL = 12pF
TA = +25°C
4
3
STEP SIZE (V)
OVERSHOOT (%)
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
50
30
2
1
0.1%
0
-1
-2
0.1%
-3
10
-4
10
100
1k
LOAD CAPACITANCE (pF)
FIGURE 21. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
1V
1µs
VS = ±5V
TA = +25°C
AV = 1
RL = 10k
CL = 12pF
FIGURE 23. LARGE SIGNAL TRANSIENT RESPONSE
10
0
200
400
600
800
SETTLING TIME (ns)
FIGURE 22. SETTLING TIME vs STEP SIZE
50mV
200ns
VS = ±5V
TA = +25°C
AV = 1
RL = 10k
CL = 12pF
FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Pin Descriptions
EL5120
EL5220
5 LD
TSOT
8 LD MSOP,
8 LD DFN
EL5420
16 LD
QFN
PIN NAME
13, 16
NC
No Connect
IN+
Amplifier Non-Inverting Input
(Reference Circuit 1)
IN-
Amplifier Inverting Input
(Reference Circuit 1)
OUT
Amplifier Output
(Reference Circuit 2)
3
VIN+
Amplifier Non-Inverting Input
(Reference Circuit 1)
4
VIN-
Amplifier Inverting Input
(Reference Circuit 1)
1
VOUT
Amplifier Output
(Reference Circuit 2)
Amplifier A Output
(Reference Circuit 2)
5
2
14 LD TSSOP,
14 LD SOIC
PIN FUNCTION
EQUIVALENT CIRCUIT
1
1
15
VOUTA
2
2
1
VINA-
Amplifier A Inverting Input
(Reference Circuit 1)
3
3
2
VINA+
Amplifier A Non-Inverting Input
(Reference Circuit 1)
8
4
3
VS+
5
5
4
VINB+
Amplifier B Non-Inverting Input
(Reference Circuit 1)
6
6
5
VINB-
Amplifier B Inverting Input
(Reference Circuit 1)
7
7
6
VOUTB
Amplifier B Output
(Reference Circuit 2)
8
7
VOUTC
Amplifier C Output
(Reference Circuit 2)
9
8
VINC-
Amplifier C Inverting Input
(Reference Circuit 1)
10
9
VINC+
Amplifier C Non-Inverting Input
(Reference Circuit 1)
11
10
VS-
12
11
VIND+
Amplifier D Non-Inverting Input
(Reference Circuit 1)
13
12
VIND-
Amplifier D Inverting Input
(Reference Circuit 1)
14
14
VOUTD
Amplifier D Output
(Reference Circuit 2)
4
Positive Power Supply
Negative Power Supply
VS+
VS+
VSCIRCUIT 1
11
VSGND
CIRCUIT 2
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Applications Information
Product Description
The EL5120, EL5220, and EL5420 voltage feedback
amplifiers are fabricated using a high voltage CMOS
process. They exhibit rail-to-rail input and output capability,
they are unity gain stable, and have low power consumption
(500µA per amplifier). These features make the EL5120,
EL5220, and EL5420 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode
and driving a load of 10k and 12pF, the EL5120, EL5220,
and EL5420 have a -3dB bandwidth of 12MHz while
maintaining a 10V/µs slew rate. The EL5120 is a single
amplifier, the EL5220 is a dual amplifier, and the EL5420 is a
quad amplifier.
Operating Voltage, Input, and Output
indefinitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never exceeds
±30mA. This limit is set by the design of the internal metal
interconnects.
Output Phase Reversal
The EL5120, EL5220, and EL5420 are immune to phase
reversal as long as the input voltage is limited from (VS-)
-0.5V to (VS+) +0.5V. Figure 26 shows a photo of the output
of the device with the input voltage driven beyond the supply
rails. Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diodes placed in the input stage of the device
begin to conduct and overvoltage damage could occur.
The EL5120, EL5220, and EL5420 are specified with a
single nominal supply voltage from 5V to 15V or a split
supply with its total range from 5V to 15V. Correct operation
is guaranteed for a supply range of 4.5V to 16.5V. Most
EL5120, EL5220, and EL5420 specifications are stable over
both the full supply range and operating junction
temperature range of -40°C to +125°C. Parameter variations
with operating voltage and/or temperature are shown in the
typical performance curves.
The input common-mode voltage range of the EL5120,
EL5220, and EL5420 extends 500mV beyond the supply
rails. The output swings of the EL5120, EL5220, and
EL5420 typically extend to within 80mV of positive and
negative supply rails with load currents of 5mA. Decreasing
load currents will extend the output voltage range even
closer to the supply rails. Figure 25 shows the input and
output waveforms for the device in the unity-gain
configuration. Operation is from ±5V supply with a 10k load
connected to GND. The input is a 10VP-P sinusoid. The
output voltage is approximately 9.985VP-P.
1V
1V
100µs
VS = ±2.5V
TA = +25°C
AV = 1
VIN = 6VP-P
FIGURE 26. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5120, EL5220,
and EL5420 amplifiers, it is possible to exceed the +125°C
maximum operating junction temperature under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
OUTPUT
INPUT
VS = ±5V
TA = +25°C
AV = 1
VIN = 10VP-P
FIGURE 25. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short Circuit Current Limit
T JMAX – T AMAX
P DMAX = -------------------------------------------- JA
(EQ. 1)
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
The EL5120, EL5220, and EL5420 will limit the short circuit
current to ±120mA if the output is directly shorted to the
positive or the negative supply. If an output is shorted
12
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
supply voltage, plus the power in the IC due to the loads as
shown in Equation 2:
P DMAX = i   V S  I SMAX +  V S + – V OUT i   I LOAD i 
(EQ. 2)
when sourcing, and:
P DMAX = i   V S  I SMAX +  V OUT i – V S -   I LOAD i 
(EQ. 3)
when sinking.
where:
parallel with 10k with just 1.5dB of peaking, and 100pF
with 6.4dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5 and
50) can be placed in series with the output. However, this
will obviously reduce the gain slightly. Another method of
reducing peaking is to add a “snubber” circuit at the output.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. Values of 150 and 10nF are typical. The
advantage of a snubber is that it does not draw any DC load
current or reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
• i = 1 to 2 for dual and 1 to 4 for quad
• VS = Total supply voltage
• ISMAX = Maximum supply current per amplifier
• VOUTi = Maximum output voltage of the application
• ILOADi = Load current
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figure 27
provide a convenient way to see if the device will overheat.
The maximum safe power dissipation can be found
graphically, based on the package type and the ambient
temperature. By using the previous equation, it is a simple
matter to see if PDMAX exceeds the device's power derating
curves. To ensure proper operation, it is important to observe
the recommended derating curves in Figure 27.
The EL5120, EL5220, and EL5420 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to ground, a 0.1µF ceramic capacitor should be
placed from VS+ to pin to VS- pin. A 4.7µF tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
POWER DISSIPATION (W)
3.0
2.5
2.27W
2.0
1.80W
1.5
QFN16
JA = 44°C/W
DFN8
JA = 55°C/W
SOIC14
JA = 82°C/W
TSSOP14
JA = 93°C/W
1.22W
MSOP8
JA = 115°C/W
1.0
870mW
0.5
TSOT5
JA = 214°C/W
467mW
0.0
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
Driving Capacitive Loads
The EL5120, EL5220, and EL5420 can drive a wide range of
capacitive loads. As load capacitance increases, however,
the -3dB bandwidth of the device will decrease and the
peaking will increase. The amplifiers drive 10pF loads in
13
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
October 15, 2015
FN7186.8
CHANGE
- Updated Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
2.00
A
2X 1.50
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
6X 0.50
1
1.80 +0.10/-0.15
3.00
B
(4X)
0.15
8
8X 0.40 ±0.10
TOP VIEW
1.65 +0.10/-0.15
8X 0.25 +0.07/-0.05 4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 ±0.10
0.10 C
(1.65)
(1.50)
(8X 0.60)
C
BASE PLANE
SEATING PLANE
0.08 C
0.05 MAX
SIDE VIEW
(2.80)(1.80)
0.20 REF
C
(6X 0.50)
0.05 MAX
(8X 0.25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
Compies to JEDEC MO-229 VCED-2.
either a mold or mark feature.
15
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Small Outline Package Family (SO)
A
D
h X 45¬
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL ‚Äö
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4¬¨¬®Ð
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
16
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Mini SO Package Family (MSOP)
0.25 M C A B
D
MINI SO PACKAGE FAMILY
(N/2)+1
N
E
MDP0043
A
E1
MILLIMETERS
PIN #1
I.D.
1
B
(N/2)
e
H
C
SEATING
PLANE
0.10 C
N LEADS
0.08 M C A B
b
SYMBOL
MSOP8
MSOP10
TOLERANCE
NOTES
A
1.10
1.10
Max.
-
A1
0.10
0.10
±0.05
-
A2
0.86
0.86
±0.09
-
b
0.33
0.23
+0.07/-0.08
-
c
0.18
0.18
±0.05
-
D
3.00
3.00
±0.10
1, 3
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
8
10
Reference
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
L
A1
0.25
3¬¨¬®Ð
DETAIL X
17
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B
D
MDP0044
A
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
0.20 C B A
1
(N/2)
B
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL ‚Äö
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0¬¨¬®Ðê
DETAIL X
18
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
QFN (Quad Flat No-Lead) Package Family
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
A
MILLIMETERS
D
N
(N-1)
(N-2)
B
1
2
3
PIN #1
I.D. MARK
E
(N/2)
2X
0.075 C
2X
0.075 C
N LEADS
TOP VIEW
0.10 M C A B
(N-2)
(N-1)
N
b
L
SYMBOL QFN44 QFN3
TOLERANCE
NOTES
A
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
+0.03/-0.02
-
b
0.25
0.25
0.23
0.22
±0.02
-
c
0.20
0.20
0.20
0.20
Reference
-
D
7.00
5.00
8.00
5.00
Basic
-
Reference
8
Basic
-
Reference
8
Basic
-
D2
5.10
3.80
5.80 3.60/2.48
E
7.00
7.00
8.00
1
2
3
6.00
E2
5.10
5.80
5.80 4.60/3.40
e
0.50
0.50
0.80
0.50
L
0.55
0.40
0.53
0.50
±0.05
-
N
44
38
32
32
Reference
4
ND
11
7
8
7
Reference
6
NE
11
12
8
9
Reference
5
MILLIMETERS
PIN #1 I.D.
3
QFN32
SYMBOL QFN28 QFN2
QFN20
QFN16
A
0.90
0.90
0.90
0.90
0.90
±0.10
-
A1
0.02
0.02
0.02
0.02
0.02
+0.03/
-0.02
-
b
0.25
0.25
0.30
0.25
0.33
±0.02
-
c
0.20
0.20
0.20
0.20
0.20
Reference
-
D
4.00
4.00
5.00
4.00
4.00
Basic
-
D2
2.65
2.80
3.70
2.70
2.40
Reference
-
(E2)
(N/2)
NE 5
7
(D2)
BOTTOM VIEW
0.10 C
e
C
SEATING
PLANE
TOLERANCE NOTES
E
5.00
5.00
5.00
4.00
4.00
Basic
-
E2
3.65
3.80
3.70
2.70
2.40
Reference
-
e
0.50
0.50
0.65
0.50
0.65
Basic
-
L
0.40
0.40
0.40
0.40
0.60
±0.05
-
N
28
24
20
20
16
Reference
4
ND
6
5
5
5
4
Reference
6
NE
8
7
5
5
4
Reference
5
Rev 11 2/07
0.08 C
N LEADS
& EXPOSED PAD
SEE DETAIL "X"
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
(c)
C
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
2
A
(L)
A1
N LEADS
DETAIL X
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
19
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
TSOT Package Family
MDP0049
e1
D
TSOT PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
2X
1
5
2
(N/2)
0.25 C
2X N/2 TIPS
e
ddd M
B
C A-B D
b
NX
0.15 C A-B
1
3
D
2X
TSOT5
TSOT6
TSOT8
TOLERANCE
A
1.00
1.00
1.00
Max
A1
0.05
0.05
0.05
±0.05
A2
0.87
0.87
0.87
±0.03
b
0.38
0.38
0.29
±0.07
c
0.127
0.127
0.127
+0.07/-0.007
D
2.90
2.90
2.90
Basic
E
2.80
2.80
2.80
Basic
E1
1.60
1.60
1.60
Basic
e
0.95
0.95
0.65
Basic
e1
1.90
1.90
1.95
Basic
L
0.40
0.40
0.40
±0.10
L1
0.60
0.60
0.60
Reference
ddd
0.20
0.20
0.13
-
N
5
6
8
Reference
Rev. B 2/07
C
A2
SEATING
PLANE
1. Plastic or metal protrusions of 0.15mm maximum per side are
not included.
2. Plastic interlead protrusions of 0.15mm maximum per side are
not included.
A1
0.10 C
NOTES:
NX
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
(L1)
5. Index area - Pin #1 I.D. will be located within the indicated zone
(TSOT6 AND TSOT8 only).
H
A
GAUGE
PLANE
c
L
20
6. TSOT5 version has no center lead (shown as a dashed line).
0.25
4¬¨¬®Ð
FN7186.8
October 15, 2015
EL5120, EL5220, EL5420
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
8
14
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
0.20 C B A
7
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06
0.10 C
0.10
GAUGE
PLANE
0.25
5
0°-8°
0.05 MIN
0.15 MAX
CBA
SIDE VIEW
0.60 ±0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
21
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
FN7186.8
October 15, 2015