EL5420T ® Data Sheet September 25, 2009 12MHz Rail-to-Rail Input-Output Operational Amplifier Features • 12MHz (-3dB) Bandwidth The EL5420T is a low power, high voltage rail-to-rail input-output amplifier. The EL5420T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. • 4.5V to 19V Maximum Supply Voltage Range • 12V/µs Slew Rate • 500µA Supply Current (per Amplifier) The maximum operating voltage range is from 4.5V to 19V. It can be configured for single or dual supply operation, and typically consumes only 500µA per amplifier. The EL5420T has an output short circuit capability of ±200mA and a continuous output current capability of ±70mA. • ±70mA Continuous Output Current The EL5420T features a slew rate of 12V/µs. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. These features make the EL5420T an ideal amplifier solution for use in TFT-LCD panels as a VCOM or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. • Rail-to-rail Output Swing The EL5420T is available in a 14 Ld TSSOP package, 14 Ld SOIC package, and a space saving thermally enhanced 16 Ld QFN package. All feature a standard operational amplifier pin out. The devices operate over an ambient temperature range of -40°C to +85°C. • Static Gamma Buffers Ordering Information • Personal Communication Devices PART NUMBER (Note) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # • ±200mA Output Short Circuit Current • Unity-gain Stable • Beyond the Rails Input Capability • Built-in Thermal Protection • -40°C to +85°C Ambient Temperature Range • Pb-free (RoHS compliant) Applications • TFT-LCD Panels • VCOM Amplifiers • Electronics Notebooks • Electronics Games • Touch-screen Displays • Personal Digital Assistants (PDA) • Portable Instrumentation EL5420TILZ* 5420TIL Z 16 Ld QFN MDP0046 EL5420TIRZ* 5420TIR Z 14 Ld TSSOP MDP0044 • Sampling ADC Amplifiers EL5420TISZ* 5420TIS Z 14 Ld SOIC MDP0027 • Wireless LANs *Add “-T7” or “-T13” suffix for tape and reel.Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 FN6838.0 • Office Automation • Active Filters • ADC/DAC Buffer CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5420T Pinouts EL5420T (14 LD TSSOP, SOIC) TOP VIEW VOUTA 1 13 NC 14 VOUTD 15 VOUTA 16 NC EL5420T (16 LD QFN) TOP VIEW VINA- 1 VINA+ 2 THERMAL PAD VS+ 3 VINC- 8 VOUTC 7 VOUTB 6 VINB- 5 VINB+ 4 VINA- 2 12 VIND- VINA+ 3 11 VIND+ VS+ 4 10 VS- VINB+ 5 9 VINC+ VINB- 6 VOUTB 7 14 VOUTD - + + - 13 VIND12 VIND+ 11 VS10 VINC+ - + + - 9 VINC8 VOUTC THERMAL PAD CONNECTS TO VS- 2 FN6838.0 September 25, 2009 EL5420T Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . +19.8V Input Voltage Range (VINx+, VINx-) . . . . . . . . . VS- -0.5V, VS+ +0.5V Input Differential Voltage (VINx+ - VINx-) . . .(VS+ +0.5V)-(VS- -0.5V) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . ±70mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V Thermal Resistance Junction-to-Ambient (Typical) θJA (°C/W) 16 Ld QFN (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ld SOIC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 14 Ld TSSOP (Note 2) . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Junction-to-Case (Typical) 47 88 100 θJC (°C/W) 16 Ld QFN (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . 9 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Power Dissipation Curves . . . . . . . . . . . . . . .See Figures 30 and 31 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 13 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 3 TCVOS Average Offset Voltage Drift (Note 4) 14 LD TSSOP, SOIC package 7 µV/°C 16 LD QFN package 2 µV/°C VCM = 0V 2 IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio For VINx from -5.5V to +5.5V 50 75 dB AVOL Open Loop Gain -4.5V ≤ VOUTx ≤ +4.5V 75 105 dB -5.5 50 +5.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA ISC Short Circuit Current VCM = 0V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ IOUT Output Current -4.94 4.85 -4.85 V 4.94 V ±200 mA ±70 mA POWER SUPPLY PERFORMANCE (VS+) - (VS-) Supply Voltage Range IS Supply Current (Per Amplifier) VCM = 0V, No load PSRR Power Supply Rejection Ratio Supply is moved from ±2.25V to ±9.5V 4.5 500 60 19 V 750 µA 75 dB 12 V/µs DYNAMIC PERFORMANCE SR Slew Rate (Note 5) 3 -4.0V ≤ VOUTx ≤ +4.0V, 20% to 80% FN6838.0 September 25, 2009 EL5420T Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 10kΩ to 0V, TA = +25°C, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT tS Settling to +0.1% (Note 6) AV = +1, VOUTx = 2V step, RL= 10kΩ, CL= 8pF 500 ns BW -3dB Bandwidth RL= 10kΩ, CL= 8pF 12 MHz GBWP Gain-Bandwidth Product AV = -50, RF = 5kΩ, RG= 100Ω RL= 10kΩ, CL= 8pF 8 MHz PM Phase Margin AV = -50, RF = 5kΩ, RG= 100Ω RL= 10kΩ, CL= 8pF 50 ° CS Channel Separation f = 5MHz 75 dB Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, RL = 10kΩ to 2.5V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 13 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 3 TCVOS Average Offset Voltage Drift (Note 4) 14 LD TSSOP, SOIC package 7 µV/°C 16 LD QFN package 2 µV/°C VCM = 2.5V 2 IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio For VINx from -0.5V to +5.5V 45 70 dB AVOL Open Loop Gain 0.5V ≤ VOUTx ≤+ 4.5V 75 105 dB -0.5 50 +5.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -2.5mA VOH Output Swing High IL = +2.5mA ISC Short Circuit Current VCM = 2.5V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ IOUT Output Current 30 4.85 150 mV 4.97 V ±125 mA ±70 mA POWER SUPPLY PERFORMANCE (VS+) - (VS-) Supply Voltage Range IS Supply Current (Per Amplifier) VCM = 2.5V, No load PSRR Power Supply Rejection Ratio Supply is moved from 4.5V to 19V 4.5 500 60 19 V 750 µA 75 dB DYNAMIC PERFORMANCE SR Slew Rate (Note 5) 1V ≤ VOUTx ≤ 4V, 20% to 80% 12 V/µs tS Settling to +0.1% (Note 6) AV = +1, VOUTx = 2V step, RL= 10kΩ, CL= 8pF 500 ns BW -3dB Bandwidth RL= 10kΩ, CL= 8pF 12 MHz GBWP Gain-Bandwidth Product AV = -50, RF = 5kΩ, RG= 100Ω RL= 10kΩ, CL= 8pF 8 MHz PM Phase Margin AV = -50, RF = 5kΩ, RG= 100Ω RL= 10kΩ, CL= 8pF 50 ° CS Channel Separation f = 5MHz 75 dB 4 FN6838.0 September 25, 2009 EL5420T Electrical Specifications PARAMETER VS+ = +18V, VS- = 0V, RL = 10kΩ to 9V, TA = +25°C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 15 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 9V 4 TCVOS Average Offset Voltage Drift (Note 4) 14 LD TSSOP, SOIC package 7 µV/°C 16 LD QFN package 2 µV/°C VCM = 9V 2 IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio For VINx from -0.5V to +18.5V 53 78 dB AVOL Open Loop Gain 0.5V ≤ VOUTx ≤ 17.5V 75 90 dB -0.5 50 +18.5 nA V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -9mA VOH Output Swing High IL = +9mA ISC Short Circuit Current VCM = 9V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ IOUT Output Current 100 17.85 150 mV 17.90 V ±200 mA ±70 mA POWER SUPPLY PERFORMANCE (VS+) - (VS-) Supply Voltage Range IS Supply Current (Per Amplifier) VCM = 9V, No load PSRR Power Supply Rejection Ratio Supply is moved from 4.5V to 19V 4.5 550 60 19 V 750 µA 75 dB DYNAMIC PERFORMANCE SR Slew Rate (Note 5) 1V ≤ VOUTx ≤ 17V, 20% to 80% 12 V/µs tS Settling to +0.1% (Note 6) AV = +1, VOUTx = 2V step, RL= 10kΩ, CL= 8pF 500 ns BW -3dB Bandwidth RL= 10kΩ, CL= 8pF 12 MHz GBWP Gain-Bandwidth Product AV = -50, RF = 5kΩ, RG= 100Ω RL= 10kΩ, CL= 8pF 8 MHz PM Phase Margin AV = -50, RF = 5kΩ, RG= 100Ω RL= 10kΩ, CL= 8pF 50 ° CS Channel Separation f = 5MHz 75 dB NOTES: 4. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in the “Typical Performance Curves” on page 6 5. Typical slew rate is an average of the slew rates measured on the rising (20%-80%) and the falling (80%-20%) edges of the output signal. 6. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%] 5 FN6838.0 September 25, 2009 EL5420T Typical Performance Curves 35 VS = ±5V TA = +25°C TYPICAL PRODUCTION DISTRIBUTION 2400 QUANTITY (AMPLIFIERS) 2800 2000 1600 1200 800 400 0 FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION QUANTITY (AMPLIFIERS) VS = ±5V -40°C to +85°C 25 TYPICAL PRODUCTION DISTRIBUTION 20 15 10 5 0 20 15 10 5 2 4 6 8 10 12 14 16 18 20 22 24 26 28 INPUT OFFSET VOLTAGE DRIFT (|µV|/°C) VS = ±5V 5.0 2.5 0.0 -2.5 -50 0 50 100 TEMPERATURE (°C) 150 FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE 2 4.95 VS = ±5V OUTPUT HIGH VOLTAGE (V) INPUT BIAS CURRENT (nA) 25 FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (TSSOP, SOIC) 1 2 3 4 5 6 7 8 9 10 11 12 INPUT OFFSET VOLTAGE DRIFT (|µV|/°C) FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (QFN) 1 0 -1 -2 -50 TYPICAL PRODUCTION DISTRIBUTION 7.5 30 0 VS = ±5V -40°C TO +85°C 30 0 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE (mV) QUANTITY (AMPLIFIERS) 3200 0 50 100 TEMPERATURE (°C) 150 FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE 6 VS = ±5V IOUT = 5mA 4.93 4.91 4.89 -50 0 50 100 TEMPERATURE (°C) 150 FIGURE 6. OUTPUT HIGH VOLTAGE vs TEMPERATURE FN6838.0 September 25, 2009 EL5420T Typical Performance Curves (Continued) 140 -4.92 VS = ±5V IOUT = -5mA OPEN LOOP GAIN (dB) OUTPUT LOW VOLTAGE (V) -4.91 -4.93 -4.94 -4.95 -4.96 -50 0 50 100 TEMPERATURE (°C) 80 60 40 -50 SUPPLY CURRENT (µA) 13.0 12.5 0 50 100 TEMPERATURE (°C) 150 FIGURE 9. SLEW RATE vs TEMPERATURE 150 VS = ±5V NO LOAD INPUTS AT GND 525 500 475 450 -50 0 50 100 TEMPERATURE (°C) 150 FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE 650 16 TA = +25°C AV = 1 RL = 10kΩ CL = 8pF TA = +25°C SLEW RATE (V/µs) SUPPLY CURRENT (µA) 50 100 TEMPERATURE (°C) 550 V S = ±5V R L = 10k Ω 600 0 FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE 13.5 SLEW RATE (V/µs) 100 150 FIGURE 7. OUTPUT LOW VOLTAGE vs TEMPERATURE 12.0 -50 VS = ±5V RL = 10kΩ 120 550 500 450 14 12 10 400 350 2 4 6 8 SUPPLY VOLTAGE (±V) 10 FIGURE 11. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE 7 8 2 6 8 4 SUPPLY VOLTAGE (±V) 10 FIGURE 12. SLEW RATE vs SUPPLY VOLTAGE FN6838.0 September 25, 2009 EL5420T Typical Performance Curves (Continued) 250 5 10kΩ 200 80 GAIN 60 150 40 100 PHASE 20 50 VS = ±5V TA = +25°C RL = 10kΩ CL = 8pF 0 -20 10 100 GAIN (dB) 0 PHASE (°) OPEN LOOP GAIN (dB) 100 1kΩ 560Ω -5 150Ω VS = ±5V AV = 1 CL = 8pF -10 0 1k 10k 100k 1M 10M -50 100M -15 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS RL 20 200 GAIN (dB) 10 0 50pF 8pF -10 1000pF -20 VS = ±5V AV = 1 RL = 10kΩ -30 100k 1M 10M FREQUENCY (Hz) 40 1k 10k 100k 1M FREQUENCY (Hz) 10M VS = ±5V TA = +25°C VINx = -10dBm -10 -20 CMRR (dB) 8 0 80 0 10 2 120 FIGURE 16. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY 12 4 VS = ±5V AV = 1 RL = OPEN VOUTx = +13dBm 160 0 100M FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS CL MAXIMUM OUTPUT SWING (VP-P) OUTPUT IMPEDANCE (Ω) 100pF 6 100M VS = ±5V TA = +25°C AV = 1 RL = 10kΩ CL = 8pF 10k -30 -40 -50 -60 100k 1M FREQUENCY (Hz) 10M FIGURE 17. MAXIMUM OUTPUT SWING vs FREQUENCY 8 -70 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M FIGURE 18. CMRR vs FREQUENCY FN6838.0 September 25, 2009 EL5420T Typical Performance Curves (Continued) 0 1000 PSRR (dB) -20 -30 -40 -50 PSRR+ -60 -70 TA = +25°C VOLTAGE NOISE (nV/√Hz) VS = ±5V TA = +25°C -10 100 10 PSRR- -80 1k 10k 100k 1M FREQUENCY (Hz) 1 100 10M -60 0.035 1M 10M 100M 0.030 0.025 0.020 MEASURED CH A TO D, OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION -70 XTALK(dB) VS = ±5V RL = 10kΩ AV = 1 VIN = 1.4VRMS 0.040 100k FIGURE 20. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 0.050 0.045 10k FREQUENCY (Hz) FIGURE 19. PSRR vs FREQUENCY THD+N (%) 1k VS = ±5V AV = 1 VINx = 0dBm -80 -90 0.015 0.010 0.005 100 1k 10k FREQUENCY (Hz) 100k FIGURE 21. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY -100 10k 5 4 3 STEP SIZE (V) OVERSHOOT (%) 80 40 VS = ±5V TA = +25°C AV = 1 RL = 10kΩ VINx = ±50mV 20 0 10 100 LOAD CAPACITANCE (pF) FIGURE 23. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE 9 10M FIGURE 22. CHANNEL SEPARATION vs FREQUENCY RESPONSE 100 60 100k 1M FREQUENCY (Hz) 2 VS = ±5V TA = +25°C AV = 1 RL = 10kΩ CL = 8pF 0.1% 1 0 -1 -2 0.1% -3 -4 1000 -5 100 200 300 400 500 SETTLING TIME (ns) 600 700 FIGURE 24. STEP SIZE vs SETTLING TIME FN6838.0 September 25, 2009 EL5420T Typical Performance Curves (Continued) VS = ±5V TA = +25°C AV = 1 RL= 10kΩ CL =8pF 50mV/DIV 1V/DIV VS = ±5V TA = +25°C AV = 1 RL= 10kΩ CL =8pF 200ns/DIV 100mV STEP 6V STEP 1µs/DIV FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE EL5420T (14LD TSSOP/SOIC shown) 1 VOUTA RLA CLA VOUTD 14 VOUTA 0 VOUTD RLD 0 VINA+ 2 VINA- VIND- 13 3 VINA+ VIND+ 12 VIND+ 49.9 49.9 4 VS+ + 4.7µF Vs- Vs+ 11 0.1µF 49.9 6 VINC+ VINB+ VINC- VINB- 4.7µF 10 VINC+ 9 0 49.9 0 7 VOUTB VS+ 0.1µF 5 VINB+ VOUTC VOUTB 8 VOUTC RLC RLB CLB CLD CLC FIGURE 27. BASIC TEST CIRCUIT Pin Descriptions EL5420T 14 LD TSSOP, 14 LD SOIC 16 LD QFN PIN NAME 1 15 VOUTA 2 1 3 FUNCTION EQUIVALENT CIRCUIT Amplifier A Output (Reference Circuit 1) VINA- Amplifier A Inverting Input (Reference Circuit 2) 2 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 2) 4 3 VS+ 5 4 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 2) 6 5 VINB- Amplifier B Inverting Input (Reference Circuit 2) 7 6 VOUTB Amplifier B Output (Reference Circuit 1) 8 7 VOUTC Amplifier C Output (Reference Circuit 1) 9 8 VINC- Amplifier C Inverting Input (Reference Circuit 2) 10 Positive Power Supply FN6838.0 September 25, 2009 EL5420T Pin Descriptions (Continued) EL5420T 14 LD TSSOP, 14 LD SOIC 16 LD QFN PIN NAME 10 9 VINC+ 11 10 VS- 12 11 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 2) 13 12 VIND- Amplifier D Inverting Input (Reference Circuit 2) 14 14 VOUTD Amplifier D Output (Reference Circuit 1) 13, 16 NC pad Thermal Pad FUNCTION EQUIVALENT CIRCUIT Amplifier C Non-Inverting Input (Reference Circuit 2) Negative Power Supply No Connect Functions as a heat sink. Connects to most negative potential, VS- VS+ VS+ VOUTx VINx GND CIRCUIT 1 11 VSVS- CIRCUIT 2 FN6838.0 September 25, 2009 EL5420T Applications Information VS = ±2.5V, TA = +25°C, AV = 1, VINx = 6VP-P, RL = 10kΩ to GND The EL5420T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL5420T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability, and is unity gain stable. The EL5420T features a slew rate of 12V/µs. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 12MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. 1V/DIV Product Description OUTPUT 100µs/DIV INPUT FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT Operating Voltage, Input and Output Capability The EL5420T can operate on a single supply or dual supply configuration. The EL5420T operating voltage ranges from a minimum of 4.5V to a maximum of 19V. This range allows for a standard 5V (or ±2.5V) supply voltage to dip to -10%, or a standard 18V (or ±9V) to rise by +5.5% without affecting performance or reliability. The EL5420T output typically swings to within 50mV of positive and negative supply rails with load currents of ±5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 29 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from ±5V supply with a 10kΩ load connected to GND. The input is a 10VP-P sinusoid and the output voltage is approximately 9.9VP-P. Refer to the “Electrical Specifications” Table beginning on page 3 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the “Typical Performance Curves” on page 6. INPUT OUTPUT 5V/DIV The input common-mode voltage range of the EL5420T extends 500mV beyond the supply rails. Also, the EL5420T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than 0.5V, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 28 shows the input voltage driven 500mV beyond the supply rails and the device output swinging between the supply rails. VS = ±5V, TA = +25°C, AV = 1, VINx = 10VP-P, RL = 10kΩ to GND 100µs/DIV FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND Output Current The EL5420T is capable of output short circuit currents of 200mA (source and sink), and the device has built-in protection circuitry which limits the short circuit current to ±200mA (typical). To maintain maximum reliability the continuous output current should never exceed ±70mA. This ±70mA limit is determined by the characteristics of the internal metal interconnects. Also, see “Power Dissipation” on page 13 for detailed information on ensuring proper device operation and reliability for temperature and load conditions. Unused Amplifiers It is recommended that any unused amplifiers be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground. Thermal Shutdown The EL5420T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +165°C (typical) the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by 15°C (typical) the device automatically turns 12 FN6838.0 September 25, 2009 EL5420T ON the outputs by putting them in a low impedance (normal) operating state. Driving Capacitive Loads where: • i = 1 to 4 (1, 2, 3, 4 corresponds to Channel A, B, C, D respectively) As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL5420T. A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL5420T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between 1Ω to 10Ω). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. • VS = Total supply voltage (VS+ - VS-) • VS+ = Positive supply voltage • VS- = Negative supply voltage • ISMAX = Maximum supply current per amplifier (ISMAX = EL5420T quiescent current ÷ 4) • VOUT = Output voltage • ILOAD = Load current Device overheating can be avoided by calculating the minimum resistive load condition, RLOAD, resulting in the highest power dissipation. To find RLOAD set the two PDMAX equations equal to each other and solve for VOUT/ILOAD. Reference the package power dissipation curves, Figures 30 and 31, for further information. Power Dissipation The maximum power dissipation allowed in a package is determined according to Equation 1: JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 SOIC14 θJA = 120°C/W 1.04W 1.0 Power Dissipation (W) With the high-output drive capability of the EL5420T amplifiers, it is possible to exceed the +150°C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL5420T in the application. Proper load conditions will ensure that the EL5420T junction temperature stays within a safe operating region. 0.8 962mW 833mW QFN16 θJA = 130°C/W 0.6 0.4 TSSOP14 θJA = 150°C/W 0.2 T JMAX – T AMAX P DMAX = --------------------------------------------θ JA (EQ. 1) 0.0 0 25 50 75 85 100 125 150 Am bie nt Te m pe ra ture (°C) where: • TJMAX = Maximum junction temperature FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE • TAMAX = Maximum ambient temperature • ΘJA = Thermal resistance of the package JEDEC JESD51-7 HIGH EFFECTIVE THERMAL • PDMAX = Maximum power dissipation allowed P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] (EQ. 2) when sourcing, and: 3.0 2.66W QFN16 θJA = 47°C/W 2.5 Power Dissipation (W) The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or: 2.0 1.5 SOIC14 θJA = 88°C/W 1.42W TSSOP14 θJA = 100°C/W 1.25W 1.0 0.5 P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] (EQ. 3) 0.0 0 25 50 75 85 100 125 150 Am b ie n t T e m p e ra tu re (°C) when sinking, FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 13 FN6838.0 September 25, 2009 EL5420T Power Supply Bypassing and Printed Circuit Board Layout The EL5420T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the VS- pin is connected to ground) a 4.7µF capacitor should be placed from VS+ to ground, then a parallel 0.1µF capacitor should be connected as close to the amplifier as possible. One 4.7µF capacitor may be used for multiple devices. For dual supply operation the same capacitor combination should be placed at each supply pin to ground. For the QFN package, with exposed thermal pad, the pad should be connected to the lowest potential, VS-, to optimize thermal and operating performance. PCB vias should be placed below the device’s exposed thermal pad to transfer heat to the VS- plane and away from the device. Revision History DATE REVISION 9/25/09 FN6838.0 14 CHANGE Initial Release FN6838.0 September 25, 2009 EL5420T Small Outline Package Family (SO) A D h X 45¬ (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL ‚Äö 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4¬¨¬®¬ DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 15 FN6838.0 September 25, 2009 EL5420T QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN38 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN24 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 16 FN6838.0 September 25, 2009 EL5420T Thin Shrink Small Outline Package Family (TSSOP) 0.25 M C A B D MDP0044 A THIN SHRINK SMALL OUTLINE PACKAGE FAMILY (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 0.20 C B A 1 (N/2) B 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE 0.10 M C A B b 0.10 C N LEADS H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. SIDE VIEW 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL ‚Äú 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0¬× - 8 DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN6838.0 September 25, 2009