mm2850

HA-2850 SPICE
Operational Amplifier Macro-Model
TM
Macro Model
June 1998
MM2850.1
Introduction
tle
2
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0
E
raal
pliroel)
tho
ds
r-
EX1 , D1 and D2 model output current limiting. IH and IL are
the power supply currents. DPH , DPL and GPS vary the supply currents based on the op amp’s output current. DL , DH ,
ECC and EEE provide voltage clamping on the output to simulate the typical output voltage swing. Some effects of output
parasitics due to package capacitance and inductance are
lumped with the poles.
Model Description
Parameters Not Modeled
Input Stage
To maintain a simple macro-model, not all op amp parameters
are modeled. Most of the parameters not modeled are listed
below:
DP and D N represent the differential input resistance. Input
bias currents are created by l1 and offset current is modeled
with FA . Source VN represents the input offset voltage. No
input parasitics due to package capacitance and lead
inductance are included.
Gain Stage
pon,
i-
Poles and Zeros
This application note describes the SPICE macro-model for
the HA-2850, a wide bandwidth op amp. The model was
designed to be compatible with the well known SPICE program developed by the University of California in hope that
most simulation software vendors follow this basic format
and syntax. A schematic of the macro-model, the SPICE net
listing and various simulated performance curves are
included. The macro-model schematic includes node numbers to help relate the SPICE listing to the schematic. The
model is designed to emulate a typical rather than a worst
case part. Most AC and DC parameters are simulated.
Significant poles and zeros are included to give the most
accurate AC and transient simulation with minimum
complexity.
The HA-2850 macro-model uses a combination of complex
zeros modeled with an RLC network plus a pole-zero pair
and three additional poles using RC networks.
Output Stage
• Temperature Effects
• Differential Voltage Restrictions
• Input Voltage and Current Noise
• Common Mode Restrictions
G2 , R2 , CC , GOL , and RD simulate open loop gain. CC is
the macro-model dominant pole capacitor, which effects
slew rate and bandwidth.
• Tolerances for Monte Carlo Analysis
• Power Supply Range
or,
()
CI
k
1
1-888-INTERSIL or 321-724-7143
| Intersil and Design is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2001, All Rights Reserved
Macro Model MM2850
Spice Listing
*
* COPYRIGHT (C) 1998 INTERSIL CORPORATION
* ALL RIGHTS RESERVED
*
* HA-2850 MacroModel
* Rev: 06-10-98 Alan Erzinger and Jeff Lies
*
* Pinout: +In -In Vcc Vee Out
*
.SUBCKT HA2850 1 2 4 5 3
.MODEL DP D IS=+1.0E-17 N=+2.3872
.MODEL DN D IS=+1.0E-17
N=+2.3872
.MODEL DV D IS=+1.6146E-13 N=.2
.MODEL D1 D IS=1E-9 N=1
.MODEL D2 D IS=1E-9 N=+1.0
.MODEL DX D IS=1E-20 N=+30.0
*
*
Input Stage
* Value of source VN models VIO and may be
adjusted as desired.
*
VP 1 6 0
VN 2 7 +1.0E-03
I1 8 0 +1.004E-05
FA 2 0 VN +2.156998E-01
DP 6 8 DP
DN 7 8 DN
FP 9 0 VP +6.03E+02
FN 0 9 VN +6.029E+02
GC 0 9 8 0 +2.7311E-06
GPP 9 0 4 0 +3.4326E-06
GPN 9 0 5 0 +3.8529E-06
IRX 0 9 -3.0927E-06
RT 9 0 1.0
*
2
*
Poles and Zeros
EZZ 10 0 9 0 1.0
VZZ 10 11 0.0
CZZ 11 0 1E-12
RZZ 11 0 1E+07
FCZ 0 12 VZZ 1.0
RCZ 12 13 +1.7407E+01
LCZ 13 14 +6.1841E-08
CCZ 14 0 1E-12
RXZ 14 0 1E+07
EP1 15 0 12 0 1.0
RP1 15 16 +7.2967
RZ1 16 17 +1.99
CP1 17 0 1E-10
EP2 18 0 16 0 1.0
RP2 18 19 +4.5486
CP2 19 0 1E-10
EP3 20 0 19 0 1.0
RP3 20 21 +8.0
CP3 21 0 1E-10
EP4 30 0 21 0 1.0
RP4 30 31 +8.0
CP4 31 0 1E-10
*
*
Output Stage
G2 0 22 31 0 1.0
R2 22 0 +5.0577E+02
CC 22 23 +1.590E-11
GOL 23 0 22 0 +2.0104E+03
RD 23 0 +6.07E-01
DH 23 24 DV
DL 25 23 DV
ECC 24 0 POLY 1 4 0 -2.4167 1.0
EEE 25 0 POLY 1 5 0 +2.5203 1.0
IH 4 0 +7.5422E-03
IL 0 5 +7.5382E-03
GPS 26 0 23 3 +2.6302E-02
DPH 4 26 DX
DPL 26 5 DX
D1 23 27 D1
D2 27 23 D2
EX1 27 0 POLY 2 23 0 3 0 0.0
+7.8568E-01
+2.1269E-01
RO 23 3 +3.80195E+01
.ENDS HA2850
Macro Model MM2850
Macro-Model Schematic
-INPUT
DN
8
VN
7
-
+
11
-
EZZ
RCZ
12
CZZ
13
FCZ
RZZ
-
GPN
+
+
-
-
FP
RT
FA
VZZ
GPP
+
9
+
-
0
+
5
IRX
FN
GC
LCZ
14
15
C CZ
R XZ
+
RP1
EP1
-
DP
I1
10
4
RZ1
16
17
18
+
CP1
-
+
6
9
VEE
2
1
VP
VCC
RP2
19
20
+
CP2
EP2
-
+INPUT
RP3
EP3
21
CP3
-
0
23
5
25
CC
22
EEE
+
ECC
24
+
26 GPS
+ 23
+
+
R2
EP4
DL
GOL
RD
CP4 +
-
DH
-
31
IH
D2
D1
DPL
DPH
-
4
27
RO
+
EX1
-
RP4
-
30
IL
3
-
G2
3
GND
OUTPUT
Model Performance
90
50
PHASE
GAIN
25
135
0
180
OUTPUT VOLTAGE (mV)
45
PHASE (DEGREES)
75
GAIN (dB)
150
0
100
100
50
0
-50
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 1. GAIN/PHASE RESPONSE vs FREQUENCY
3
0
50
100
150
TIME (ns)
FIGURE 2. SMALL SIGNAL RESPONSE
200
Macro Model MM2850
Model Performance
(Continued)
OUTPUT VOLTAGE (V)
12
8
4
0
-4
0
50
100
150
200
TIME (ns)
FIGURE 3. LARGE SIGNAL RESPONSE
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