Wideband, Low Noise, Low Distortion, Fixed Gain, Differential Amplifier ISL55211 Features The ISL55211 is a wideband, differential input to differential output amplifier offering 3 possible internal gain settings. Using fixed 500Ω internal feedback resistors, the amplifier may be configured for a differential gain of 2, 4 or 5V/V depending on which combination of input pins are connected to the signal source. Internal feedback capacitors controls the signal bandwidth to be a constant 1.4GHz in all gain settings. • 3 Fixed Gain Options . . . . . . . . . . . . . . . . . . . . . . . 2, 4, or 5V/V • Constant Bandwidth Over Gain . . . . . . . . . . . . . . . . . . 1.4GHz • Differential Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 5,600V/µs • 2VP-P, 2-tone IM3 (200Ω) 100MHz . . . . . . . . . . . . . . -103dBc • Low Differential Output Noise (Gain 5V/V) . . . . . . <12nV/√Hz • Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 3.0V to 4.2V Ideally suited for AC-coupled data acquisition applications, the output DC common mode voltage is controlled through an external VCM pin or left to default to 1.2V above the negative supply pin. Where the differential signal source is AC-coupled, the input common mode voltage will equal the output common mode voltage. • Quiescent Power (3.3V Supply) . . . . . . . . . . . . . . . . . .115mW Applications • Low Power, High Dynamic Range ADC Interface • Differential Mixer Output Amplifier Intended for very high dynamic range ADC interface applications, the ISL55211 offers 5600V/µs differential slew rate, <12nV/√Hz output noise, and >100dBc SFDR to >100MHz for 2VP-P 2-tone 3rd order intermodulation. Its balanced architecture effectively suppresses even order distortion terms - an important issue for very wide band 1st Nyquist zone ADC interface applications. Minimum gain operation of 2V/V (6dB) with <1dB peaking ensures stable performance over-temperature. It's ultra high differential slew rate of 5600V/µs provides adequate performance margin for large signal application through 500MHz. • SAW Filter Pre/Post Driver • Fixed Gain Coax Receiver Related Devices • ISL55210 - External Gain Set Version • ISLA112P50 - 12-bit, 500MSPS ADC (<500mW) • ISLA214P50 - 14-bit, 500MSPS ADC (<850mW) Related Literature The ISL55211 requires only a single 3.3V (max. 4.2V) power supply and 35mA quiescent current, providing a very low power solution (115mW). Further power savings are possible using the optional power shutdown control - where the quiescent current can be reduced to <0.4mA. A companion device, the ISL55210, offers similar performance where the feedback and gain resistors are external. Both are available in a 16 Ld TQFN (Pb-free) package and are specified for operation over the -40°C to +85°C ambient temperature range. • AN1649 - “Designer’s guide to the ISL55210 and ISL55211 Evaluation Boards” +3.3V ISLA214P50 (850mW) 35mA (115mW) 10 + 120nH 1:2 ISL55211 VCM 50 ADT4-1T 180mVP-P For ADC -1dBFS 1.2V 1:1.4 22pF VADC 300 G = 5V/V 120nH - 10 20 log 50 VADC = 20dB Vi VCM 8pF GAIN (dB) Vi 14Bit 500MSPS ADT2-1T 50 23 20 17 14 11 8 5 2 -1 -4 -7 -10 -13 1M HIGH GAIN, VERY LOWPOWER, ADC INTERFACE WITH 3RD ORDER OUTPUT FILTER MEASURED FREQUENCY RESPONSE 10M 100M 1G FREQUENCY (Hz) FIGURE 1. TYPICAL APPLICATION CIRCUIT June 21, 2011 FN7868.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL55211 Pin Configuration ISL55211 (3x3 16 LD TQFN) TOP VIEW VIN2- 1 VIN1- 2 GND VS+ VCM GND 16 15 14 13 348 500 750 0.2pF - 140 12 VO+ 11 NC 10 NC 9 VO- VCM VIN1+ 3 140 + 0.2pF 750 VIN2+ 4 500 348 5 GND Pin Descriptions 6 VS+ 7 8 GND GND Pd PIN NUMBER SYMBOL DESCRIPTION 1 VIN2- Balanced Differential Input for Av = 6dB, strapped to VIN1- for Av = 14dB 2 VIN1- Balanced Differential Input for Av = 12dB, strapped to VIN2- for Av = 14dB 3 VIN1+ Balanced Differential Input for Av = 12dB, strapped to VIN2+ for Av = 14dB 4 VIN2+ Balanced Differential Input for Av = 6dB, strapped to VIN1+ for Av = 14dB 5, 8, 13, 16 GND Supply Ground (thermal pad electrically connected) 6, 15 VS+ Positive Power Supply (3.0V~4.2V) 7 Pd Power-down: Pd = logic low. Puts part into low power mode; Pd = logic high or open for normal operation 9 VO- Inverting Amplifier Output 10, 11 NC No Internal Connection 12 VO+ Non-Inverting Amplifier Output 14 VCM Common-mode Voltage Input Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL55211IRTZ 5211 ISL55211IRTZ-EVAL1Z Evaluation Board TEMP RANGE (°C) -40 to +85 PACKAGE (Pb-free) 16 Ld 3x3 TQFN PKG. DWG. # L16.3x3D NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55211. For more information on MSL please see techbrief TB363. 2 FN7868.0 June 21, 2011 ISL55211 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage from VS+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VS+ +0.3V to GND-0.3V Power Dissipation. . . . . . . . . . . . . . . . . . . . See Thermal Conditions Section ESD Rating ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . 3500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Latch up (Per JESD-78; Class II; Level A) . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 16 Ld TQFN Package (Notes 4, 5) . . . . . . . 63 16.5 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Max. Continuous Operating Junction Temperature . . . . . . . . . . . . .+135°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications VS+ = +3.3V Test Conditions: G = 12dB, VCM = open, VO = 2VP-P, RL = 200Ω differential, TA = +25°C, differential input, differential output, input and output referenced to internal default VCM (1.2V nominal) unless otherwise specified. PARAMETER CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT TESTED AC PERFORMANCE Small-Signal Bandwidth (4-port S parameter, Test Circuit 2) G = 6dB, VO = 100mVP-P 1.6 GHz G = 12dB, VO = 100mVP-P 1.4 GHz G = 14dB, VO = 100mVP-P 1.4 GHz Bandwidth for 0.1-dB Flatness G = 12dB, VO = 2VP-P (Figure 17) 150 MHz Large-Signal Bandwidth G = 12dB, VO = 2VP-P 1.2 GHz Gain Accuracy G = 6dB, RL = Open 1.96 2 2.04 V/V * G = 12dB, RL = Open 3.88 4 4.12 V/V * G = 14dB, RL = Open 4.8 5 5.2 V/V Slew Rate (Differential) 5,600 V/µs Differential Rise/Fall Time 2-V step (simulated) 0.22 ns 2nd-order Harmonic Distortion, Test Circuit 1, 15dB Gain f = 20MHz, VO = 2VP-P -110 dBc f = 50MHz, VO = 2VP-P -98 dBc f = 100MHz, VO = 2VP-P -85 dBc f = 20MHz, VO = 2VP-P -120 dBc f = 50MHz, VO = 2VP-P -110 dBc f = 100MHz, VO = 2VP-P -100 dBc 2nd-order Intermodulation Distortion, Test Circuit 1, 15dB Gain fc = 70MHz, 200kHz spacing (2VP-P envelope) -89 dBc fc = 140MHz, 200kHz spacing (2VP-P envelope) -78 dBc 3rd-order Intermodulation Distortion, Test Circuit 1, 15dB Gain fc = 70MHz, 200kHz spacing (2VP-P envelope) -104 dBc fc = 140MHz, 200kHz spacing (2VP-P envelope) -92 dBc 11.2 nV/√Hz 3rd-order Harmonic Distortion, Test Circuit 1, 15dB Gain Output Voltage Noise Test Circuit 1, total gain 15dB, ADT2-1T DC PERFORMANCE (Internal Nodes) Input Offset Voltage 3 TA = +25°C -1.4 ±0.1 +1.4 mV TA = -40°C to +85°C -1.6 ±0.1 +1.6 mV * FN7868.0 June 21, 2011 ISL55211 Electrical Specifications VS+ = +3.3V Test Conditions: G = 12dB, VCM = open, VO = 2VP-P, RL = 200Ω differential, TA = +25°C, differential input, differential output, input and output referenced to internal default VCM (1.2V nominal) unless otherwise specified. (Continued) PARAMETER CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT µV/°C Average Offset Voltage Drift TA = -40°C to +85°C ±3 Input Bias Current TA = +25°C, positive current into the pin +50 +120 µA TA = -40°C to +85°C +50 +140 µA Average Bias Current Drift TA = -40°C to +85°C 200 Input Offset Current TA = +25°C -5 TA = -40°C to +85°C -6 Average Offset Current Drift TA = -40°C to +85°C ±1 TESTED * nA/°C +5 µA +6 µA * nA/°C ±8 INPUT Common-mode Input Range High Internal Nodes 1.7 Common-mode Input Range Low Internal Nodes 1.1 Common-mode Rejection Ratio f < 10MHz, common mode to differential output 56 Differential Input Impedance VIN1- Connected to VIN2VIN1+ Connected to VIN2+ V * V * 75 dB * 200 Ω 2.35 V * V * VP-P * OUTPUT (Pins 9 AND 12) Maximum Output Voltage Minimum Output Voltage Differential Output Voltage Swing Each output (with 200Ω differential load) Linear Operation 2.15 TA = +25°C 3.04 TA = -40°C to +85°C 2.95 Differential Output Current Drive RL = 10Ω [sourcing or sinking] Closed-loop Output Impedance f < 10MHz, differential 0.45 40 0.63 3.8 V 45 mA 0.6 Ω * OUTPUT COMMON-MODE VOLTAGE CONTROL (Pin 14) Small-signal Bandwidth From VCM pin to Output VCM 30 MHz Slew Rate Rising/Falling 150 V/µs Gain VCM input pin 1.0V to 1.4V 0.995 0.999 V/V * -8 ±1 +8 mV * 1.18 1.2 1.22 V * Output Common-Mode Offset from CM Input CM Default Voltage Output VCM with VCM pin floating CM Input Bias Current At control pin CM Input Voltage Range At control pin CM Input Impedance At control pin 2 0.9 µA 1.9 15 || 50 V * kΩ || pF POWER SUPPLY Specified Operation Voltage Quiescent Current TA = +25°, VS+ = 3.3V, VS- = 0V TA = -40°C to +85°C Power-supply Rejection (PSRR) VS+ 3.0V to 4.5V range f < 10MHz [PSRR to differential output] POWER-DOWN (Pin 7) Referenced to GND Enable Voltage Threshold Assured on above 1.55V Disable Voltage Threshold Assured off below 0.54V 4 3 3.3 4.2 V * 33 35 37 mA * 30.5 35 39.5 mA 50 67 1.3 0.54 0.7 1.55 dB * V * V * FN7868.0 June 21, 2011 ISL55211 Electrical Specifications VS+ = +3.3V Test Conditions: G = 12dB, VCM = open, VO = 2VP-P, RL = 200Ω differential, TA = +25°C, differential input, differential output, input and output referenced to internal default VCM (1.2V nominal) unless otherwise specified. (Continued) MIN (Note 6) TYP TA = +25°C 0.2 0.3 TA = -40°C to +85°C 0.15 PARAMETER CONDITIONS Power-down Quiescent Current Input Bias Current PD = 0V, current positive into pin -5 1 MAX (Note 6) UNIT TESTED * 0.4 mA 0.45 mA +5 µA 2 || 5 Input Impedance MΩ || pF Turn-on Time Delay Measured to output on 200 ns Turn-off Time Delay Measured to output off 400 ns NOTE: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. TABLE 1. ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN SETTINGS ISL55211 500 RG + VI 1:n 50 INPUT VO RT RG - INPUT XFMR TURNS RATIO INTERNAL RG VALUE (Ω) GAIN (V/V) VO/VI GAIN (dB) VO/VI RT VALUE (Ω) TO GET 50Ω MATCH 1:1.4 250 2.8 9 122 1:1.4 125 5.6 15 162 1:1.4 100 7 17 192 1:2 250 4 12 333 1:2 125 8 18 1020 1:2 100 10 20 Open 500 FIGURE 2. INTENDED CONFIGURATION 5 FN7868.0 June 21, 2011 ISL55211 Typical Performance Curves Vs+ = 3.3V, TA ≈ +25°C, unless otherwise noted. 3 3 2 2 1 Av = 2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 0 -1 -2 -3 Av = 5 -4 Av = 4 -5 -6 -7 -8 TEST CIRCUIT #1 VO = 500mVP-P 100M FREQUENCY (Hz) -3 -5 -6 3 2 NORMALIZED GAIN (dB) -1 -2 Av = 5 -5 Av = 4 -6 -7 -9 Av = 2 0 -1 -2 -3 Av = 5 -4 -5 -6 -7 TEST CIRCUIT #1 VO(P-P) = 3VP-P -8 100M FREQUENCY (Hz) Av = 4 TEST CIRCUIT #1 VO(P-P) = 3VP-P -8 10M 1G 1 Av = 2 -4 100M FREQUENCY (Hz) FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE WITH ADT4-1WT INPUT TRANSFORMER 2 -3 Av = 4 TEST CIRCUIT #1 VO = 500mVP-P -9 10M 3 0 Av = 5 -4 1G 1 NORMALIZED GAIN (dB) -2 -8 FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE WITH ADT2-1T INPUT TRANSFORMER -9 10M 1G 100M FREQUENCY (Hz) 1G FIGURE 5. LARGE SIGNAL FREQUENCY RESPONSE WITH ADT2-1T INPUT TRANSFORMER FIGURE 6. LARGE SIGNAL FREQUENCY RESPONSE WITH ADT4-1WT INPUT TRANSFORMER 25 20 20 NOISE FIGURE (dB) 16 15 10 GAIN = 17dB GAIN = 15dB 5 14 12 10 8 6 GAIN = 20dB GAIN = 18dB 4 2 TEST CIRCUIT #1 0 GAIN = 12dB 18 GAIN = 9dB NOISE FIGURE (dB) -1 -7 -9 10M Av = 2 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) FIGURE 7. NOISE FIGURE WITH ADT2-1T INPUT TRANSFORMER 6 0 TEST CIRCUIT #1 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) FIGURE 8. NOISE FIGURE WITH ADT4-1WT INPUT TRANSFORMER FN7868.0 June 21, 2011 ISL55211 Typical Performance Curves Vs+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued) HD2, HD3 SPURIOUS (dBc) -65 -70 -60 HD2 of 3VP-P TEST CIRCUIT 1 RL = 200Ω GAIN = 15dB TEST CIRCUIT 1 RL = 200Ω -70 GAIN = 15dB HD2 of 2VP-P IM2, IM3 SPURIOUS (dBc) -60 -75 HD3 of 3VP-P -80 -85 -90 -95 -100 HD3 of 2VP-P -105 HD2 of 1VP-P -110 50M 100M 150M FREQUENCY (Hz) IM2 of 2VP-P -90 -100 IM3 of 2VP-P 100 150 FREQUENCY (MHz) -60 -80 -70 HD2 of 9dB HD2 of 15dB HD2 of 17dB -85 -90 HD3 of 17dB -95 -100 IM2, IM3 SPURIOUS (dBc) HD2, HD3 SPURIOUS (dBc) -60 -75 HD3 of 15dB -105 TEST CIRCUIT 1 VO = 1VP-P EACH TONE IM2 of 15dB -80 -90 IM3 of 9dB -100 IM3 of 15dB -110 100M 150M FREQUENCY (Hz) -120 50M 200M 100M 150M FREQUENCY (MHz) HD2 of 200Ω HD2 of 500Ω -70 -80 -90 HD3 of 500Ω -100 -110 50M HD3 of 100Ω 100M 150M FREQUENCY (Hz) FIGURE 13. HD2, HD3 vs DIFFERENTIAL LOAD 7 IM2 of 100Ω IM2 of 50Ω -70 IM2 of 200Ω -80 -90 -100 IM2 of 500Ω -110 IM3 of 50Ω -120 HD3 of 200Ω HD3 of 50Ω TEST CIRCUIT 1 -60 IM2, IM3 SPURIOUS (dBc) HD2, HD3 SPURIOUS (dBc) -60 HD2 of 100Ω -50 HD2 of 50Ω TEST CIRCUIT 1 GAIN = 15dB 200M FIGURE 12. IM2 AND IM3 vs GAIN FIGURE 11. HD2, HD3 vs GAIN -50 IM2 of 9dB IM2 of 17dB IM3 of 17dB HD3 of 9dB -110 50M 200 FIGURE 10. IM2 AND IM3 vs OUTPUT SWING FIGURE 9. HD2, HD3 vs OUTPUT SWING TEST CIRCUIT 1 -65 RL = 200Ω VO = 2VP-P -70 IM3 of 1VP-P IM3 of 3VP-P -120 50 200M IM2 of 1VP-P -80 -110 HD3 of 1VP-P IM2 of 3VP-P IM3 of 500Ω IM3 of 100Ω IM3 of 200Ω 200M -130 50M 100M 150M FREQUENCY (Hz) 200M FIGURE 14. IM2, IM3 vs DIFFERENTIAL LOAD FN7868.0 June 21, 2011 ISL55211 Typical Performance Curves Vs+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued) 180 TEST CIRCUIT 1 WITH ADT2-1T INPUT PHASE OF 15dB PHASE (°) 1.4 140 1.3 120 15 14 1.6 1.5 PHASE OF 9dB 160 1.7 1.2 GROUP DELAY OF 17dB 100 1.1 GROUP DELAY OF 15dB 80 10 GROUP DELAY OF 9dB 30 50 70 90 110 130 150 170 190 OUTPUT SPOT NOISE (nV/√Hz) PHASE OF 17dB GROUP DELAY (ns) 200 GAIN = 17dB 13 GAIN = 15dB 12 11 10 9 8 7 1.0 5 1M 10M FREQUENCY (Hz) FREQUENCY (MHz) 3 12 10 0 OUTPUT IMPEDANCE (Ω) NORMALIZED GAIN (dB) 6dB -3 12dB -6 14dB -9 10 TEST CIRCUIT 2 SIMULATED 8 6 GAIN = 2 4 100 1000 0 1M 5000 10M 100M 1000M FREQUENCY (Hz) FREQUENCY (MHz) FIGURE 17. SMALL SIGNAL FREQUENCY RESPONSE FIGURE 18. DIFFERENTIAL OUTPUT IMPEDANCE -50 DIFFERENTIAL TO COMMON MODE CONVERSION (dBc) 3 0 -3 GAIN (dB) GAIN = 5 GAIN = 4 2 TEST CIRCUIT 2 NO TRANSFORMERS -6 100M FIGURE 16. DIFFERENTIAL OUTPUT NOISE vs GAIN FIGURE 15. PHASE AND GROUP DELAY vs GAIN -12 TEST CIRCUIT 1 ADT2-1T OUTPUT NOISE INCLUDING 50Ω SOURCE NOISE GAIN = 9dB 6 200mVP-P 10mVP-P -9 -12 -15 -18 TEST CIRCUIT 3 COMMON MODE AC OUTPUT -21 1 10 FREQUENCY (MHz) 100 200 FIGURE 19. VCM PIN INPUT FREQUENCY RESPONSE TO OUTPUT COMMON MODE 8 -55 TEST CIRCUIT 3 VO(P-P) DIFFERENTIAL IS 2VP-P 9dB -60 15dB -65 -70 17dB -75 -80 2M 20M FREQUENCY (Hz) 200M FIGURE 20. OUTPUT BALANCE ERROR FN7868.0 June 21, 2011 ISL55211 Typical Performance Curves Vs+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued) 0.15 1.5 TEST CIRCUIT #1 WITH ADT2-1T 100MHz SQUARE WAVE INPUT TEST CIRCUIT #1 WITH ADT2-1T 100MHz SQUARE WAVE INPUT OUTPUT INPUT 0.05 0 -0.05 INPUT 0.5 0 -0.5 -0.10 -0.15 OUTPUT 1.0 AMPLITUDE (V) AMPLITUDE (V) 0.10 -1 0 2 4 6 8 10 12 14 16 18 -1.5 20 0 2 4 6 8 10 12 14 16 18 20 TIMEBASE (ns) TIMEBASE (ns) FIGURE 21. SMALL SIGNAL STEP RESPONSE FIGURE 22. LARGE SIGNAL RESPONSE -14.4 100MHz 100MHz OUTPUT OUTPUT OUTPUT vs INPUT (dBc) -14.6 ENABLED ENABLED PD DISABLED DISABLED 2VP-P -14.8 -15.0 -15.2 100mVP-P -15.4 -15.6 -15.8 -16.0 1M TEST CIRCUIT 1 2µs/DIV 2µs/DIV FIGURE 23. ENABLE/DISABLE TIMES (2µs/DIV) 95 OUTPUT 100M PSRR TO VO (DIFFERENTIAL) 2.0 85 1.5 1.0 INPUT 0.5 0 -0.5 -1.0 -1.5 75 CMRR TO VO (DIFFERENTIAL) 65 55 45 -2.0 -2.5 10M FREQUENCY (Hz) FIGURE 24. SHUTDOWN FEED-THROUGH PSRR/CMRR (dB) INPUT AND OUTPUT WAVEFORMS (V) 2.5 TEST CIRCUIT 1 WITH ADT2-1T INPUT OUTPUT VP-P RELATIVE TO INPUT VP-P TEST CIRCUIT 1 0 20 40 60 80 100 120 TIME (ns) 140 FIGURE 25. OVERDRIVE RECOVERY 9 160 180 200 35 TEST CIRCUIT 1 SIMULATED EXACT EXTERNAL R’s 1 10 100 1000 FREQUENCY (MHz) FIGURE 26. PSRR/CMRR TO DIFFERENTIAL VO FN7868.0 June 21, 2011 ISL55211 Typical Performance Curves Vs+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued) 6 5 4 MAXIMUM DIFFERENTIAL VP-P OUTPUT USING DEFAULT VCM 3 2 INTERNALLY SET VCM 1 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 SUPPLY VOLTAGE (V) FIGURE 27. DEFAULT VCM AND MAX VOPP vs SUPPLY VOLTAGE Applications SUPPLY CURRENT (mA) OUTPUT DEFAULT VCM AND MAX DIFFERENTIAL VOPP (V) TEST CIRCUIT 1 45 44 TEST CIRCUIT 1 43 TA = +85°C 42 41 40 39 38 TA = +25°C 37 36 35 TA = -40°C 34 33 32 31 30 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 SINGLE SUPPLY VOLTAGE (V) FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE shown in Table 1, gives a 9dB to 20dB operating gain range in approximately 3dB steps. Basic Operation The ISL55211 is a very wideband, voltage feedback based, differential amplifier including an output common mode control loop and optional power shutdown feature. Intended for very low distortion differential signal driving, this internally fixed gain device provides 3 possible gain settings by simply picking the input side connections as shown in Table 1. Including internal compensation, the ISL55211 holds a constant bandwidth over gain settings. Most applications are intended for AC-coupled I/O using a single 3.3V supply and an input transformer. The internal resistor values have been scaled up slightly to require an external termination element along with the two internal resistors where a 50Ω differential input match is desired. This does increase the output noise slightly but narrows up the input VSWR tolerance and lowers the added loading of the feedback resistors improving SFDR. Where DC-coupled differential I/O operation is desired, the ISL55211 can be connected directly to the source as long as the internal input common mode range limits are observed (1.1V to 1.7V for a 3.3V single supply operation). For a DC-coupled, single to differential requirement, consider the ISL55210. This device is an external resistor version of the ISL55211 where the flexibility in the external resistors will enable single to differential operation. For a ground referenced input signal, this will require a negative supply when using the ISL55210. Most applications behave as a differential inverting op amp design. There is therefore an input gain resistor on each side of the inputs that must be driven. The 3 possible connections to the two pairs of input pins will give a 100Ω, 125Ω, or 250Ω input resistor on each side. Combined with the two input turns ratio's 10 The device can be powered down to < 400µA supply current using the optional disable pin. To operate normally, this pin should be asserted high using a simple logic gate to +VCC or tied high through a 10kΩ resistor to +VCC. When disabled, the power dissipation drops to < 1mW but, due to the inverting op amp type architecture, the input signal will feed-forward through the feedback and gain resistors giving limited isolation. Application and Characterization Circuits Test Circuit 1 of Figure 29 forms a starting point for many of the characterization curves for the ISL55211. Since most lab sources and measurement devices are single-ended, this circuit converts to differential at the input through a wideband transformer and would also be a typical application circuit coming from a single-ended source. Assuming the source is a 50Ω impedance, the internal RG resistors and external RT are set to provide both the input termination and the gain. Since the inverting summing nodes act as virtual ground points for AC signal analysis, the total termination impedance across the input transformer secondary will be (2*RG)||RT. Setting this equal to n2*RS will give a matched input impedance inside the bandwidth of the transformer (where "n" is the turns ratio). The amplifier gain is fixed by the selected input RG element and the internal 500Ω feedback resistors. While the ISL55211 is internally a Voltage Feedback Design (VFA) to give the lowest possible noise, internal compensation caps hold the bandwidth over gain setting approximately constant at 1.4GHz. For wider small signal bandwidth at lower gains, consider the ISL55210, which provides >2.2GHz at a gain of 12dB. FN7868.0 June 21, 2011 ISL55211 +3.3V 115mW 35mA 10k 500 RG 1:1.4 RT Vi 1µF ADT21T or ADT41Wt 85 0.2pF + 50 PD 1µF 200 35 VO VCM 1µF 0.1µF 35 - 0.2pF RG 50 1:1 Vm ADT11WT Where just the amplifier is tested, a 4-port network analyzer is used and the very simple test circuit of Figure 30 is implemented. This is used to measure the differential S21 curves vs gain of Figure 17 and as a simulation circuit for the differential output impedance vs gain of Figure 18. Changing the gain is a simple matter of adjusting the connections to the four input RG connections resistors, as shown in Table 1. This circuit depends on the two AC-coupled source 50Ω of the 4 port network analyzer and presents an AC-coupled differential 100Ω load to the amplifier as the input impedance of the remaining two ports of the network analyzer. +3.3V 1µF 85 RF 500 ISL55211 RG 50 10k PD 50 + FIGURE 29. TEST CIRCUIT 1 Working with a transformer coupled input as shown in Figure 29, or with two DC blocking caps from a differential source, means the output common mode voltage set by either the default internal VCM setting, or a voltage applied to the VCM control pin, will also appear as the input common mode voltage. This provides a very easy way to control the ISL55211 I/O common mode operating voltages for an AC-coupled signal path. The internal common mode loop holds the output pins to VCM and, since there is no DC path for an ICM current back towards the input in Figure 29, that VCM setting will also appear as the input common mode voltage. It is useful, for this reason, to leave any input transformer secondary centertap unconnected. The internally set VCM voltage is referenced from the negative supply pin. With a single 3.3V supply, it is very close to 1.2V but will change with total supply voltage across the device as shown in Figure 27. Most of the characterization curves starting with Figure 29 then get different gains by changing the connections to the two pairs of input RG connections, as shown on the pin configuration drawing on page 2. Two input turns ratios are intended for Test Circuit 1; either a 1:1.4 turns ratio (ohms ratio of 2) or a 1:2 turns ratio (ohm ratio of 4). The specific transformers shown in Figure 29 are representative of broadband RF transformers but alternate devices and manufacturers of these turns ratio devices are certainly applicable. The output side of this test circuit presents a differential 200Ω load while converting the differential to single-ended through a resistive attenuator and a 1:1 transformer. This inserts approximately a 17dB insertion loss that is removed to report the characteristic curves. For load tests below the 200Ω shown in Figure 29, a simple added shunt resistor is placed across the output pins. For loads > 200Ω, the series and shunt load R's are adjusted to show that total load (including the 50Ω measurement load reflected through the 1:1 output measurement port transformer) and provide an apparent 50Ω differential source to that transformer. This output side transformer is for measurement purposes only and is not necessary for final applications circuits. There are output interface designs that do benefit from a transformer as part of the signal path as shown in Figure 1. In that case, the 1:1:4 output side transformer becomes part of a filter design and recovers the filter insertion loss from the amplifier output pins to the ADC inputs. 11 1/2 of a 4-port S-parameter 1/2 of a 4-port S-parameter VCM RT 50 50 RG RF ISL55211 FIGURE 30. TEST CIRCUIT 2 4-PORT S-PARAMETER MEASUREMENTS Using this measurement allows the small single bandwidth of just the ISL55211 to be exposed. Many of the other measurements are using I/O transformers that are limiting the apparent bandwidth to a reduced level. Figure 17 shows the 3 normalized differential S21 curves for the possible internal gains of 9dB, 14dB and 15dB. The small signal bandwidth is remaining nearly constant at 1.4GHz due to the internal capacitive feedback network. The closed loop differential output impedance of Figure 18 is simulated using Figure 30 in ADS. This shows a relatively low output impedance (< 1Ω through 100MHz) constant with signal gain setting. Typical FDA outputs show a closed loop output impedance that increases with signal gain setting. The ISL55211 holds a more constant response due to internal design elements unique to this device. Common mode output measurements are made using the circuit in Figure 31. Here, the outputs are summed together through two 100Ω resistors (still a 200Ω differential load) to a center point where the average, or common mode, output voltage may be sensed. This is coupled through a 1µF DC blocking capacitor and measured using 50Ω test equipment. The common mode source impedance for this circuit is the parallel combination of the 2-100Ω elements, or 50Ω. Figure 19 uses this circuit to measure the small and large signal response from the VCM control pin to the output common mode. This pin includes an internal 50pF capacitor on the default bias network (to filter supply noise when there is no connection to this pin), which bandlimits the response to approximately 30MHz. This is far lower than the actual bandwidth of the common mode loop. Figure 20 uses this output FN7868.0 June 21, 2011 ISL55211 CM measurement circuit with a large signal (2VP-P) differential output voltage (generated through the Vi path of Figure 31) to measure the differential to common mode conversion - often called the "Output Balance Error" for an FDA. ISL55211 500 RS +3.3V PD Vi 50 ADT2-1T 1:1.4 500 + 75 INPUT 1:n 1µF V CM 500 V CM Input RS 1:1.4 -> CX2045NL 1:2 -> CX2032 50 RG VO RT 100 Output V CM 1µF 1µF + Vi 10k RG RG - RG 500 100 ISL55211 50 FIGURE 31. TEST CIRCUIT #3 COMMON MODE AC OUTPUT MEASUREMENTS Single Supply, Input Transformer Coupled, Design Considerations The characterization circuit of Figure 29 shows one possible input stage interface that offers several advantages. Where AC coupling is adequate, the circuit of Figure 29 simplifies the input common mode voltage control. If the source coming into this stage is single-ended, the input transformer provides a zero power conversion to differential. The two gain resistors (RG in Figure 29) provide both a portion of the input termination impedance and the gain element for the amplifier. For 50Ω systems, these RG resistors are too high with the turns ratios shown in Figure 29 to provide the full match and an external RT resistor is required. This RT element goes away at the highest gain setting using a 1:2 input turns ratio transformer. It is also possible to adapt this circuit to other input characteristic impedances. Figure 32 shows a 75Ω example similar to Figure 2 while Table 2 shows the necessary external R values and resulting gains. FIGURE 32. 75Ω IMPEDANCE IMPLEMENTATIONS Here, the sum of the two internal RG resistors at the higher two gain settings is too low to retain a match for the 1:2 input step up case. There, a pair of external series resistors are added to get the total differential input impedance up to 300Ω on the secondary side of the transformer and the RT element goes to infinity. These two conditions are not particularly useful but Figure 32 shows how to implement the full range of internal conditions with the two turns ratios considered in Table 2. Figure 32 also shows a pair of alternate input transformer types from Pulse Engineering particularly suitable to the 75Ω case. TABLE 2. EXTERNAL RESISTORS FOR A 75Ω INPUT IMPEDANCE DESIGN ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN SETTINGS INPUT XFMR TURNS RATIO INTERNAL RG VALUE (Ω) GAIN (V/V) VO/VI GAIN (dB) VO/VI 1:1.4 250 2.8 9 214 0 1:1.4 125 5.6 15 375 0 1:1.4 100 7 17 600 0 1:2 250 4 12 750 0 1:2 125 6.7 16.5 Open 25 1:2 100 6.7 16.5 Open 50 EXTERNAL EXTERNAL RT VALUE RS VALUE (Ω) (Ω) This input interface also simplifies the input common mode control. The VCM pin controls the output common mode voltage. In most DC-coupled FDA applications, the input common mode voltage is determined by both this output common mode and the source signal. In a configuration like Figure 29, there is no path for a common mode current to flow from output to input, so the input common mode voltage equals the output. A similar effect could be achieved with just two blocking caps on the two RG resistors. A DC-coupled, single to differential, configuration will also have a common mode input that is moving with the input signal. Converting to just a differential signal at the amplifier, as in Figure 29, removes any input signal related artifacts from the input common mode making the ISL55211 behave as a differential only VFA amplifier. There is only a very small differential error signal at the inputs set by the loop gain, as in a 12 FN7868.0 June 21, 2011 ISL55211 normal single-ended VFA application, but no common mode signal related terms. Amplifier I/O Range Limits maximum differential VP-P swing will be 4x this 0.6V single-ended limit or 2.4VP-P. Where +Vs is increased, the limit then becomes the 0.9V below VCM, but then the absolute maximum differential VP-P is then 4 x 0.9V to 3.6VP-P. So for instance, to get this maximum output swing, increase the supply voltage until +Vs - 1.5V > VCM + 0.9V. If we assume a VCM voltage of 1.3V for instance, then 1.3V + 0.9V + 1.5V = 3.7V will give an unclipped 3.6VP-P output capability. The VP-P reported in Figure 27 is an asymmetrically clipped maximum swing. Going 10% above this 3.7V target to 4.1V will be within the recommended operating range and give some tolerancing headroom that would also suggest the VCM voltage be moved up to approximately 1.5V, which coincides with the default output VCM from Figure 27. Operating at +4.1V single supply in a Figure 29 type configuration will give the maximum linear differential output swing of 3.6VP-P. The ISL55211 is intended principally to give the lowest IM3 performance on the lowest power for a differential I/O application. The amplifier will work DC coupled and over a relatively wide supply range of 3.0V to 4.2V supplies. The outputs have both a differential and common mode operating range limits while the input pins internal to the ISL55211 have a common mode voltage operating range. For single supply operation, the -Vs pins are at ground as is the exposed metal pad on the underside of the package. The ISL55211 can operate split supply where then -Vs will be a negative supply voltage and the exposed metal pad is either connected to this negative supply or left unconnected on an insulating board layer. The differential inputs internal to the ISL55211 also have operating range limits relative to the supply voltages. Operating in an AC-coupled circuit like Figure 29 will produce an input common mode voltage equal to the outputs. The inputs can operate with full linearity with this VCM voltage down to 1.1V above the -Vs supply. On the default 1.2V output VCM on +3.3V supplies this gives a 100mV guardband on the input VCM voltages. Overriding the default VCM by applying a control voltage to the VCM pin should be done with care in going towards the negative supply due to this limit. On the + side, the maximum input VCM above the -Vs supply is 2V so there is more room to move the output VCM up than down from the default value. Briefly, the I/O and VCM limits are as follows: Power Supply, Shutdown, and Thermal Considerations The examples shown are using the transformer to convert from single to differential. However, if the source is already differential, these same transformer input circuits can drive the transformer differentially still providing impedance scaling if needed and common mode rejection for both DC and AC common mode issues. A good example would be differential mixer outputs or SAW filter outputs. Those differential sources could also be connected into the ISL55211 RG resistors through blocking caps as well eliminating the input transformer. The AC termination impedance for the differential source will then be the sum of the two RG resistors when simple blocking caps are used. 1. Maximum VCM setting = -Vs +2V 2. Input common mode operating range (internal summing junction pints of the ISL55211) of -Vs + 1.1V or to output VCM + 0.5V 3. Output VO minimum (on each side) is either -Vs + 0.3V or output VCM - 0.9V 4. Output VO maximum (on each side) is +Vs - 1.5V The output swing limits are often asymmetrical around the VCM voltage. The maximum single-ended swings are set by these two limits - VO(MIN) is either -Vs + 0.3V or VCM - 0.9V, whichever is less. So for instance, on a single 3.3V supply with the default VCM voltage of 1.2V, these two limits give the same result and the output pins can swing down to 0.3V above -Vs (= 0V). If, however, the VCM pin is raised to 1.5V, then the minimum output voltage will become 1.5V - 0.9V = 0.6V. VO(MAX) is set by a headroom limit to the positive supply to be -VO(MAX) = +Vs - 1.5V. Again, on a 3.3V single supply and the default 1.2V VCM setting, this means the maximum referenced to ground output pin voltages can be 3.3V - 1.5V = +1.8V or 0.6V above the default VCM voltage. Using these default conditions, and the maximum positive excursion of 0.6V above the 1.2V output VCM setting, the 13 The ISL55211 is intended for single supply operation from 3.0V to 4.2V with an absolute maximum setting of 4.5V. The 3.3V supply current is trimmed to be nominally 35mA at +25°C ambient. Figure 28 shows the supply current for nominal +25°C and -40°C to +85°C operation over the specified maximum supply range. The input stage is biased from an internal voltage reference from the negative supply giving the exceptional 90dB low frequency PSRR shown in Figure 26. Since the input stage bias is from a re-regulated internal supply, a simple approach to single +5V operation can be supported as shown in Figure 33. Here, a simple IR drop from the +5V supply will bring the operating supply voltage for the ISL55211 into its allowed range. Figure 33 shows example calculations for the voltage range at the ISL55211 +Vs pin assuming a ±5% tolerance on the +5V supply and a 35mA to 55mA range on the total supply current. Considering the 34mA to 44mA quiescent current range from Figure 28 over the -40°C to +85°C ambient, and the 3.4V to 4.4V supply voltage range assumed here, this is designing for a 1mA to 11mA average load current, which should be adequate for most intended application loads. Good supply decoupling at the device pins is required for this simple solution to still provide exceptional HD performance. FN7868.0 June 21, 2011 ISL55211 +85°C maximum operating ambient from Figure 27, we get 4.5V*45mA*+120°C/W = +24°C rise above +85°C or approximately +109°C operating TJ maximum - still well below the specified Absolute Maximum operating junction temperature of +135°C. +5V ±5% 35 24.3 3.4 55mA 4.4V + 2.2µF 10nF Noise Analysis 10k RF PD + Vi RO RG C IN 1:n V CM VO RG RO RF The decompensated voltage feedback design of the ISL55211 provides very low input voltage and current noise. Based on the ISL55210, these internal noise terms are 0.85nV/√Hz differential voltage noise and a 5pA/√Hz current noise term on each side. Since the ISL55211 is an internally fixed gain version, these internal noise terms will produce only a few set of output noise values. Figure 34 shows the analysis model for just the ISL55211 with no input transformer while Table 3 shows the resulting output and input referred differential spot noise voltages using Equation 1. ISL55211 4kTR F * RF FIGURE 33. OPERATING FROM A SINGLE +5V SUPPLY 500 The ISL55211 includes a power shutdown feature that can be used to reduce system power dissipation when signal path operation is not required. This pin (Pd) is referenced to -Vs and must be asserted low to activate the shutdown feature. When not used, a 10kΩ external resistor to +Vs should be used to assert a high level at this pin. Digital control on this pin can be either an open collector output (using that 10kΩ pull-up) or a CMOS logic line running off the same +Vs as the amplifier. For split supply operation, the Pd pins must be pulled to below -Vs + 0.54V to disable. 4kTR G The very low internal power dissipation of the ISL55211, along with the excellent thermal conductivity of the TQFN package when the exposed metal pad is tied to a conductive plate, reduces the TJ rise above ambient to very modest levels. Assuming a nominal 115mW dissipation and using the 63°C/W measured thermal impedance from Junction to ambient, gives a rise of only 0.115*63 = 7.2°C. Operation at elevated ambient temperatures is easily supported given this very low internal rise to junction. The maximum internal junction temperatures would occur at maximum supply voltage, +85°C maximum ambient operating, and where the TQFN exposed pad is not tied to a conductive layer. Where the TQFN must be mounted with an insulating layer to the exposed metal plate, such as in a split supply application, device measurements show an increased thermal impedance junction to ambient of +120°C/W. Using this, and a maximum quiescent internal power on 4.5V absolute maximum, which shows 45mA for 14 + RG en * 4kTR G R G Since the ISL55211 operates as a differential inverting op amp, there is only modest signal path isolation when disabled, as shown in Figure 24. The inputs include 2 pairs of back to back low capacitance diodes intended to protect any subsequent devices from large input signals during shutdown. Those diodes limit the maximum overdrive voltage across the input to approximately 1.0V in each polarity. The internal RG resistors of Test Circuit 1 limit the current into those diodes under this condition. The supply current in shutdown does not reduce to zero as internal circuitry is still active to hold the output common mode voltage at the VCM voltage even during shutdown. This is intended to hold the ISL55211 outputs near the desired common mode output level during shutdown. This improves the turn on characteristic and keeps those output voltages in a safe range for downstream circuitry. iN * eO ISL55211 iN * 500 * 4kTR F RF FIGURE 34. AMPLIFIER ONLY NOISE MODEL With equal feedback and gain resistors, the total output noise expression becomes very simple. This is shown as Equation 1. (EQ. 1) e 0 ( e N∗ NG ) 2 + 2 ( i N R F ) 2 + 2 ( 4kTR F NG ) The NG term in this equation is the Noise Gain = 1 + RF/RG. The last term in Equation 1 captures both the RF and RG resistor noise terms. Table 3 evaluates this expression for the 3 possible internal gains with a fixed 500Ω internal feedback. nV/√HZ TABLE 3. OUTPUT AND INPUT SPOT NOISE FROM EQUATION 1 FOR THE 3 GAINS OF THE ISL55211 INPUT REFERRED RG (Ω) GAIN V/V NOISE GAIN V/V EO nV/√Hz ENI nV/√Hz 250 2 3 8.19 4.09 125 4 5 10.51 2.63 100 5 6 11.60 2.32 FN7868.0 June 21, 2011 ISL55211 TABLE 4. OUTPUT NOISE AND INPUT REFERRED EQUIVALENT NOISE FOR THE TRANSFORMER COUPLED INPUT INPUT REFERRED ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN SETTINGS INPUT XFMR TURNS RATIO INTERNAL RG VALUE (Ω) GAIN (V/V) VO/VI GAIN (dB) VO/VI EXTERNAL RT VALUE (Ω) TOTAL GAIN RESISTOR FOR NG (Ω) NOISE GAIN V/V EO nV/√Hz ENI nV/√Hz 1:1.4 250 2.8 9 122 277.48 2.80 7.94 2.834811 1:1.4 125 5.6 15 162 155.92 4.21 9.62 1.718338 1:1.4 100 7 17 192 132.88 4.76 10.25 1.46452 1:2 250 4 12 333 312.48 2.60 7.68 1.920066 1:2 125 8 18 1020 208.61 3.40 8.67 1.083876 1:2 100 10 20 1008 200.00 3.50 8.79 0.879492 Adding an input transformer can improve the input referred noise by adding a noiseless voltage gain. Starting from Test Circuit 1 of Figure 29, and assuming the source shows a matched broadband source RS that will be matched by the input referred parallel combination of 2*RG||RT, a noise gain analysis circuit can be developed as shown in Figure 35. RF 500 RT/2 RG + n2RS/2 ISL55211 n2RS/2 - Driving Cap and Filter Loads Most applications will drive a resistive or filter load. The ISL55211 is robust to direct capacitive load on the outputs up to approximately 10pF. For frequency response flatness, it is best to avoid any output pin capacitance as much as possible - as the capacitance increases, the high frequency portion of the ISL55211 (>1GHz) response will start to show considerable peaking. No oscillations were observed up through 10pF load on each output. For AC-coupled applications, an output network that is a small series resistor (10 to 50Ω) into a blocking capacitor is preferred. This series resistor will isolate parasitic capacitance to ground from the internally closed loop output stage of the amplifier and de-que the self resonance of the blocking capacitors. Once the output stage sees this resistive element first, the remaining part of a passive filter design can be done without fear of amplifier instability. Driving ADC's RG 500 RT/2 RF FIGURE 35. NOISE GAIN MODEL FOR THE TRANSFORMER COUPLED INPUT CIRCUIT OF FIGURE 29 Stepping through the 3 gain settings with two input transformers will allow the noise gain to be calculated for the circuit of Figure 35, which is all that is needed in Equation 1 to arrive at an output differential noise (since RF is fixed at 500Ω). Doing this gives Table 4. The signal gain is taken from the input of the transformer for this analysis and shows the total input referred noise going below 0.9nV at the highest gain setting here. While this analysis is including the approximate 0.9nV noise of a 50Ω source R, that noise is assumed to be divided down by 2 to the input of the transformer, which explains the total input referred noise showing up as less than just a 50Ω resistor. The total output differential noise goes below 9nV/√Hz at the higher gains settings using this input transformer technique. For even lower noise, consider the ISL55210 where the input RT element is generally not required. In that case, simply setting RG to the desired input Z and adjusting RF to the desired gain will give an output noise that is slightly lower than shown previously for the same input transformer due to the removal of the RT element. 15 Many of the intended applications for the ISL55211 are as a low power, very high dynamic range, last stage interface to high performance ADC's. The lowest power ADC's, such as the ISLA214P50 shown on the front page, include an innovative "Femto-Charge™" internal architecture that eliminates op amps from the ADC design and only passes signal charge from stage to stage. This greatly reduces the required quiescent power for these ADC's but then that signal charge has to be provided by the external circuit at the two input pins. This appears on an ADC like the ISLA112P50 as a clock rate dependent common mode input current that must be supplied by the interface circuit. At 500MHz, this DC current is 1.3mA on each input for the 14-bit ISLA214P50. Most interfaces will also include an interstage noise power bandlimiting filter between the amplifier and the ADC. This filter needs to be designed considering the loading of the amplifier, any VCM level shifting that needs to take place, the filter shape, and this Icm issue into the ADC input pins. Here are 4 example topologies suitable for different situations. 1. AC-coupled, broadband RLC interstage filter design. This approach lets the amplifier operate at its desired output common mode, then provides the ADC common mode voltage and current through a bias path as part of the filters designs last stage R values. The Vb is set to include the IR loss from that voltage to the ADC inputs due to the ICM current. FN7868.0 June 21, 2011 ISL55211 ADC LS +3.3V RT VCM1 IN+ CB RS ISL55211 ICM CT RIN VB 1.2V CB RS LS RT CIN CT 3. AC-coupled with output side transformer. This design includes an output side transformer, very similar to ADC characterization circuits. This approach allows a slightly lower amplifier output swing (if N>1 is used) and very easy 2nd or 3rd order low pass responses to be implemented. It also provides the ICM and VCM bias to the ADC through the transformer centertap. This approach would be attractive for higher ADC input swing targets and more aggressive noise power bandwidth control needs. Figure 1 on page 1 is an example showing this approach. IN- Rt >Rs Vb −Icm ×Rt =Vcm2 ICM ADC +3.3V VCM2 ICM CB RS ISL55211 IN+ RT 1:N CT FIGURE 36. AC- COUPLED BROADBAND RLC INTERSTAGE FILTER DESIGN 2. AC-coupled, higher frequency range interstage filter design. This design replaces the RT resistors in Figure 35 with large valued inductors and implements the filter just using shunt resistors at the end of the RLC filter. In this case, the ADC VCM can be tied to the centerpoint of the bias path inductors (very much like a Bias-T) to provide the common mode voltage and current to the ADC inputs. These bias inductors do limit the low frequency end of the operation where, with 1µH values, operation from 10MHz to 200MHz is supported using the approach of Figure 37. ADC LS +3.3V RS ISL55211 VCM1 ICM CB LP IN+ RS CB LS RIN 1.2V RIN CT RT INICM RT<30 VCM2 2ICM FIGURE 38. AC-COUPLED WITH OUTPUT SIDE TRANSFORMER 4. DC-coupled with ADC VCM and ICM provided from the amplifier. Here, DC to very high frequency interstage low pass filter can be provided. Again, the RS element must be low to reduce the IR drop from the VCM of the converter, which now shows up on the output of the ISL55211, to the ADC input pins. ADC CIN LS +3.3V LP CT ICM Lp >>Ls IN+ RS ISL55211 INICM CIN CB RS CT RT 1.2V VCM1 CT VCM2 FIGURE 37. AC-COUPLED, HIGHER FREQUENCY RLC INTERSTAGE FILTER DESIGN RT RIN VCM RS LS CIN CT IN- Rs ≤30Ω ICM VCM2 FIGURE 39. DC-COUPLED WITH A VCM VOLTAGE FROM THE ADC 16 FN7868.0 June 21, 2011 ISL55211 Layout Considerations The ISL55211 pinout is organized to isolate signal I/O along one axis of the package with ground, power and control pins on the other axis. Ground and power should be planes coming into the upper and lower sides of the package (see “Pin Configuration” on page 2). The signal I/O should be laid out as tight as possible. The ground pins and package backside metal contact should be connected into a good ground plane. The power supply should have both a large values electrolytic cap to ground, then a high frequency ferrite beads, then 0.01µF SMD ceramic caps at the supply pins. Some improvement in HD2 performance may be experienced by placing and X2Y cap between the two Vs+ pins and ground underneath the package on the board back side. This is 3 terminal device that is included in the Evaluation board layout. Evaluation Board (Rev. C) Test circuit 1 (Figure 29) is implemented on an Evaluation Board available from Intersil. This board includes a number of optional features that not populated as the board is delivered. The full Evaluation circuit is shown in Figure 40 where unloaded (optional) elements are shown in green. The nominal supply voltage for the board and device is a single 3.3V supply. From this, the ISL55210, ISL55211 generates an internal common mode voltage of approximately 1.2V. That voltage can be overridden by populating the two resistors and potentiometer shown as R19 to R21 above. 17 The primary test purpose for this board is to implement different interstage differential passive filters intended for the ADC interface along with the ADC input impedances. The board is delivered with only the output R's loaded to give a 200Ω differential load. This is done using the two 85Ω resistors as R9 and R10, then the 4 0Ω elements (R10, R12, R24, and R25) and finally the two shunt elements R13 and R14 set to 35.5Ω. Including the 50Ω measurement load on the output side of the 1:1 transformer reflecting in parallel with the two 35Ω resistors takes the nominal AC shunt impedance to 71Ω||50Ω = 29.3Ω. This adds to the two 85Ω series output elements to give a total load across the amplifier outputs of 170Ω + 29.3Ω = 199.3Ω. To test a particular ADC interface RLC filter and converter input impedance, replace R11 and R12 with RF chip inductors, load C10 and C11 with the specified ADC input capacitance and R26 with the specified ADC differential input R. With these loaded, the remaining resistive elements (R24, R25, R13, R14) are set to hit a desired total parallel impedance to implement the desired filter (must be < than the ADC input differential R since that sits in parallel with any "external" elements) and achieve a 250Ω source looking into each side of the tap point transformer. This Evaluation board includes a user's manual showing a number of example circuits and tested results and is available on the Intersil web site on the ISL55211 Product Information Page. FN7868.0 June 21, 2011 +Vs C1001 + BEAD 4.7uF GND R21 VCC L1 200ohm/DNP C3 C1002 1.0uF C2 100nF R19 1k/DNP 100nf R17 R18 200ohm R1001 R1002 R1003 R1004 R1005 0ohm/DNP 0ohm/DNP 0ohm/DNP 0ohm/DNP 0ohm/DNP 50ohm C9 100nf TEST POINT R20 200ohm/DNP C10 DNP 13 15 14 R26 DNP TP1 18 16 C11 DNP R70ohm 0ohm R8DNP Cterm2 2.2pF 4 GND Vs+ Vcm NC Vi+ NC Fb- Vo- 11 1uf C6 9 1uf 85ohm R11 0ohm R24 0ohm 0ohm/DNP R10 R12 R25 85ohm 0ohm 0ohm R15 50ohm C5 100nf TP2 DIFPROBE R16 100nf 50ohm Pd 1 R22 50ohm 2 3 NC VCC 5 A GND Y R13 35.5ohm C8 4 FN7868.0 June 21, 2011 74AHC1G04 FIGURE 40. ISL55210, ISL55211 SINGLE INPUT TRANSFORMER EVALUATION BOARD REV C R14 35.5ohm OUT ADT1-1WT R28 ISL55210/11 C4 R1006 R1007 R1008 R1009 R1010 R1011 0ohm/DNP 0ohm/DNP 0ohm/DNP 0ohm/DNP 0ohm/DNP 0ohm/DNP R9 10 GND R4 Vi- C7 12 8 3 Vo+ Pd R2 DNP 2 Fb+ 1uf R27 0ohm ISL55211 R23 0ohm R60ohm 1 Vs+ 0ohm R0 162ohm 1uF R5DNP 7 R3 GND ADT2-1T 6 C1 5 IN Cterm1 2.2pF GND U1 R1 DNP ISL55211 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION June 21, 2011 FN7868.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL55211 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN7868.0 June 21, 2011 ISL55211 Package Outline Drawing L16.3x3D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 3/10 4X 1.50 3.00 A 12X 0.50 B 13 6 PIN 1 INDEX AREA 16 6 PIN #1 INDEX AREA 12 3.00 1 1.60 SQ 4 9 (4X) 0.15 0.10 M C A B 5 8 16X 0.40±0.10 TOP VIEW 4 16X 0.23 ±0.05 BOTTOM VIEW SEE DETAIL “X” 0.10 C 0.75 ±0.05 C 0.08 C SIDE VIEW (12X 0.50) (2.80 TYP) ( 1.60) (16X 0.23) C 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. (16X 0.60) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.25mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. JEDEC reference drawing: MO-220 WEED. either a mold or mark feature. 20 FN7868.0 June 21, 2011