INTERSIL ISL55210

Wideband, Low-Power, Ultra-High Dynamic Range
Differential Amplifier
ISL55210
Features
The ISL55210 is a very wide band, Fully Differential Amplifier
(FDA) intended for high dynamic range ADC input interface
applications. This voltage feedback FDA design includes an
independent output common mode voltage control.
• Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . 4.0GHz
• Input Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . 0.85nV/√(Hz)
• Differential Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 5,600V/µs
• 2VP-P, 2-tone IM3 (200Ω) 100MHz . . . . . . . . . . . . . . -109dBc
Intended for very high dynamic range ADC interface
applications, at the lowest quiescent power (115mW), the
ISL55210 offers a 4.0GHz Gain Bandwidth Product with a very
low input noise of 0.85nV/√(Hz). In a balanced differential I/O
configuration, with 2VP-P output into a 200Ω load configured
for a gain of 15dB, the IM3 terms are <-100dBc through
110MHz. With a minimum operating gain of 2V/V (6dB), the
ISL55210 supports a wide range of higher gains with minimal
BW or SFDR degradation. Its ultra high differential slew rate of
5,600V/µs ensures clean large signal SFDR performance or a
fast settling step response.
• Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 3.0V to 4.2V
• Quiescent Power (3.3V Supply) . . . . . . . . . . . . . . . . . .115mW
Applications
• Low Power, High Dynamic Range ADC Interface
• Differential Mixer Output Amplifier
• SAW Filter Pre/Post Driver
• Differential Comms-DAC Output Driver
Related Products
The ISL55210 requires only a single 3.3V (max 4.2V) power
supply with 35mA typical quiescent current. This industry
leading low current solution can be further reduced when
needed using the optional power shutdown to <0.4mA supply
current. External feedback and gain setting resistors give
maximum flexibility and accuracy. A companion device, the
ISL55211, includes on-chip feedback and 3 possible gain
setting connections where an internally fixed gain solution is
preferred. The ISL55210 is available in a leadless, 16 Ld TQFN
package and is specified for operation over the -40ºC to +85ºC
ambient temperature range.
• Coming Soon: ISL55211 - Fixed Gain Version of the
ISL55210
• ISLA112P50 - 12-bit, 500MSPS ADC (<500mW)
• Coming Soon: ISLA214P50 - 14-bit, 500MSPS ADC
(<850mW)
+3.3V
10k
100
Vi
50
35mA
(115mW)
495
105MHz SINGLE TONE
180mVpp for -1dBFS
180MHz SPAN
40.2
+
V+
33nH
0.1µF
1:2
0.1µF
SNRFS = 64.9dBFS
500kHz
PD
Vcm
ISL55210
210
33nH
0.1µF
ADT4-1WT
-
20pF
V-
500MSPS
20log (
495
Vdiff
Vi
HD2 = -83dBc
HD3 = -84dBc
ENOBFS = 10.5 Bits
Vdiff
40.2
100
12 Bit
<500mW
20pF
210
Vb
ISLA112P50
CLK
) = 17.3dB gain
FIGURE 1. TYPICAL APPLICATION CIRCUIT
March 2, 2011
FN7811.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL55210
Pin Configuration
ISL55210
(3x3 16 LD TQFN)
TOP VIEW
FB+
1
V i-
2
GND
V S+
V CM
GND
16
15
14
13
-
12
V O+
11
NC
10
NC
9
V O-
V CM
V i+
3
FB-
4
+
5
6
GND
V S+
7
8
GND
PD
GND
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
FB+
2
Vi-
Inverting Amplifier Input
3
Vi+
Noninverting Amplifier Input
4
FB-
Negative Output Feedback resistor connection
5, 8, 13, 16
GND
Supply Ground (Thermal Pad Electrically Connected)
6, 15
VS+
Positive power supply (3.0V~4.5V)
7
PD
Power-down: PD = logic low puts part into low power mode, PD = logic high or 1kΩ to VS+ for normal operation
9
VO-
Inverting Amplifier Output
10, 11
NC
No Internal Connection
12
VO+
Noninverting Amplifier Output
14
VCM
Common-mode Voltage Input
Positive Output Feedback resistor connection
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
TRANSPORT
MEDIA, QUANTITY
PKG.
DWG. #
ISL55210IRTZ
5210
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL55210IRTZ-T7
5210
-40 to +85
16 Ld 3x3 TQFN
Tape and Reel, 1000
L16.3x3D
ISL55210IRTZ-T7A
5210
-40 to +85
16 Ld 3x3 TQFN
Tape and Reel, 250
L16.3x3D
ISL55210IRTZ-EVALZ
Evaluation Board (Contact local sales)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55210. For more information on MSL please see techbrief TB363.
2
FN7811.0
March 2, 2011
ISL55210
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage from VS+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VS+ +0.3V to GND-0.3V
Power Dissipation (See “Power Supply, Shutdown, and Thermal
Considerations” on page 13)
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . 3500V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Latch up (Per JESD-78; Class II; Level A) . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld TQFN Package (Notes 4, 5) . . . . . . .
63
16.5
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Maximum Continuous Operating Junction Temperature. . . . . . . . . . .+135°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VS+ = +3.3V Test Conditions: G = 12dB, VCM = open, VO = 2VP-P, RF = 200Ω, RL = 200Ω differential, TA = +25°C,
differential input, differential output, input and output referenced to internal default VCM (1.2V nominal) unless otherwise specified.
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
TESTED
(Note 7)
AC PERFORMANCE
Small-Signal Bandwidth (4-port S
parameter, Test Circuit #2)
G = 12dB, VO = 100mVP-P
2,200
MHz
G = 18dB, VO = 100mVP-P
700
MHz
G = 24dB, VO = 100mVP-P
300
MHz
Gain-Bandwidth Product
G = 18dB
4.0
GHz
Bandwidth for 0.1-dB Flatness
G = 12dB, VO = 100mVP-P
200
MHz
Large-Signal Bandwidth
G = 12dB, VO = 2VP-P
1.2
GHz
5,600
V/µs
Slew Rate (Differential)
Differential Rise/Fall Time
2-V step
0.17
ns
2nd-order Harmonic Distortion
f = 20MHz, VO = 2VP-P
-105
dBc
f = 50MHz, VO = 2VP-P
-88
dBc
f = 100MHz, VO = 2VP-P
-72
dBc
f = 20MHz, VO = 2VP-P
-120
dBc
f = 50MHz, VO = 2VP-P
-107
dBc
f = 100MHz, VO = 2VP-P
-95
dBc
fc = 70MHz, 200kHz spacing (2VP-P envelope)
-80
dBc
fc = 140MHz, 200kHz spacing (2VP-P envelope)
-68
dBc
fc = 70MHz, 200kHz spacing (2VP-P envelope)
-102
dBc
fc = 140MHz, 200kHz spacing (2VP-P envelope)
-94
dBc
Input Voltage Noise
f > 1MHz, Differential
0.85
nV/√HZ
Input Current Noise
f > 1MHz, Each Input
5.0
pA/√HZ
3rd-order Harmonic Distortion
2nd-order Intermodulation Distortion
3rd-order Intermodulation Distortion
3
FN7811.0
March 2, 2011
ISL55210
Electrical Specifications
VS+ = +3.3V Test Conditions: G = 12dB, VCM = open, VO = 2VP-P, RF = 200Ω, RL = 200Ω differential, TA = +25°C,
differential input, differential output, input and output referenced to internal default VCM (1.2V nominal) unless otherwise specified. (Continued)
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
TESTED
(Note 7)
dB
*
*
DC PERFORMANCE
Open-loop Voltage Gain (AOL)
Differential
86
100
Input Offset Voltage
TA = +25°C
-1.4
±0.1
+1.4
mV
TA = -40°C to +85°C
-1.6
±0.1
+1.6
mV
µV/°C
Average Offset Voltage Drift
TA = -40°C to +85°C
±3
Input Bias Current
TA = +25°C, positive current into the pin
+50
+120
µA
TA = -40°C to +85°C
+50
+140
µA
Average Bias Current Drift
TA = -40°C to +85°C
+200
Input Offset Current
TA = +25°C
-5
±1
+5
µA
TA = -40°C to +85°C
-6
±1
+6
µA
TA = -40°C to +85°C
Average Offset Current Drift
*
nA/°C
*
nA/°C
±8
INPUT
Common-mode Input Range High
1.7
Common-mode Input Range Low
V
*
V
*
75
dB
*
1 || 2
kΩ || pF
2.35
V
*
V
*
VP-P
*
1.1
Common-mode Rejection Ratio
f < 10MHz, common mode to differential
output
56
Differential Input Impedance
OUTPUT
Maximum Output Voltage
Minimum Output Voltage
Differential Output Voltage Swing
Each output (with 200Ω differential load)
Linear Operation
2.15
TA = +25°C
3.04
TA = -40°C to +85°C
2.95
Differential Output Current Drive
RL = 10Ω [sourcing or sinking]
Closed-loop Output Impedance
f < 10MHz, differential
0.45
40
0.63
3.8
V
45
mA
0.6
Ω
*
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal Bandwidth
From VCM pin to Output VCM
30
MHz
Slew Rate
Rising/Falling
150
V/µs
Gain
VCM input pin 1.0V to 1.4V
0.995
0.999
V/V
*
-8
±1
+8
mV
*
1.18
1.2
1.22
V
*
Output Common-Mode Offset from CM Input
CM Default Voltage
Output VCM with VCM pin floating
CM Input Bias Current
At control pin
CM Input Voltage Range
At control pin
CM Input Impedance
At control pin
2
0.9
µA
1.9
15 || 50
V
*
kΩ || pF
POWER SUPPLY
Specified Operation Voltage
Quiescent Current
TA = +25°, VS+ = 3.3V, VS- = 0V
TA = -40°C to +85°C
Power-supply Rejection (PSRR) VS+
4
3.0V - 4.5V range
3
3.3
4.2
V
33
35
37
mA
30.5
36
39.5
mA
56
90
dB
*
*
FN7811.0
March 2, 2011
ISL55210
Electrical Specifications
VS+ = +3.3V Test Conditions: G = 12dB, VCM = open, VO = 2VP-P, RF = 200Ω, RL = 200Ω differential, TA = +25°C,
differential input, differential output, input and output referenced to internal default VCM (1.2V nominal) unless otherwise specified. (Continued)
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
TESTED
(Note 7)
1.3
1.55
V
*
V
*
*
POWER-DOWN
Referenced to GND
Enable Voltage Threshold
Assured on above 1.55V
Disable Voltage Threshold
Assured off below 0.54V
0.54
0.7
Power-down Quiescent Current
TA = +25°C
0.2
0.3
0.4
mA
TA = -40°C to +85°C
0.15
0.3
0.45
mA
PD = 0V, current positive into pin
Input Bias Current
Input Impedance
-2
µA
2 || 5
MΩ || pF
Turn-on Time Delay
Measured to output on
200
ns
Turn-off Time Delay
Measured to output off
400
ns
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
7. Parameters denoted by an “*” are ATE tested.
5
FN7811.0
March 2, 2011
ISL55210
Typical Performance Curves
VS+ = 3.3V, TA ≈ +25°C, unless otherwise noted.
18
6
VO = 3VP-P
SLEW LIMITING
15dB
0
15
21dB
-3
-6
-9
GAIN (dB)
NORMALIZED GAIN (dB)
3
27dB
-12
VO = 1VP-P
+2VP-P
9
-15
33dB
-18
6
-21 TEST CIRCUIT #1, RL = 200Ω,
VO = 500mVP-P DIFFERENTIAL
-24
107
108
FREQUENCY (Hz)
TEST CIRCUIT #1
3
106
107
109
6.0
IM2 15dB GAIN
-85
IM2 21dB GAIN
IM3 15dB GAIN
IM3 21dB GAIN
-105
-115
TEST CIRCUIT #1,
RL = 200Ω, VOP-P = 1VP-P EACH TONE
100
150
200
OUTPUT COMPRESSION POINT
(VP-P, DIFFERENTIAL)
-75
-125
50
5.5
RL = 200Ω
5.0
RL = 100Ω
4.5
RL = 50Ω
4.0
3.5
TEST CIRCUIT #1
3.0
50
100
250
150
TEST FREQUENCIES CENTER (MHz)
250
FIGURE 5. OUTPUT V P-P FOR -1dB GAIN COMPRESSION
12
12
11
11
GAIN = 15dB
GAIN = 18dB
NOISE FIGURE (dB)
NOISE FIGURE (dB)
200
FREQUENCY (MHz)
FIGURE 4. IM2 AND IM3 vs GAIN
10
9
GAIN = 21dB
8
10
GAIN = 24dB
9
8
7 TEST CIRCUIT #1 WITH ADT4-1T
INPUT AND RG = 100Ω, RF = 400Ω
7
6
50
109
FIGURE 3. FREQUENCY RESPONSE vs OUTPUT SWING
-65
-95
108
FREQUENCY (Hz)
FIGURE 2. FREQUENCY RESPONSE vs GAIN SETTING
2-TONE IM SPURIOUS (dBc)
INPUT TRANSFORMER
12
TEST CIRCUIT #1
200
350
FREQUENCY (MHz)
FIGURE 6. NOISE FIGURE
6
500
6
50
200
350
500
FREQUENCY (MHz)
FIGURE 7. NOISE FIGURE AT HIGHER GAINS
FN7811.0
March 2, 2011
ISL55210
Typical Performance Curves
HD2 3VP-P
-70
HD2/HD3 SPURIOUS (dBc)
-60
TEST CIRCUIT #1, RL = 200Ω
HD2 2VP-P
-80
HD3 3VP-P
-90
HD2 1VP-P
-100
-110
HD3 1VP-P
IM2 AND IM3 SPURIOUS (dBc)
-60
VS+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued)
TEST CIRCUIT #1, RL = 200Ω
IM2 3VP-P
-70
IM2 2VP-P
-80
IM2 1VP-P
IM3 3VP-P
-90
-100
IM3 2VP-P
-110
HD3 2VP-P
-120
20
-120
200
100
IM3 1VP-P
20
FIGURE 9. IM2 AND IM3 vs OUTPUT SWING
FIGURE 8. HD2/HD3 vs VOPP
HD2, GAIN = 15dB
-80
HD2, GAIN = 21dB
HD2,
GAIN = 27dB
-90
HD3,
GAIN = 15dB
-100
HD3,
GAIN = 21dB
-110
IM2 AND IM3 SPURIOUS (dBc)
HD2 AND HD3 DISTORTION (dBc)
-65
TEST CIRCUIT #1
-70
TEST CIRCUIT #1
-75
IM2 GAIN = 15dB
-85
IM3 GAIN = 21dB
-95
-105
IM3 GAIN = 27dB
IM3 GAIN = 27dB
IM3
GAIN = 21dB
-115
IM3 GAIN = 15dB
HD3, GAIN = 27dB
-120
20
100
-125
20
200
FREQUENCY (MHz)
FIGURE 10. HD2 AND HD3 vs GAIN
100
TEST FREQUENCIES CENTER (MHz)
200
FIGURE 11. IM2 AND IM3 vs GAIN
-50
-50
HD2, 50Ω
-60
-60
HD2, 100Ω
-70
HD2, 200Ω
-80
HD3, 50Ω
-90 HD2, 500Ω
HD3, 100Ω
-100
IM SPURIOUS (dBc)
DISTORTION (dBc)
200
TEST FREQUENCIES CENTER (MHz)
FREQUENCY (MHz)
-60
100
-70
-80
IM3, 100Ω
-90
IM2, 200Ω
-100
HD3, 200Ω
-110
-110
IM2, 100Ω
IM2, 50Ω
IM3, 500Ω
IM2, 500Ω
HD3, 500Ω
-120
20
100
FREQUENCY (MHz)
FIGURE 12. HD2 AND HD3 vs RLOAD
7
IM3, 200Ω
200
-120
20
100
200
CENTER FREQUENCY (MHz)
FIGURE 13. IM2 AND IM3 vs RLOAD
FN7811.0
March 2, 2011
ISL55210
GROUP DELAY, G = 27dB
165
1.6
150
1.5
PHASE, G = 15dB
PHASE (°)
135
1.4
120
1.3
105
1.2
GROUP DELAY
G = 21dB
90
1.1
GROUP DELAY
G = 15dB
75
60
PHASE
G = 21dB
TEST CIRCUIT #2
45
10
40
70
100
130
FREQUENCY (MHz)
10.0
1.7
1.0
PHASE
G = 27dB
VOLTAGE NOISE (nV/√Hz) AND
CURRENT NOISE (pA/√Hz)
180
VS+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued)
GROUP DELAY (ns)
Typical Performance Curves
1.0
EN (DIFFERENTIAL)
0.9
0.8
190
160
IN (EACH INPUT)
0.1
105
RF = 1.6kΩ
-6
RF = 806Ω
-12
-15
-18
4-PORT S21 TEST, TEST CIRCUIT #2
-21
107
108
FREQUENCY (Hz)
CLOSED LOOP OUTPUT IMPEDANCE (Ω)
NORMALIZED DIFFERENTIAL GAIN (dB)
0
-9
10
8
7
6
GAINS 12dB TO 30dB
5
4
3
2
1
0
109
SIMULATED TEST, TEST CIRCUIT #2
9
1
-45
GAIN (dB)
OUTPUT VCM vs VDIFF (dB)
0
200mVP-P
10mVP-P
-9
-12
-15
-18 TEST CIRCUIT #3
COMMON MODE AC OUTPUT
-21
1
10
FREQUENCY (MHz)
100
200
FIGURE 18. VCM PIN INPUT FREQUENCY RESPONSE TO OUTPUT
COMMON MODE
8
100
1000
FIGURE 17. DIFFERENTIAL OUTPUT IMPEDANCE
3
-6
10
FREQUENCY (MHz)
FIGURE 16. SMALL SIGNAL RESPONSE vs GAIN
-3
108
FIGURE 15. INPUT VOLTAGE AND CURRENT SPOT NOISE
RF = 200Ω
RF = 402Ω
-3
107
FREQUENCY (Hz)
FIGURE 14. PHASE AND GROUP DELAY vs GAIN
3
106
TEST CIRCUIT #3
COMMON MODE AC OUTPUT MEASUREMENTS
-50
-55
-60
-65
-70
-75
2
10
TEST FREQUENCY (MHz)
100
200
FIGURE 19. OUTPUT BALANCE ERROR
FN7811.0
March 2, 2011
ISL55210
Typical Performance Curves
VS+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued)
0.15
1.5
OUTPUT
0.05
INPUT
0
-0.05
-0.10
-0.15
OUTPUT
1.0
AMPLITUDE (V)
AMPLITUDE (V)
0.10
0.5
INPUT
0
-0.5
-1.0
TEST CIRCUIT #1, 50MHz SQUARE WAVE INPUT
0
10
20
30
40
-1.5
50
TEST CIRCUIT #1, 50MHz SQUARE WAVE INPUT
0
5
10
15
20
TIMEBASE (ns)
FIGURE 20. SMALL SIGNAL STEP RESPONSE
25
30
TIME (ns)
35
40
45
50
FIGURE 21. LARGE SIGNAL STEP RESPONSE
0
100MHz OUTPUT
TEST CIRCUIT #1
FEEDTHROUGH (dB)
-2
ENABLED
PD
DISABLED
-4
100mVP-P INPUT
-6
-8
-10
-12
2VP-P INPUT
-14
-16
TEST CIRCUIT #1
2µs/DIV
1
FIGURE 22. ENABLE/DISABLE TIMES
95
OUTPUT
PSRR TO VO (DIFFERENTIAL)
2.0
85
1.5
1.0
INPUT
0.5
0
-0.5
-1.0
-1.5
75
CMRR TO VO (DIFFERENTIAL)
65
55
45
-2.0
-2.5
100
FIGURE 23. DISABLED FEEDTHROUGH
PSRR/CMRR (dB)
INPUT AND OUTPUT WAFEFORMS (V)
2.5
10
FREQUENCY (MHz)
TEST CIRCUIT #1
0
20
40
60
80
100 120
TIME (ns)
140
FIGURE 24. OVERDRIVE RECOVERY
9
160
180
200
35
TEST CIRCUIT #1 SIMULATED,
EXACT EXTERNAL R’s
1
10
100
1000
FREQUENCY (MHz)
FIGURE 25. PSRR/CMRR TO DIFFERENTIAL VO
FN7811.0
March 2, 2011
ISL55210
Typical Performance Curves
TEST CIRCUIT #1
5
4
MAXIMUM DIFFERENTIAL VP-P
OUTPUT USING DEFAULT VCM
3
2
SUPPLY CURRENT (mA)
OUTPUT DEFAULT VCM AND
MAX DIFFERENTIAL VOPP (V)
6
VS+ = 3.3V, TA ≈ +25°C, unless otherwise noted. (Continued)
INTERNALLY SET VCM
1
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5
SUPPLY VOLTAGE (V)
45
44 TEST CIRCUIT #1
43
TA = +85°C
42
41
40
39
38
TA = +25°C
37
36
35
TA = -40°C
34
33
32
31
30
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5
SINGLE SUPPLY VOLTAGE (V)
FIGURE 26. DEFAULT VCM AND MAX VOPP vs SUPPLY VOLTAGE
Applications
Basic Operation
The ISL55210 is a very wideband, voltage feedback based,
differential amplifier including an output common mode control
loop and optional power shutdown feature. Intended for very low
distortion differential signal driving, this non-unity gain stable
device also delivers extremely low input noise terms of
0.85nV/√Hz and 5pA/√Hz. Most applications are intended for AC
coupled I/O using a single 3.3V supply. It will operate over a
single supply range of 3.0V to 4.2V. Where DC coupled operation
is desired, using split power supplies will allow the ISL55210 I/O
common mode range limits to be observed while giving either a
differential I/O or single to differential configuration.
Most applications behave as a differential inverting op amp design.
There is, therefore, an input gain resistor on each side of the inputs
that must be driven. To retain overall low output noise, these
resistors are normally of low value. The device can be powered down
to <400µA supply current using the optional disable pin. To operate
normally, this pin should be asserted high using a simple logic gate
to +VS or tied high through a 10kΩ resistor to +VS. When disabled,
the power dissipation drops to <1mW but, due to the inverting op
amp type architecture, the input signal will feed forward through the
external resistors giving limited isolation.
Application and Characterization Circuits
The circuit of Figure 28 forms a starting point for many of the
characterization curves for the ISL55210. Since most lab sources
and measurement devices are single-ended, this circuit converts
to differential at the input through a wideband transformer and
would also be a typical application circuit coming from a single
ended source. Assuming the source is a 50Ω impedance, the RG
resistors are set to provide both the input termination and the
gain. Since the inverting summing nodes act as virtual ground
points for AC signal analysis, the total termination impedance
across the input transformer secondary will be 2 * RG. Setting
this equal to n2*RS will give a matched input impedance inside
the bandwidth of the transformer (where "n" is the turns ratio).
The amplifier gain is then set by adjusting the feedback resistors
10
FIGURE 27. SUPPLY CURRENT vs SUPPLY VOLTAGE
values. Since the ISL55210 is a VFA design, increasing the
feedback resistor to get higher gain does not directly reduce the
bandwidth as it would with a CFA based design. This gives
increased flexibility in the input turns ratio and overall gain
setting (while holding a matched input impedance) over
alternate solutions.
+3.3V
33mA 110mW
200
RF
50
50
1:1.4
VI
10k
85
+
RG
1µF
PD
200
1µF
0.1uF
VCM
50
35
200
VO LOAD
1µF
VM
ISL55210
ADT2-1T
35
RG
1:1
-
50
ADT1-1WT
1µF 85
RF
200
FIGURE 28. TEST CIRCUIT #1
Working with a transformer coupled input as shown in Figure 28,
or with two DC blocking caps from a differential source, means
the output common mode voltage set by either the default
internal VCM setting, or a voltage applied to the VCM control pin,
will also appear as the input common mode voltage. This
provides a very easy way to control the ISL55210 I/O common
mode operating voltages for an AC coupled signal path. The
internal common mode loop holds the output pins to VCM and,
since there is no DC path for an ICM current back towards the
input in Figure 28, that VCM setting will also appear as the input
common mode voltage. It is useful, for this reason, to leave any
input transformer secondary centertap unconnected. The
internally set VCM voltage is referenced from the negative supply
pin. With a single 3.3V supply, it is very close to 1.2V but will
change with total supply voltage across the device as shown in
Figure 26.
FN7811.0
March 2, 2011
ISL55210
Most of the characterization curves start with Figure 28 then get
different gains by changing the feedback resistor, RF, use
different input transformers where then the RG is also adjusted
to hold an input match, or vary the loading. For load tests below
the 200Ω shown in Figure 28, a simple added shunt resistor is
placed across the output pins. For loads >200Ω, the series and
shunt load R's are adjusted to show that total load (including the
50Ω measurement load reflected through the 1:1 output
measurement port transformer) and provide an apparent 50Ω
differential source to that transformer. This output side
transformer is for measurement purposes only and is not
necessary for final applications circuits. There are output
interface designs that do benefit from a transformer as part of
the signal path, but the one shown at the right of Figure 28 is
used only for characterization to get a doubly terminated 50Ω
measurement path going differential to single ended.
Where just the amplifier is tested, a 4 port network analyzer is
used and the very simple test circuit of Figure 29 is
implemented. This is used to extract the differential S21 curves
and differential output impedance vs gain. Changing the gain is a
simple matter of adjusting the two RF resistors of Figure 29. This
circuit depends on the two AC coupled source 50Ω of the 4 port
network analyzer and presents an AC coupled differential 100Ω
load to the amplifier as the input impedance of the remaining
two ports of the network analyzer.
impedance that increases with signal gain setting. The ISL55210
holds a more constant response vs gain due to internal design
elements unique to this device.
Common mode output measurements are made using the circuit
Figure 30. Here, the outputs are summed together through two
100Ω resistors (still a 200Ω differential load) to a center point
where the average, or common mode, output voltage may be
sensed. This is coupled through a 1µF DC blocking capacitor and
measured using 50Ω test equipment. The common mode source
impedance for this circuit is the parallel combination of the
2Ω - 100Ω elements, or 50Ω. Figure 18 uses this circuit to
measure the small and large signal response from the VCM
control pin to the output common mode. This pin includes an
internal 50pF capacitor on the default bias network (to filter
supply noise when there is no connection to this pin) which
bandlimits the response to approximately 30MHz. This is far
lower than the actual bandwidth of the common mode loop.
Figure 19 uses this output CM measurement circuit with a large
signal (2VP-P) differential output voltage (generated through the
Vi path of Figure 30) to measure the differential to common
mode conversion.
+3.3V
200
10k
+3.3V
50
RF
Vi
PD
10k
50
50
50
+
1µF
V CM
VCM
ISL55210
50
50
50
100
200
VCM INPUT
-
1µF
ISL55210
50
1/2 OF A 4-PORT
S-PARAMETER
50
OUTPUT
VCM
ADT2-1T
PD
1/2 OF A 4-port
S-PARAMETER
100
+
1:1.4
50
FIGURE 30. TEST CIRCUIT #3 COMMON MODE AC OUTPUT
MEASUREMENTS
RF
FIGURE 29. TEST CIRCUIT #2 4-PORT S-PARAMETER
MEASUREMENTS
Using this measurement allows the full small single bandwidth of
the ISL55210 to be exposed. Many of the other measurements are
using I/O transformers that are limiting the apparent bandwidth to
reduced level. Figure 16 shows a series of normalized differential
S21 curves for gains of 12dB to 30dB in 6dB steps. These are
simply stepping two feedback resistor values (RF) up from 200Ω to
1600Ω in 2X steps. The lowest gain of 12dB (4V/V) is showing a
2.2GHz small signal bandwidth. This response gets some
bandwidth extension due to phase margin <60degree effects, but
by the gain of 24dB (16V/V), the bandwidth is following a Gain
Bandwidth type characteristic showing 300MHz bandwidth or
>4GHz Gain Bandwidth Product (GBP).
The closed loop differential output impedance of Figure 17 is
simulated using Figure 29 in ADS. This shows a relatively low
output impedance (<1Ω through 100MHz) constant with signal
gain setting. Typical FDA outputs show a closed loop output
11
Single Supply, Input Transformer Coupled,
Design Considerations
The characterization circuit of Figure 28 shows one possible
input stage interface that offers several advantages. The
ISL55210 can also support a DC coupled differential to
differential or single ended input to differential requirement if
needed. Where AC coupling is adequate, the circuit of Figure 28
simplifies the input common mode voltage control. If the source
coming into this stage is single ended, the input transformer
provides a zero power conversion to differential. The two gain
resistors (RG in Figure 28) provide both the input termination
impedance and the gain element for the amplifier. For minimum
noise, only RG should be used and set to achieve the desired
input impedance. Since the ISL55210 is a VFA device, these
resistor values can be scaled up and down a bit more freely than
a current feedback based FDA.
FN7811.0
March 2, 2011
ISL55210
For instance, if a minimum noise configuration is not required,
but it is desirable to increase the feedback resistors to reduce the
added loading they present to the output stage, the RG and RF
resistors can be scaled up to achieve the same gain with an
additional termination resistance added across the input
transformer to adjust the termination impedance. Figure 31
shows an example using a 1:2 input turns ratio where the RG and
RF elements have been scaled up and a shunt termination
resistance added. This example provides a single to differential
signal gain of 20dB and input impedance of 50Ω to the source.
The 1:2 turn ratio transformer needs a 200Ω differential
secondary impedance to provide an input side 50Ω match. This is
provided here by the parallel combination of the 2Ω - 200Ω RG
resistors and the 400Ω parallel impedance at the transformer
secondary.
+3.3V
1k
RF
200
50
Vi
1µF
+
RG
1:2
V CM
400
ISL55210
VO
ADT41WT
RG
-
200
RF
1k
FIGURE 31. SINGLE TO DIFFERENTIAL WITH REDUCED FEEDBACK
LOADING
The examples shown are using the transformer to convert from
single to differential. However, if the source is already
differential, these same transformer input circuits can drive the
transformer differentially still providing impedance scaling if
needed and common mode rejection for both DC and AC
common mode issues. A good example would be differential
mixer outputs or SAW filter outputs. Those differential sources
could also be connected into the ISL55210 RG resistors through
blocking caps as well eliminating the input transformer. The AC
termination impedance for the differential source will then be
the sum of the two RG resistors when simple blocking caps are
used.
Amplifier I/O Range Limits
The ISL55210 is intended principally to give the lowest IM3
performance on the lowest power for a differential I/O
application. The amplifier will work DC coupled and over a
relatively wide supply range of 3.0V to 4.2V supplies. The outputs
have both a differential and common mode operating range
while the input pins have a common operating range. For single
supply operation, the ground pins are at ground as is the exposed
metal pad on the underside of the package. The ISL55210 can
operate split supply where then the ground pins will be a
negative supply voltage and the exposed metal pad is either
connected to this negative supply or left unconnected on an
insulating board layer.
Briefly, the I/O and VCM limits are:
1. Maximum VCM setting = -VS + 2V
2. Input common mode operating range of -VS + 1.1V or the
output VCM + 0.5V
3. Output VO minimum (on each side) is either -VS + 0.3V or
output VCM - 0.9V
4. Output VO maximum (on each side) is +VS - 1.5V
This circuit has scaled the feedback resistor up to 1kΩ to still
achieve the amplifier gain of 5V/V which gives the overall gain of
10V/V (20dB) when the 1:2 step up at the input is considered.
The particular transformer shown is typical of 1:2 turns ratio
broadband transformers, but there a many alternates with the
similar or improved characteristics.
This input interface also simplifies the input common mode
control. The VCM pin controls the output common mode voltage.
In most DC coupled FDA applications, the input common mode
voltage is determined by both this output common mode and the
source signal. In a configuration like Figure 31, there is no path
for a common mode current to flow from output to input, so the
input common mode voltage equals the output. A similar effect
could be achieved with just two blocking caps on the two RG
resistors. A DC coupled, single to differential, configuration will
also have a common mode input that is moving with the input
signal. Converting to just a differential signal at the amplifier, as
in Figure 31, removes any input signal related artifacts from the
input common mode making the ISL55210 behave as a
differential only VFA amplifier. There is only a very small
differential error signal at the inputs set by the loop gain, as in a
normal single ended VFA application, but no common mode
signal related terms.
12
The output swing limits are often asymmetrical around the VCM
voltage. The maximum single ended swings are set by these two
limits:
VOMIN is either -VS + 0.3V or VCM - 0.9V whichever is less. So for
instance on a single 3.3V supply with the default VCM voltage of
1.2V, these two limits give the same result and the output pins
can swing down to 0.3V above -VS = 0V. If, however, the VCM pin
is raised to 1.5V, then the minimum output voltage will become
1.5V - 0.9V = 0.6V.
VOMAX is set by a headroom limit to the positive supply to be:
VOMAX = +VS - 1.5V. Again, on a 3.3V single supply and the
default 1.2V VCM setting, this mean the maximum referenced to
ground output pin voltages can be 3.3V - 1.5V = +1.8V or 0.6V
above the default VCM voltage.
Using these default conditions, and the maximum positive
excursion of 0.6V above the 1.2V output VCM setting, the
maximum differential VP-P swing will be 4X this 0.6V single
ended limit or 2.4VP-P. Where +VS is increased the limit then
becomes the 0.9V below VCM, but then the absolute maximum
differential VP-P is then 4X 0.9V to 3.6VP-P. So, for instance, to
get this maximum output swing, increase the supply voltage until
+VS - 1.5V > VCM + 0.9V. If we assume a VCM voltage of 1.3V for
instance, then 1.3V + 0.9V + 1.5V = 3.7V will give an unclipped
FN7811.0
March 2, 2011
ISL55210
3.6VP-P output capability. The VP-P reported in Figure 26 is an
asymmetrically clipped maximum swing. Going 10% above this
3.7V target to 4.1V will be within the recommended operating
range and give some tolerancing headroom that would also
suggest the VCM voltage be moved up to approximately 1.5V. This
coincides with the default output VCM from Figure 26. Operating
at +4.1V single supply in a Figure 28 type configuration will give
the maximum linear available output swing of 3.6VP-P.
The differential inputs of the ISL55210 also have operating
range limits relative to the supply voltages. Operating in an AC
coupled circuit like Figure 28 will produce an input common
mode voltage equal to the outputs. The inputs can operate with
full linearity with this VCM voltage down to 1.1V above the GND
connection (or -VS supply). On the default 1.2V output VCM on
+3.3V supplies this gives a 100mV guardband on the input VCM
voltages. Overriding the default VCM by applying a control voltage
to the VCM pin should be done with care in going towards the
negative supply due to this limit. On the + side, the maximum
VCM above the -VS supply is 2V so there is more room to move
the output VCM up than down from the default value.
When operated as a DC coupled single to differential amplifier,
the input common mode voltage will move with the input signal
and will be different than the output common mode voltage
when the external resistors are set for gain. When the input
common mode can be different than the output, the additional
constraint that must be observed is that the input common mode
voltage cannot be > output VCM +0.5V. This would only occur if
the single source was coming from a higher voltage than the
output VCM setting.
Power Supply, Shutdown, and Thermal
Considerations
The ISL55210 is intended for single supply operation from 3.0V
to 4.2V with an absolute maximum setting of 4.5V. The 3.3V
supply current is trimmed to be nominally 35mA at +25°C
ambient. Figure 27 shows the supply current for nominal +25°C
and -40°C to +85°C operation over the specified maximum
supply range. The input stage is biased from an internal voltage
referenced from the negative supply giving the exceptional 90dB
low frequency PSRR shown in Figure 25.
Since the input stage bias is from a re-regulated internal supply,
a simple approach to single +5V operation can be supported as
shown in Figure 32. Here, a simple IR drop from the +5V supply
will bring the operating supply voltage for the ISL55210 into its
allowed range. Figure 32 shows example calculations for the
voltage range at the ISL55210 +VS pin assuming a ±5%
tolerance on the +5V supply and a 35mA to 55mA range on the
total supply current. Considering the 34mA to 44mA quiescent
current range from Figure 27 over the -40°C to +85°C ambient,
and the 3.4V to 4.4V supply voltage range assumed here, this is
designing for a 1mA to 11mA average load current which should
be adequate for most intended application loads. Good supply
decoupling at the device pins is required for this simple solution
to still provide exceptional SFDR performance.
13
+5V ±5%
35
24.3
3.4
55mA
+
RF
4.4V
2.2µF
10nF
10k
+
C in
1:n
RO
RG
PD
V CM
Vi
VO
ISL55210
RO
RG
-
RF
FIGURE 32. OPERATING FROM A SINGLE +5V SUPPLY
The ISL55210 includes a power shutdown feature that can be
used to reduce system power dissipation when signal path
operation is not required. This pin (PD) is referenced to the
ground pins and must be asserted low to activate the shutdown
feature. When not used, a 10kΩ external resistor to +VS should
be used to assert a high level at this pin. Digital control on this
pin can be either an open collector output (using that 10kΩ
pullup) or a CMOS logic line running off the same +VS as the
amplifier. For split supply operation, the PD pins must be pulled
to below -VS + 0.54V to disable.
Since the ISL55210 operates as a differential inverting op amp,
there is only modest signal path isolation when disabled as
shown in Figure 23. For small input signals, Figure 23 shows
about 5dB to 6dB isolation while for large signals, back to back
protection diodes across the inputs compress the signal to show
actually an improved isolation. This is intended to protect any
subsequent devices from large input signals during shutdown.
Those diodes limit the maximum overdrive voltage across the
input to approximately 0.5V in each polarity. The RG resistors of
Test Circuit #1 limit the current into those diodes under this
condition.
The supply current in shutdown does not reduce to zero as
internal circuitry is still active to hold the output common mode
voltage at the VCM control input voltage even during shutdown (or
the default value). This is intended to hold the ISL55210 output
near the desired common mode output level during shutdown.
This improves turn on characteristic and keeps the output
voltages in a safe range for downstream circuitry.
The very low internal power dissipation of the ISL55210, along
with the excellent thermal conductivity of the QFN package when
the exposed metal pad is tied to a conductive plate, reduces the
TJ rise above ambient to very modest levels. Assuming a nominal
115mW dissipation and using the +63°C/W measured thermal
impedance from Junction to ambient, gives a rise of only
0.12 * 63 = +7.6°C. Operation at elevated ambient
temperatures is easily supported given this very low internal rise
to junction.
FN7811.0
March 2, 2011
ISL55210
The maximum internal junction temperatures would occur at
maximum supply voltage, +85°C maximum ambient operating,
and where the QFN exposed pad is not tied to a conductive layer.
Where the QFN must be mounted with an insulating layer to the
exposed metal plate, such as in a split supply application, device
measurements show an increased thermal impedance junction
to ambient of +120°C/W. Using this, and a maximum quiescent
internal power on 4.5V absolute maximum, which shows 45mA
for +85°C maximum operating ambient from Figure 27, we get
4.5V * 45mA * +120°C/W = +24°C rise above +85°C or
approximately +109°C operating TJ maximum - still well below
the specified Absolute Maximum operating junction temperature
of +135°C.
Noise Analysis
The decompensated voltage feedback design of the ISL55210
provides very low input voltage and current noise. While a
detailed noise model using arbitrary external resistors can be
made, most applications will have a balanced feedback network
with the two RF (feedback) resistors equal and the two RG (gain)
resistors equal. Figure 33 shows the test circuit used to measure
the output noise with the noise terms detailed. The aim here was
to measure the output noise with two different resistor settings
to extract out a model for the input referred En and In terms for
just the amplifier itself.
4kTRf
*
+
RG
1µF
25
in
1:1
*
*
in
4kTRg
*
en
ISL55210
ADT1-1WT
eO
1µF
50
*
25
-
RG
1µF
RF
*
4kTRf
FIGURE 33. NOISE MODEL AND TEST CIRCUIT
With equal feedback and gain resistors, the total output noise
expression becomes very simple. This is:
e0 =
2
Driving Cap and Filter Loads
Most applications will drive a resistive or filter load. The
ISL55210 is robust to direct capacitive load on the outputs up to
approximately 10pF. For frequency response flatness, it is best to
avoid any output pin capacitance as much as possible - as that
capacitance increases, the high frequency portion of the
ISL55210 (>1GHz) response will start to show considerable
peaking. No oscillations were observed up through 10pF load on
each output.
For AC coupled applications, an output network that is a small
series resistor (10Ω to 50Ω) into a blocking cap is preferred. This
series resistor will isolate parasitic capacitance to ground from
the internally closed loop output stage of the amplifier and
de-queue the self resonance of the blocking capacitors. Once the
output stage sees this resistive element first, the remaining part
of the filter design can be done without fear of amplifier
instability.
Driving ADCs
RF
4kTRg
*
Putting in NG = 3, RF = 200Ω, RG = 100Ω with the ISL55210
noise terms of En = 0.85nV/√Hz and In = 5pA/√Hz into Equation 1
(4kT = 1.6E - 20J) gives a total output differential noise
voltage = 5.26nV/√Hz. Input referring this to the input side of the
transformer of Test Circuit #1 gives an input referred spot noise
of only 0.88nV/√Hz. This extremely low input referred noise is a
combination of low amplifier noise terms and the effect of the
input transformer configuration.
2
( e n • NG ) + 2 ( i n R f ) + 2 ( 4kTR f NG )
(EQ. 1)
The NG term in Equation 1 is the Noise Gain = 1 + RF/RG. The
last term in Equation 1 captures both the RF and RG resistor
noise terms. If we assume a 50Ω source in Test Circuit #1, the
total RG resistor value will be 100Ω as that 50Ω will come
through the transformer to look like a 50Ω source on each side.
This gives a lower noise gain (3V/V) than signal gain (4V/V) for
just the amplifier. The total gain in Test Circuit #1 is still
approximately 1.4 * 4 = 5.6V/V including the transformer step
up.
14
Many of the intended applications for the ISL55210 are as a low
power, very high dynamic range, last stage interface to high
performance ADCs. The lowest power ADCs, such as the
ISLA112P50 shown on the front page, include an innovative
"Femto-Charge" internal architecture that eliminates op amps
from the ADC design and only passes signal charge from stage to
stage. This greatly reduces the required quiescent power for
these ADCs but then that signal charge has to be provided by the
external circuit at the two input pins. This appears on an ADC like
the ISLA112P50 as a clock rate dependent common mode input
current that must be supplied by the interface circuit. At
500MHz, this DC current is 1.3mA on each input for the
ISLA112P50.
Most interfaces will also include an interstage noise power
bandlimiting filter between the amplifier and the ADC. This filter
needs to be designed considering the loading of the amplifier,
any VCM level shifting that needs to take place, the filter shape,
and this ICM issue into the ADC input pins. Here are 4 example
topologies suitable for different situations.
1. AC coupled, broadband RLC interstage filter design. This
approach lets the amplifier operate at its desired output
common mode, then provides the ADC common mode
voltage and current through a bias path as part of the filter
design’s last stage R values. The VB is set to include the IR
loss from that voltage to the ADC inputs due to the ICM
current. This circuit is the one shown on the front page where
we get a usable frequency range from about 500kHz to
150MHz.
FN7811.0
March 2, 2011
ISL55210
2. AC coupled, higher frequency range interstage filter design.
This design replaces the Rt resistors in Figure 34 with large
valued inductors and implements the filter just using shunt
resistors at the end of the RLC filter (here, that is just the ADC
internal differential Rin). In this case, the ADC VCM can be tied
to the centerpoint of the bias path inductors (very much like a
Bias-T) to provide the common mode voltage and current to
the ADC inputs. These bias inductors do limit the low
frequency end of the operation where, with 1µH values,
operation from 10MHz to 200MHz is supported using the
approach of Figure 35.
3. AC coupled with output side transformer. This design includes
an output side transformer, very similar to ADC
characterization circuits. This approach allows a slightly lower
amplifier output swing (if N > 1 is used) and very easy 2nd
order low pass responses to be implemented. It also provides
the ICM and VCM bias to the ADC through the transformer
centertap. This approach would be attractive for higher ADC
input swing targets and more aggressive noise power
bandwidth control needs.
4. DC coupled with ADC VCM and ICM provided from the
amplifier. Here, DC to very high frequency interstage low pass
filters can be provided. Again, the RS element must be low to
reduce the IR drop from the VCM of the converter, which now
shows up on the output of the ISL55210, to the ADC input
pins. In this case, split supplies are required to satisfy the
amplifier output and input common mode range limits
discussed earlier.
RF
Rf
ADC
ADC
+3.3V
ISL55210
Vcm1
Ls
+3.3V
Icm
IN+
ISL55210
Cb
Rs
Rt
1.2V
Vb
Rt
Ls
ICM
Ci n
VCM1
IN+
Cb
RS
LP
Ct
Rin
Cb
Rs
LS
1.2V
Ct
RT
Cb
RS
Ct
LP
LS
Ct
INRf
Icm
R R>t R> R s
t
s
v –VI − I× R ×=R V = V
B bcm cm t
t cm2cm
IN-
Vcm2 = 0.535
or 1V
RF
VCM2 = 0.535
or 1V
ICM
Lp>>Ls
2
FIGURE 34. AC COUPLED, BROADBAND RLC INTERSTAGE FILTER
DESIGN
FIGURE 35. AC COUPLED, HIGHER FREQUENCY RLC FILTER DESIGN
Rf
RF
ADC
ADC
+3.3V
ISL55210
VCM1
Cin
Rin
+3.0V
ICM
RS
Cb
1:n
IN+
ISL55210
Cin
Ct
Rin
Rs
Ct
Ls
Ct
-1.1V
IN-
IN-
Rf
RF
ICM
VCM2 = 0.535
or 1V
Rt ≤30Ω
Cin
Rt
Cb
Rt
IN+
Ct
Vcm
Rin
RS
Icm
Rs
Rt
1.2V
Ls
Icm
Rs ≤30Ω
Vcm = 0.535V
or 1V
2ICM
FIGURE 36. AC COUPLED WITH OUTPUT SIDE TRANSFORMER
15
FIGURE 37. DC COUPLED WITH A COMMON VCM VOLTAGE FROM
THE ADC
FN7811.0
March 2, 2011
ISL55210
Layout Considerations
The ISL55210 pinout is organized to isolate signal I/O along one
axis of the package with ground, power and control pins on the
other axis. Ground and power should be planes coming into the
upper and lower sides of the package (see the Pin Configuration
on page 2). The signal I/O should be laid out as tight as possible
with parasitic C to the ground and/or power planes reduced as
much as possible by opening up those planes under the I/O
elements.
The ground pins and package backside metal contact should be
connected into a good ground plane. The power supply should
have both a large value electrolytic cap to ground, then a high
frequency ferrite beads, then 0.01µF SMD ceramic caps at the
supply pins. Some improvement in HD2 performance may be
experienced by placing and X2Y cap between the two VS+ pins
and ground underneath the package on the board back side. This
is 4 terminal device that is included in the EVM board layout.
EVM Board (Rev. C)
Test circuit #1 (Figure 28) is implemented on an Evaluation
Module Board available from Intersil. This board includes a
number of optional features that are not populated as the board
is delivered. The full EVM board circuit is shown in Figure 38
where unloaded (optional) elements are shown in green.
The nominal supply voltage for the board and device is a single
3.3V supply. From this, the ISL55210, ISL55211 generates an
internal common mode voltage of approximately 1.2V. That
voltage can be overridden by populating the two resistors and
potentiometer shown as R19 to R21 above.
The primary test purpose for this board is to implement different
interstage differential passive filters intended for the ADC
interface along with the ADC input impedances. The board is
delivered with only the output R's loaded to give a 200Ω
differential load. This is done using the two 85Ω resistors as R9
and R10, then the 4 zero ohm elements (R10, R12, R24, and R25)
and finally the two shunt elements R13 and R14 set to 35.5Ω.
Including the 50Ω measurement load on the output side of the 1:1
transformer reflecting in parallel with the two 35Ω resistors takes
the nominal AC shunt impedance to 71Ω||50Ω = 29.3Ω. This adds
to the two 85Ω series output elements to give a total load across
the amplifier outputs of 170Ω + 29.3Ω = 199.3Ω.
To test a particular ADC interface RLC filter and converter input
impedance, replace R11 and R12 with RF chip inductors, load
C10 and C11 with the specified ADC input capacitance and R26
with the specified ADC differential input R. With these loaded,
the remaining resistive elements (R24, R25, R13, R14) are set to
hit a desired total parallel impedance to implement the desired
filter (must be < than the ADC input differential R since that sits
in parallel with any "external" elements) and achieve a 25Ω
source looking into each side of the tap point transformer.
This EVM board includes a user's manual showing a number of
example circuits and tested results. Available on the Intersil web
site in the ISL55210 Product Information Page.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
March 2, 2011
REVISION
CHANGE
FN7811.0 Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL55210
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN7811.0
March 2, 2011
C1001
4.7µF
GND
R21
VCC
L1
+Vs
+ BEAD
C1002
1.0µF
C3
200Ω/DNP
100nF
R19
1k/DNP
C2
100nF
R18
R17
17
Cterm2
2.2pF
R8 200Ω
4
13
14
GND
Vcm
Vs+
GND
Vi-
NC
11
Vi+
NC
Fb-
Vo-
1µF
10
C6
9
GND
R7 0Ω
12
TEST POINT
R20
200Ω/DNP
C10
DNP
1µF
R11
R24
0Ω
0Ω
R13
35.5Ω
0Ω/DNP
R14
35.5Ω
R10
R12
R25
85Ω
0Ω
0Ω
50Ω
C5
100nF
TP2
DIFPROBE
R16
50Ω
1
PD
R22
50Ω
2
3
NC
VCC
5
A
GND
Y
C8
ADT1-1WT
R28
R15
C4
100nF
R9
85Ω
ISL55210,
ISL55211
8
50Ω
R26
DNP
TP1
4
74AHC1G04
FIGURE 38. SCHEMATIC FOR ISL55210, ISL55211 SINGLE INPUT TRANSFORMER EVM REV. C
OUT
1µF
R27
0Ω
ISL55210
R2
DNP
2
3
R4
R23
0Ω
C9
100nF
C7
Vo+
Fb+
PD
50Ω
R6 0Ω
1
Vs+
R0
DNP
R5 200Ω
7
1µF
R3
GND
ADT2-1T
50Ω
U1
6
C1
Cterm1
2.2pF
5
IN
R1
DNP
15
16
200Ω
C11
DNP
FN7811.0
March 2, 2011
ISL55210
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
A
12X 0.50
B
13
6
PIN 1
INDEX AREA
16
6
PIN #1
INDEX AREA
12
3.00
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
5
8
16X 0.40±0.10
TOP VIEW
4 16X 0.23 ±0.05
BOTTOM VIEW
SEE DETAIL “X”
0.10 C
0.75 ±0.05
C
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) (
1.60)
(16X 0.23)
C
0 . 2 REF
5
0 . 02 NOM.
0 . 05 MAX.
(16X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-220 WEED.
either a mold or mark feature.
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FN7811.0
March 2, 2011