®
ADS
ADS902
902
E
10-Bit, 30MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
DESCRIPTION
● HIGH SNR: 57dB
The ADS902 is a high speed pipelined analog-todigital converter that is specified to operate from a
single +5V supply. This converter includes a wide
bandwidth track/hold and a 10-bit quantizer. The performance is specified with a single-ended input range
of 2.25V to 3.25V, or 2V to 4V. The input range is set
by the external reference values.
●
●
●
●
EXTERNAL REFERENCE
LOW POWER: 140mW
ADJUSTABLE FULL SCALE RANGE
POWER DOWN
● 28-PIN SSOP PACKAGE
The ADS902 employs digital error correction techniques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. This high performance A/D converter is specified to operate at a 30MHz sampling rate. The ADS902
is available in a 28-pin SSOP package.
APPLICATIONS
● BATTERY POWERED EQUIPMENT
● CAMCORDERS
● PORTABLE TEST EQUIPMENT
● COMPUTER SCANNERS
● COMMUNICATIONS
LVDD
CLK
ADS902
Timing
Circuitry
IN
T/H
Pipeline
A/D
Error
Correction
Logic
3-State
Outputs
10-Bit
Digital
Data
Reference
Ladder
REFT CM REFB
Pwrdn
OE
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Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
1996 Burr-Brown Corporation
PDS-1359B
1
ADS902
Printed in U.S.A., February, 1997
SPECIFICATIONS
At TA = +25°C, V S = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.
ADS902E
1Vp-p
PARAMETER
CONDITIONS
Resolution
Specified Temperature Range
TEMP
MIN
Ambient Air
–40
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
ACCURACY
Gain Error
Input Offset Error(4)
Power Supply Rejection (Gain)
Power Supply Rejection (Offset)
External REFT Voltage Range
External REFB Voltage Range
Reference Input Resistance
MIN
Full
TYP
MAX
UNITS
+85
Bits
°C
10
+85
–40
1
+2.75
350
1
1.25 || 5
DIGITAL INPUTS
Logic Family
High Input Voltage, V IH
Low Input Voltage, VIL
High Input Current, IIH
Low Input Current, IIL
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
High Output Voltage, VOH
Low Output Voltage, V OL
3-State Enable Time
3-State Disable Time
OE Internal Pull-Down to Gnd
Power-Down Enable Time
Power-Down Disable Time
Power-Down Internal Pull-Down to Gnd
2Vp-p
MAX
10
ANALOG INPUT
Specified Full Scale Input Range(1)
Common-Mode Voltage (Midscale)
Track-Mode Input Bandwidth
Analog Input Bias Current
Input Impedance
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 500kHz
f = 12.5MHz
No Missing Codes
Spurious-Free Dynamic Range
f = 12.5MHz (–1dBFS(2) input)
Integral Nonlinearity Error, f = 500kHz
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12.5MHz (–1dBFS input)
Maximum SNR
f = 9MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 3.58MHz (–1dBFS input)
f = 12.5MHz (–1dBFS) input)
Effective Number of Bits(3), f =12.5MHz
Output Noise
Aperture Delay Time
Aperture Jitter
TYP
2
3
✻
✻
✻
Vp-p
V
MHz
µA
MΩ || pF
TTL/HCT Compatible CMOS
+2.0
+VS
+0.8
±10
±10
5
TTL/HCT Compatible CMOS
✻
✻
✻
✻
✻
✻
10k
✻
30M
Full
Full
Full
±0.3
±0.3
Guaranteed
Full
Full
53
±2.0
✻
Samples/s
Clk Cyc
✻
✻
LSB
LSB
✻
dB
LSB
✻
5
±1.0
±1.0
✻
✻
Guaranteed
50
±4.5
58
✻
V
V
µA
µA
pF
Referred to Sinewave Input Signal
Full
Full
48
48
53
53
52
57
dB
dB
66
dB
Referred to DC FS Input Signal
62
Full
Full
Full
46
45
45
✻
✻
✻
dB
dB
dB
Bits
LSB rms
ns
ps rms
TTL/HCT Compatible CMOS
Straight Offset Binary
+2.4
LVDD
+0.4
20
40
18
10
50
133
18
50
TTL/HCT Compatible CMOS
Straight Offset Binary
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
ns
ns
kΩ
ns
ns
kΩ
0.5
1.4
56
68
+3.25
+2.25
4
1
✻
✻
✻
+4
+2
✻
%FS
%FS
dB
dB
V
V
kΩ
Input Grounded
50
50
49
7.8
0.2
4
7
47
53
CL = 15pF
OE = L
OE = H
Pwrdn = L
Pwrdn = H
∆ VS = ±5%
∆ VS = ±5%
Full
Full
Full
Full
Full
Full
REFT to REFB
42
42
REFB +0.5
+0.8
VS–0.8
REFT –0.5
✻
✻
✻
✻
✻
✻
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
®
ADS902
2
SPECIFICATIONS (CONT)
At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.
ADS902E
1Vp-p
PARAMETER
CONDITIONS
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation
Power Dissipation (Power Down)
Thermal Resistance, θJA
28-Pin SSOP
2Vp-p
TEMP
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Full
Full
Full
Full
+4.25
+5.0
28
140
15
+5.25
✻
✻
✻
✻
✻
✻
V
mA
mW
mW
160
✻
50
✻
°C/W
✻ Specification same as 1Vp-p.
NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) dBFS means dB relative to Full Scale. (3) Effective number of bits (ENOB) is defined
by (SINAD – 1.76)/6.02. (4) Offset deviation from ideal negative full scale.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VS, LVDD .................................................................................................................................. +6V
Analog Input ...............................................................................+VS +0.3V
Logic Input ................................................................................. +VS +0.3V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS902E
28-Pin SSOP
324
TEMPERATURE
RANGE
–40°C to +85°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PIN CONFIGURATION
PIN DESCRIPTIONS
Top VIew
SSOP
+VS
1
28
+VS
LVDD
2
27
IN
(LSB) Bit 10
3
26
CM
Bit 9
4
25
LnBY
Bit 8
5
24
REFB
Bit 7
6
23
NC
Bit 6
7
22
REFT
Bit 5
8
21
LpBY
Bit 4
9
20
GND
Bit 3
10
19
GND
Bit 2
11
18
+VS
(MSB) Bit 1
12
17
Pwrdn
GND
13
16
OE
GND
14
15
CLK
ADS902
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+VS
LVDD
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
GND
GND
CLK
OE
Pwrdn
+VS
GND
GND
LpBy
REFT
NC
REFB
LnBy
CM
IN
+VS
DESCRIPTION
Analog Supply
Output Logic Driver Supply Voltage
Data Bit 10 (D0, LSB)
Data Bit 9 (D1)
Data Bit 8 (D2)
Data Bit 7 (D3)
Data Bit 6 (D4)
Data Bit 5 (D5)
Data Bit 4 (D6)
Data Bit 3 (D7)
Data Bit 2 (D8)
Data Bit 1 (D9, MSB)
Analog Ground
Analog Ground
Convert Clock Input
Output Enable, Active Low
Power Down Pin
Analog Supply
Analog Ground
Analog Ground
Positive Ladder Bypass
Top Reference
No Connection
Bottom Reference
Negative Ladder Bypass
Common-Mode Voltage Output
Analog Input
Analog Supply
®
3
ADS902
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+6
N+7
tH
Clock
5 Clock Cycles
t2
Data Out
N–5
N–4
N–3
N–2
N–1
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
N+1
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
33
15.5
15.5
®
ADS902
N
4
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
16.5
16.5
2
4
12
N+2
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = LVDD = +5V, REFB = +2.25V, REFT = +3.25V, and Sampling Rate = 30MHz, unless otherwise specified.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 12.5MHz
VIN = 1Vp-p
Amplitude (dB)
–20
Amplitude (dB)
fIN = 12.5MHz
2Vp-p
–20
–40
–60
–40
–60
–80
–80
–100
–100
–120
0
2.5
5.0
7.5
10.0
12.5
15.0
0
2.5
5.0
Frequency (MHz)
12.5
15.0
f1 = 3.5MHz at –7dB
f2 = 3.6MHz at –7dB
2f1 – f2 = 69.5dBFS
2f2 – f1 = 68.4dBFS
–10
–20
Magnitude (dBFSR)
Amplitude (dB)
0
fIN = 40MHz
fS = 28MHz
VIN = 1Vp-p
–20
10.0
FREQUENCY SPECTRUM
UNDERSAMPLING
0
7.5
Frequency (MHz)
–40
–60
–80
–30
–40
–50
–60
–70
–80
–100
–90
–100
–120
0
2.8
5.6
8.4
11.2
0
14.0
2.50
5.00
DIFFERENTIAL LINEARITY ERROR
10.00
DIFFERENTIAL LINEARITY ERROR
2
2
fIN = 12.5MHz
VIN = 1Vp-p
fIN = 12.5MHz
2Vp-p
1
1
DLE (LSB)
DLE (LSB)
7.50
Frequency (MHz)
Frequency (MHz)
0
–1
0
–1
–2
–2
0
256
512
768
1024
0
Output Code
256
512
768
1024
Output Code
®
5
ADS902
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = Logic VDD = +5V, REFB = 2.25V, REFT = 3.25V, Sampling Rate = 30MHz, unless otherwise specified.
SWEPT POWER SFDR
INTEGRAL LINEARITY ERROR
100
10
fIN = 500kHz
VIN = 1Vp-p
fIN = 12.5MHz
1Vp-p
dBFS
80
SFDR
ILE (LSB)
5
0
60
dBc
40
–5
20
0
–10
0
256
512
768
–80
1024
–60
Output Code
SWEPT POWER SFDR
–20
0
OFFSET ERROR vs TEMPERATURE
120
1.6
fIN = 12.5MHz
2Vp-p
100
VIN = 1Vp-p
1.5
dBFS
Offset (%FS)
80
60
dBc
40
1.4
1.3
1.2
20
0
1.1
–80
–60
–40
–20
–10
–50
–25
0
Input Amplitude (dBFS)
GAIN ERROR vs TEMPERATURE
VIN = 1Vp-p
0.2
0.4
0.6
–50
–25
0
25
50
Temperature (°C)
®
ADS902
25
50
Temperature (°C)
0
Gain Error (%FS)
SFDR
–40
Input Amplitude (dBFS)
6
75
100
75
100
THEORY OF OPERATION
φ1
IN
IN
φ1
φ2
φ2
OUT
φ1
OUT
φ1
CI
VCM
φ2
CH
φ1
φ1
Input Clock (50%)
Bias
VCM
Internal Non-overlapping Clock
φ1
φ2
φ1
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
Digital Delay
Input
T/H
(Opt.)
2-Bit
Flash
STAGE 1
φ1
CH
CI
The pipelined quantizer architecture has 9 stages with each
stage containing a two-bit quantizer and a two bit digitalto-analog converter, as shown in Figure 2. Each two-bit
IN
VCM
Bias
The ADS902 is a high speed sampling analog-to-digital
converter that utilizes a pipeline architecture. The fully
differential topology and digital error correction guarantee
10-bit resolution. The differential track/hold circuit is shown
in Figure 1. The switches are controlled by an internal clock
which has a non-overlapping two phase signal, φ1 and φ2. At
the sampling time the input signal is sampled on the bottom
plates of the input capacitors (C1). In the next clock phase,
φ1, the bottom plates of the input capacitors are connected
together and the feedback capacitors are switched to the op
amp output. At this time the charge redistributes between CI
and CH, completing one acquisition cycle. The differential
output is a held DC representation of the analog input at the
sample time. The track/hold circuit also converts the singleended input signal into a fully differential signal for the
subsequent quantizer. Consequently, the input signal-tonoise performance. Other parameters such as small-signal
and full-power bandwidth, and wideband noise are also
defined in this stage.
2-Bit
DAC
+
Σ
–
x2
Digital Delay
STAGE 2
B1 (MSB)
2-Bit
DAC
B2
Digital Error Correction
2-Bit
Flash
+
Σ
–
x2
B3
B4
B5
B6
B7
B8
B9
Digital Delay
2-Bit
Flash
STAGE 8
B10 (LSB)
2-Bit
DAC
+
Σ
–
x2
STAGE 9
2-Bit
Flash
Digital Delay
FIGURE 2. Pipeline A/D Architecture.
®
7
ADS902
quantizer stage converts on the edge of the sub-clock, which
is the same frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
provides the ADS902 with excellent differential linearity
and guarantees no missing codes at the 10-bit level.
signal swing should remain approximately 0.5V away from
each rail during normal operation.
DRIVING THE ANALOG INPUTS
AC-COUPLED DRIVER
Figure 3 shows an example of an ac-coupled, single-ended
interface circuit using a high-speed op amp that operates on
dual supplies (OPA650, OPA658). The mid-point reference
voltage, VCM, biases the bipolar, ground-referenced input
signal. The capacitor C1 and resistor R1 form a high-pass
filter with the –3dB frequency set at
As a result of this pipeline architecture, there is a 5.0 clock
cycle data delay (latency) from the start convert signal to the
corresponding valid output data.
f–3dB = 1/(2 π R1 C1)
To accommodate a bipolar signal swing, the ADS902 operates with a common-mode voltage (VCM) which is derived
from the external references. Due to the symmetric resistor
ladder inside the ADS902, the VCM is situated between the
top and bottom reference voltage. Equation (1) can be used
for calculating the common-mode voltage level.
VCM = (REFT +REFB)/2
(2)
The values for C1 and R1 are not critical in most applications
and can be set freely, e.g. the shown values correspond to a
frequency of 1.6kHz.
+5V
(1)
+5V
At the same time, the two external reference voltages define
the full-scale input range for the ADS902. This makes it
possible for the input range to be adapted to the signal swing
of the front end.
C1
RS
10Ω 0.1µF
VIN
IN
OPA65x
R1
1kΩ
–5V
ADS902
CM
402Ω
VCM = +2.75V
APPLICATIONS
0.1µF
402Ω
SIGNAL SWING AND COMMON-MODE
CONSIDERATIONS
The ADS902 is designed to operate on a +5V single supply
voltage. The nominal input signal swing is 1Vp-p, situated
between +2.25V and +3.25V. This means that the signal
swings ±0.5V around a common-mode voltage of +2.75V.
In some applications it might be advantageous to increase
the input signal swing to 2Vp-p which will improve the
achievable ac-performance. However, consideration should
be given to keeping the signal swing within the linear region
of operation of the driving circuitry to avoid any excessive
distortion. In extreme situations, the performance of the
converter will start to degrade due to variations of the input’s
switch-on resistance over the input voltage. Therefore, the
FIGURE 3. Typical AC-Coupled Interface Circuit. (External references not shown.)
Figure 4 depicts a circuit that can be used in single-supply
applications. The mid-reference voltage biases the op amp
up to the appropriate common-mode voltage, for example
VCM = +2.75V. With the use of capacitor CG the DC gain for
the non-inverting op amp input is set to +1V/V. As a result
the transfer function is modified to
VOUT = VIN {(1 + RF/RG) + VCM}
+VS
C1
0.1µF
+5V
+3.25V
REFT
RS
VIN
IN
A1
R1
1kΩ
22pF
ADS902
CM
REFB
VCM = +2.75V
RF
RG
RP(1)
CG
NOTE: (1) See text for discussion.
FIGURE 4. AC-Coupled, Single-Supply Interface Circuit.
®
ADS902
+2.25V
0.1µF
8
(3)
connected through a resistor ladder, which has a nominal
resistance of 4kΩ (±15%). In order to establish a correct
voltage drop across the ladder the external reference circuit
must be able to supply typically 250µA of current. With this
current the full-scale input range of the ADS902 is set
between +2.25V and +3.25V. In general, the voltage drop
across REFT and REFB determines the input full-scale
range (FSR) of the ADS902. Equation (4) can be used to
calculate the span.
Again, the input coupling capacitor C1 and resistor R1 form
a high-pass filter. At the same time, the input impedance is
defined by R1. Possible op amps for A1 are CLC452, EL2180
or LM6152. Depending on the selected amplifier, the use of
a pull-up/pull-down resistor (RP), located directly at its
output, may considerably improve its distortion performance.
Resistor RS isolates the op amp’s output from the capacitive
load to avoid gain peaking or even oscillation. It can also be
used to establish a defined bandwidth to reduce the wideband
noise. Its value is usually between 10Ω and 100Ω.
FSR = REFT - REFB
(4)
Depending on the application several options exist how to
supply the external reference voltages to the ADS902 without degrading the typical performance.
DC-COUPLED INTERFACE CIRCUIT
Shown in Figure 5 is a single-supply, DC-coupled circuit
which can be set in a gain of –1V/V or higher. Depending on
the gain determined by RF/RIN, the divider ratio set by resistors
R1 and R2 must be adjusted to yield the correct common-mode
voltage for the ADS902. With a +5V supply, the nominal
signal input range of the ADS902 is 1Vp-p, typically centered
around the common-mode voltage of +2.75V.
LOW-COST REFERENCE SOLUTION
The easiest way to achieve the required reference voltages is
to place the reference ladder of the ADS902 between the
supply rails. Two additional resistors (RT, RB) are necessary
to set the correct current through the ladder (see Figure 6).
However, depending on the desired full-scale swing and
supply voltage, different resistor values might be selected.
EXTERNAL REFERENCE
The ADS902 requires an external top and bottom reference
on pin 22 (REFT) and 24 (REFB). Internally those pins are
RF
External
Top Reference
+VS
RIN
REFT
ADS902
RS
VIN
A1
22pF
2kΩ
CM
R1
REFB
0.1µF
R2
C2
2kΩ
IN
External
Bottom Reference
FIGURE 5. DC-Coupled, Single-Supply Interface Circuit.
+5V
10µF
L1
0.1µF
RT
7kΩ
+3.25V
REFT
+VS
0.1µF
1kΩ
0.1µF
LpBy
VIN
IN
0.1µF
1kΩ
1kΩ
ADS902
+2.75V
0.1µF
CM
1kΩ
LnBy
0.1µF
1kΩ
REFB
+2.25V
0.1µF
RB
9kΩ
FIGURE 6. Low Cost Solution to Supply External Reference Voltages.
®
9
ADS902
When selecting this reference circuit, the trade-offs are
variations in the reference voltages due to component tolerances and power supply variations. In either case, it is
recommended to bypass the reference ladder with at least
0.1µF ceramic capacitors as shown in Figure 6. The purpose
of the capacitors is twofold; they will bypass most of the
high frequency transient noise which results from feedthrough
of the clock and switching noise from the S/H stages and
secondly, they serve as a charge reservoir to supply instantaneous current to internal nodes.
consideration must be made to provide a clock with very low
jitter. Clock jitter leads to aperture jitter (tA) which can be the
ultimate limitation to achieving good SNR performance.
Equation (5) shows the relationship between aperture jitter,
input frequency and the signal-to-noise ratio:
PRECISE REFERENCE SOLUTION
For those applications requiring a higher level of dc accuracy and drift, a reference circuit with a precision reference
element might be used (see Figure 7). A stable +2.5V
reference voltage is established by a two terminal bandgap
reference diode, the REF1004-2.5. Using a general-purpose
single-supply dual operational amplifier (A1), like an
OPA2237, OPA2234 or MC34072, the two required reference voltages for the ADS902 can be generated by setting
each op amp to the appropriate gain. For example, set REFT
to +3.25V and REFB to +2.25V.
DIGITAL OUTPUTS
The digital outputs of the ADS902 are standard CMOS
stages and designed to be compatible with both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows
the ADS902 to directly interface to 3V-logic. The digital
outputs of the ADS902 uses a dedicated digital supply pin
(see Figure 8). By adjusting the voltage on LVDD, the digital
output levels will vary respectively. In any case, it is recommended to limit the fan-out to one, in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
which provide the added benefit of isolating the A/D converter from any digital activities on the bus from coupling
back high frequency noise and degrading the performance.
The standard output coding is Straight Offset Binary where
the full scale input signal corresponds to all “1”s at the
output (see Table I). The digital outputs of the ADS902 can
be set to a high impedance state by driving the OE (pin 16)
with a logic “H”. Normal operation is achieved with a “L”
at OE or left unconnected due to the internal pull-down
resistor.
SNR = 20log10 [1/(2 π fIN tA)]
For example, with a 5MHz full-scale input signal and an
aperture jitter of tA = 20ps rms, the SNR is clock jitter
limited to 54dB.
+VS
10Ω
1/2 A1
+VS
Top
Reference
(Pin 22)
RF1
10kΩ
RG1
5kΩ
REF1004
+2.5V
3kΩ
10Ω
1/2 A1
(5)
+VS
Bottom
Reference
(Pin 24)
1,18, 28
RF2
ADS902
+LVDD
2
Digital
Output
Stage
RG2
FIGURE 8. Independent Supply Connection for Output
Stage.
A1 = OPA2237 or Equivalent.
FIGURE 7. Precise Solution to Supply External Reference
Voltages to the ADS902.
CLOCK INPUT
SINGLE-ENDED INPUT
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
The clock input of the ADS902 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support maximum sampling rates (30MSPS), high speed or
advanced CMOS logic should be used (HC/HCT, AC/ACT).
When digitizing at high sampling rates, a 50% duty cycle
along with fast rise and fall times (2ns or less) are recommended to meet the rated performance specifications. However, the ADS902 performance is tolerant of duty-cycle
variations of as much as ±5%, which should not affect
performance. For applications operating with input frequencies up to Nyquist or undersampling applications, special
+FS (IN = +3.25V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +2.75V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +2.25V)
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
TABLE I. Coding Table for the ADS902.
®
ADS902
10
POWER-DOWN MODE
The ADS902’s low power consumption can be reduced even
further by initiating a power-down mode. To do so, the
Pwrdn-Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by about 88%. In normal
operation the power-down mode is disabled by an internal
pull-down resistor (50kΩ).
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 9 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close to the supply pins as possible.
During power-down, the digital outputs are set into the highimpedance condition (3-state). With the clock applied, the
converter does not accurately process the sampled signal.
After removing the power-down condition the output data
from the following 5 clock cycles is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS902 converter has several supply pins, one of
which is dedicated to supply only the output driver. The
remaining supply pins are not, as is often the case, divided
into analog and digital supply pins since they are internally
connected on the chip. For this reason it is recommended to
treat the converter as an analog component and to power it
from the analog supply only. Digital supply lines often carry
high levels of noise which can couple back into the converter
and limit the achievable performance.
ADS902
+VS
1
GND
13 14
0.1µF
+VS
18
GND
19 20
0.1µF
+VS
28
0.1µF
FIGURE 9. Recommended Bypassing for Analog Supply
Pins.
®
11
ADS902