®
ADS
ADS930
930
E
8-Bit, 30MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
TM
FEATURES
DESCRIPTION
● +3V TO +5V SUPPLY OPERATION
● INTERNAL REFERENCE
The ADS930 is a high speed pipelined analog-todigital converter specified to operate from nominal
+3V or +5V power supplies with tolerances of up to
10%. This complete converter includes a high bandwidth track/hold, a 8-bit quantizer and an internal
reference.
● SINGLE-ENDED INPUT RANGE: 1V to 2V
● LOW POWER: 66mW at +3V
● HIGH SNR: 46dB
● LOW DNL: 0.4LSB
● 28-LEAD SSOP PACKAGE
The ADS930 employs digital error correction techniques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for
telecommunications, video and test instrumentation
applications.
APPLICATIONS
● BATTERY POWERED EQUIPMENT
● CAMCORDERS
This high performance A/D converter is specified for
performance at a 30MHz sampling rate. The ADS930
is available in a 28-lead SSOP package.
● PORTABLE TEST EQUIPMENT
● COMPUTER SCANNERS
● COMMUNICATIONS
CLK
LVDD
ADS930
Timing
Circuitry
2V
IN
1V
T/H
IN
(Opt.)
Pipeline
A/D
Error
Correction
3-State
Outputs
8-Bit
Digital
Data
Internal
Reference
LpBy CM LnBy
1VREF
Pwrdn
OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1997 Burr-Brown Corporation
PDS-1348B
Printed in U.S.A. March, 1997
SPECIFICATIONS
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
ADS930E
PARAMETER
CONDITIONS
RESOLUTION
Specified Temperature Range
ANALOG INPUT
Differential Full Scale Input Range
Single-Ended Full Scale Input Range
Common-mode Voltage
Analog Input Bias Current
Input Impedance
TEMP
UNITS
Bits
°C
8
+85
0.5Vp-p
1Vp-p
1.25
1.0
1.75
2.0
1.5
1
1.25 || 5
V
V
V
µA
MΩ || pF
TTL/HCT Compatible CMOS
2.0
VDD
0.8
±10
±10
5
V
V
µA
µA
pF
Full
Rising Edge of Convert Clock
10k
20M
5
Samples/s
Clk Cyc
Full
Full
Full
±0.4
±0.4
Guaranteed
±1
±1
LSB
LSB
Full
±1.0
±2.5
LSB
Full
Largest Code Error
Largest Code Error
Integral Nonlinearity Error, f = 500kHz
Spurious Free Dynamic Range(1)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dB input)
Two-Tone Intermodulation Distortion(3)
f = 3.4MHz and 3.5MHz (–7dBFS each tone)
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 12MHz (–1dBFS input)
DIGITAL OUTPUTS
Logic Family
Logic Coding
High Output Voltage, VOH
Low Output Voltage, VOL
3-State Enable Time
3-State Disable Time
Internal Pull-Down
Power-Down Enable Time
Power-Down Disable Time
Internal Pull-Down
MAX
–40
CONVERSION CHARACTERISTICS
Start Conversion
Sample Rate
Data Latency
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 3.58MHz (–1dBFS input)
f = 12MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Output Noise
Aperture Delay Time
Aperture Jitter
Analog Input Bandwidth
Small Signal
Full Power
Overvoltage Recovery Time(4)
TYP
Ambient Air
DIGITAL INPUTS
Logic Family
High Input Voltage, VIH
Low Input Voltage, VIL
High Input Current, IIH
Low Input Current, IIL
Input Capacitance
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
f = 12MHz
No Missing Codes
MIN
Full
Full
46
46
51
50
dBFS(2)
dBFS
54
dBc
Full
Full
44
44
46
46
dB
dB
Full
Full
Full
43
42
42
45
45
45
2.3
1
0.2
2
7
dB
dB
dB
%
degrees
LSBs rms
ns
ps rms
350
100
2
MHz
MHz
ns
NTSC, PAL
NTSC, PAL
Input Grounded
–20dBFS Input
0dBFS Input
CL = 15pF
TTL/HCT
Straight Offset Binary
+2.4
OE = L
OE = H
20
2
50
133
18
50
PwrDn = L
PwrDn = H
LVDD
0.4
40
10
V
V
ns
ns
kΩ
ns
ns
kΩ
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADS930
2
SPECIFICATIONS (CONT)
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
ADS930E
PARAMETER
CONDITIONS
ACCURACY
Gain Error
Input Offset
Power Supply Rejection (Gain)
Power Supply Rejection (Offset)
Internal Positive Reference Voltage
Internal Negative Reference Voltage
TEMP
Referred to Ideal Midscale
∆ VS = +10%
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Dissipation
Operating
Operating, +3V
Operating, +3V
Operating, +5V
Operating, +3V
Operating, +5V
Power Dissipation (Power Down)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Thermal Resistance, θJA
28-Lead SSOP
MIN
TYP
MAX
UNITS
10
±60
42
42
5.9
±10
56
56
+1.75
+1.25
%FS
mV
dB
dB
V
V
+3.0
22
66
168
10
15
+5.25
V
mA
mW
mW
mW
mW
+2.7
84
50
°C/W
NOTES: (1) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full scale. (3) Two-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (4) No
"Rollover" of bits.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VS ....................................................................................................... +6V
Analog Input ............................................................................... +VS +0.3V
Logic Input ................................................................................. +VS +0.3V
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS930E
28-Lead SSOP
324
TEMPERATURE
RANGE
–40°C to +85°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
ADS930
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
SSOP
+VS
1
28
+VS
LVDD
2
27
+IN
NC
3
26
CM
NC
4
25
LnBy
LSB Bit 8
5
24
IN
Bit 7
6
23
1VREF
Bit 6
7
22
NC
Bit 5
8
21
LpBy
Bit 4
9
20
GND
Bit 3 10
19
GND
ADS930
Bit 2 11
18
+VS
MSB Bit 1 12
17
Pwrdn
GND 13
16
OE
GND 14
15
CLK
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+VS
LVDD
NC
NC
Bit 8 (LSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1(MSB)
GND
GND
CLK
OE
Pwrdn
+VS
GND
GND
LpBy
NC
1VREF
IN
LnBy
CM
+IN
+VS
DESCRIPTION
Analog Supply
Output Logic Driver Supply Voltage
No Connection
No Connection
Data Bit 8 (D7)
Data Bit 7 (D6)
Data Bit 6 (D5)
Data Bit 5 (D4)
Data Bit 4 (D3)
Data Bit 3 (D2)
Data Bit 2 (D1)
Data Bit 1 (D0)
Analog Ground
Analog Ground
Convert Clock Input
Output Enable, Active Low
Power Down Pin
Analog Supply
Analog Ground
Analog Ground
Positive Ladder Bypass
No Connection
1V Reference Output
Complementary Input
Negative Ladder Bypass
Common-Mode Voltage Output
Analog Input
Analog Supply
TIMING DIAGRAM
N+2
N+1
Analog In
N+4
N+3
N
tD
N+5
tL
tCONV
N+6
N+7
tH
Clock
5 Clock Cycles
t2
Data Out
N–5
N–4
N–3
N–2
N–1
N
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
N+2
t1
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
33
15.5
15.5
®
ADS930
N+1
4
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
16.5
16.5
2
3.9
12
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 500kHz
fIN = 3.58MHz
–20
Amplitude (dB)
Amplitude (dB)
–20
–40
–60
–40
–60
–80
–80
–100
–100
0
5
10
0
15
5
10
SPECTRAL PERFORMANCE
TWO-TONE INTERMODULATION
0
0
fIN = 12MHz
–20
f1 = 3.5MHz at –7dBFS
f2 = 3.4MHz at –7dBFS
2f1 –f2 = 54.7dBFS
2f2 –f1 = 54.2dBFS
–20
Magnitude (dBFS)
Amplitude (dB)
15
Frequency (MHz)
Frequency (MHz)
–40
–60
–80
–40
–60
–80
–100
–100
0
5
10
15
0
2
4
Frequency (MHz)
6
8
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
2.0
2.0
fIN = 500kHz
fIN = 12MHz
1.0
1.0
DLE (LSB)
DLE (LSB)
10
Frequency (MHz)
0.0
–1.0
0.0
–1.0
–2.0
–2.0
0
64
128
192
0
256
Output Code
64
128
192
256
Output Code
®
5
ADS930
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SWEPT POWER SFDR
INTEGRAL LINEARITY ERROR
100
4.0
fIN = 500kHz
dBFS
80
SFDR (dBFS, dBc)
ILE (LSB)
2.0
0
–2.0
60
40
20
dBc
–4.0
0
64
128
192
0
256
–50
–40
Output Code
–20
–10
0
UNDERSAMPLING (With Differential Input)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
0
52
fIN = 20MHz
fS = 16MHz
–20
Amplitude (dB)
SFDR
SFDR, SNR (dB)
–30
Input Amplitude (dBFS)
50
48
–40
–60
–80
SNR
–100
–120
46
0.1
1
10
0
100
1.6
3.2
4.8
6.4
Frequency (MHz)
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
SPURIOUS FREE DYNAMIC RANGE
vs TEMPERATURE
0.7
8.0
54
fIN = 500kHz
0.6
SFDR (dBFS)
DLE (LSB)
52
0.5
0.4
50
fIN = 12MHz
48
0.3
fIN = 500kHz
fIN = 10MHz
0.2
46
–50
–25
0
25
50
75
100
–50
Temperature (°C)
0
25
50
Temperature (°C)
®
ADS930
–25
6
75
100
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
48
SNR (dB)
47
Power Dissipation (mW)
69
fIN = 12MHz
46
fIN = 500kHz
45
44
–50
68
67
66
65
–25
0
25
50
75
100
–50
–25
0
Temperature (°C)
GAIN ERROR vs TEMPERATURE
50
75
100
OFFSET ERROR vs TEMPERATURE
7
6.0
6
Offset Error (mV)
6.5
5.5
5.0
5
4
4.5
3
–50
–25
0
25
50
75
100
–50
–25
Temperature (°C)
0
25
50
75
100
Temperature (°C)
OUTPUT NOISE HISTOGRAM (DC Input)
12
10
Counts (x 105)
Gain (%FSR)
25
Temperature (°C)
8
6
4
2
0
N–2
N–1
N
N+1
N+2
Output Code
®
7
ADS930
THEORY OF OPERATION
Op Amp
Bias
The ADS930 is a high speed sampling analog-to-digital
converter that utilizes a pipeline architecture. The fully
differential topology and digital error correction guarantee
8-bit resolution. The track/hold circuit is shown in Figure 1.
The switches are controlled by an internal clock which has
a non-overlapping two phase signal, φ1 and φ2. At the
sampling time the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase, φ2, the
bottom plates of the input capacitors are connected together
and the feedback capacitors are switched to the op amp
output. At this time the charge redistributes between CI and
CH, completing one track/hold cycle. The differential output
is a held DC representation of the analog input at the sample
time. In the normal mode of operation, the complementary
input is tied to the common-mode voltage. In this case, the
track/hold circuit converts a single-ended input signal into a
fully differential signal for the quantizer. Consequently, the
input signal gets amplified by a gain or two, which improves
the signal-to-noise performance. Other parameters such as
small-signal and full-power bandwidth, and wideband noise
are also defined in this stage.
IN
IN
φ1
φ1
CH
φ2
CI
IN
IN
(Opt.)
φ1
φ2
OUT
φ1
OUT
φ1
CI
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
Digital Delay
(Opt.)
2-Bit
Flash
2-Bit
DAC
+
Σ
–
x2
Digital Delay
2-Bit
Flash
2-Bit
DAC
Digital Error Correction
B1 (MSB)
STAGE 2
+
Σ
–
x2
B2
B3
B4
B5
B6
B7
B8 (LSB)
Digital Delay
2-Bit
Flash
STAGE 6
2-Bit
DAC
+
Σ
–
x2
STAGE 7
2-Bit
Flash
Digital Delay
FIGURE 2. Pipeline A/D Architecture.
®
ADS930
VCM
Internal Non-overlapping Clock
φ1
φ2
φ1
Input
T/H
STAGE 1
VCM
8
signal. The capacitor C1 and resistor R1 form a high-pass
filter with the –3dB frequency set at
The pipelined quantizer architecture has 7 stages with each
stage containing a two-bit quantizer and a two bit digitalto-analog converter, as shown in Figure 2. Each two-bit
quantizer stage converts on the edge of the sub-clock, which
is the same frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
time-align it with the data created from the subsequent
quantizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
provides the ADS930 with excellent differential linearity
and guarantees no missing codes at the 8-bit level.
f–3dB = 1/(2 π R1 C1)
The values for C1 and R1 are not critical in most applications
and can be set freely. The values shown in Figure 3 correspond to a corner frequency of 1.6kHz.
Figure 4 depicts a circuit that can be used in single-supply
applications. The mid-reference biases the op amp up to the
appropriate common-mode voltage, for example VCM =
+1.5V. With the use of capacitor CG, the DC gain for the
non-inverting op amp input is set to +1V/V. As a result, the
transfer function is modified to
The ADS930 includes an internal reference circuit that
provides the bias voltages for the internal stages (for details
see “Internal Reference”). A midpoint voltage is established
by the built-in resistor ladder which is made available at pin
26 “CM”. This voltage can be used to bias the inputs up to
the recommended common-mode voltage or to level shift
the input driving circuitry. The ADS930 can be used in both
a single-ended or differential input configuration. When
operated in single-ended mode, the reference midpoint (pin
26) should be tied to the inverting input, pin 24.
VOUT = VIN {(1 + RF/RG) + VCM}
(3)
Again, the input coupling capacitor C1 and resistor R1 form
a high-pass filter. At the same time, the input impedance is
defined by R1. Resistor RS isolates the op amp’s output from
the capacitive load to avoid gain peaking or even oscillation.
It can also be used to establish a defined bandwidth to reduce
the wideband noise. Its value is usually between 10Ω and
100Ω.
To accommodate a bipolar signal swing, the ADS930 operates with a common-mode voltage (VCM) which is derived
from the internal references. Due to the symmetric resistor
ladder inside the ADS930, VCM is situated between the top
and bottom reference voltage. Equation (1) can be used for
calculating the common-mode voltage level.
VCM = (REFT +REFB)/2
(2)
+3V
+5V
VIN
(1)
C1
10Ω 0.1µF
OPA650
OPA658
IN
IN
R1
1kΩ
–5V
APPLICATIONS
ADS930
CM
402Ω
VCM
DRIVING THE ANALOG INPUTS
Figure 3 shows an example of an ac-coupled, single-ended
interface circuit using high-speed op amps which operate on
dual supplies (OPA650, OPA658). The mid-point reference
voltage, (VCM), biases the bipolar, ground-referenced input
402Ω
FIGURE 3. AC-Coupled Driver.
+3V
+5V
C1
0.1µF
0.1µF
RS
50Ω
VIN
IN
OPA680
R1
1kΩ
22pF
IN
ADS930
CM
VCM
RF
402Ω
0.1µF
RG
402Ω
RP
402Ω
CG
0.1µF
FIGURE 4. Interface Circuit Example Using the Voltage Feedback Amplifier OPA680.
®
9
ADS930
DC-COUPLED INTERFACE CIRCUIT
Figure 5 illustrates an example of a DC-coupled interface
circuit using one high-speed op amp to level-shift the groundreferenced input signal. This serves to condition it for the
input requirements of the ADS930. With a +3V supply the
input signal swings 1Vp-p centered around a typical common-mode voltage of +1.5V. This voltage can be derived
from the internal bottom reference (REFB) and then fed
back through a resistor divider (R1, R2) to level-shift the
driving op amp (A1). A capacitor across R2 will shunt most
of the wideband noise to ground. Depending on the configured gain, the values of resistors R1 and R2 must be adjusted
since the offsetting voltage (VOS) is amplified by the noninverting gain, 1 + (RF/RIN). This example assumes the sum
of R1 and R2 to be 5kΩ, drawing only 250µA from the
bottom reference. Considerations for the selection of a
proper op amp should include its output swing, input common-mode range, and bias current. This circuit can easily be
modified for a +5V operation of the A/D converter, requiring a higher common-mode level (+2.5V).
Figure 6, each end of the resistor ladder (REFT and REFB)
are driven by a buffer amplifier. The ladder has a nominal
resistance of 4kΩ (±15%). The two outputs of the buffers are
brought out at pin 21 (LpBy) and pin 25 (LnBy), primarily
to connect external bypass capacitors, typically 0.1µF. They
will shunt the high frequency switching noise that is fed
back into the reference circuit and improve the performance.
The buffers can drive limited external loads, for example
level-shifting of the converter’s interface circuit. However,
the current draw should be limited to approximately 1mA.
Derived from the top reference of +1.75V is an additional
voltage of +1.0V. Note that this voltage, available on pin 23,
is not buffered and care should be taken when external loads
are applied. In normal operation, this pin is left unconnected
and no bypassing components are required.
CLOCK INPUT
The clock input of the ADS930 is designed to accommodate
either +5V or +3V CMOS logic levels. To drive the clock
input with a minimum amount of duty cycle variation and
support the maximum sampling rate (30MSPS), high speed
or advanced CMOS logic should be used (HC/HCT, AC/
ACT). When digitizing at high sampling rates, a 50% duty
cycle, along with fast rise and fall times (2ns or less), are
INTERNAL REFERENCE
The ADS930 features an internal reference that provides
fixed reference voltages for the internal stages. As shown in
+5V
RF
+3V
VCM = 1.5V
RIN
RS
VIN
ADS930
IN
OPA680
22pF
IN
REFB
+1.25V
CM
VOS
0.1µF
0.1µF
R2
R1
I = 250µA
FIGURE 5. Single-supply, DC-coupled Interface Circuit.
ADS930
+1.75V
21
REFT
LpBy
0.1µF
2kΩ
CM
2.1kΩ
23
26
+1VREF
2.8kΩ
0.1µF
2kΩ
+1.25V
25
REFB
LnBy
0.1µF
FIGURE 6. Internal Reference Structure and Recommended Reference Bypassing.
®
ADS930
10
0.1µF
recommended to meet the rated performance specifications.
However, the ADS930 performance is tolerant to duty cycle
variations of as much as ±10%, which should not affect the
performance. For applications operating with input frequencies up to Nyquist (fCLK/2) or undersampling applications,
special considerations must be made to provide a clock with
very low jitter. Clock jitter leads to aperture jitter (tA) which
can be the ultimate limitation in achieving good SNR performance. Equation (4) shows the relationship between aperture jitter, input frequency and the signal-to-noise ratio:
SNR = 20log10 [1/(2 π fIN tA)]
SINGLE-ENDED INPUT
(IN = 1.5V DC)
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
+FS (IN = +2V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1V)
11111111
11111111
11111110
11100000
11000000
10100000
10000001
10000000
01111111
01100000
01000000
00100000
00000001
00000000
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the A/D converter
from any digital activities on the bus coupling back high
frequency noise which degrades the performance.
POWER-DOWN MODE
The ADS930’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50kΩ).
(4)
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS930 has several supply pins, one of which is
dedicated to supply only the output driver (LVDD). The
remaining supply pins are not divided into analog and digital
supply pins since they are internally connected on the chip.
For this reason, it is recommended that the converter be
treated as an analog component and to power it from the
analog supply only. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins.
TABLE I. Coding Table for the ADS930.
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS930 can be set to a high impedance state by driving
the OE (pin 16) with a logic “HI”. Normal operation is
achieved with pin 16 “LO” or Floating due to internal pulldown resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
The digital outputs of the ADS930 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows
the ADS930 to directly interface to 3V-logic. The digital
output driver of the ADS930 uses a dedicated digital supply
pin (pin 2, LVDD) see Figure 7. By adjusting the voltage on
LVDD, the digital output levels will vary respectively. It is
+VS
ADS930
VS
1
GND
13 14
VS
28
+LVDD
0.1µF
ADS930
GND
19 20
VS
18
Digital
Output
Stage
0.1µF
0.1µF
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.
FIGURE 7. Independent Supply Connection for Output
Stage.
®
11
ADS930