DATASHEET 400MHz Slew Rate Enhanced, Rail-to-Rail Output Gain Block ISL55033 Features The ISL55033 is a triple rail-to-rail output gain block with a -3dB bandwidth of 400MHz and slew rate of 2350V/µs into a 150 load. The ISL55033 has a fixed gain of +2. The inputs are capable of sensing ground. The outputs are capable of swinging to 0.45V to either rail through a 150Ω resistor connected to V+/2. • 400MHz -3dB bandwidth The ISL55033 is designed for general purpose video applications. The part includes a fast-acting global disable/power-down function. • Fast 25ns disable time • 2350V/µs typ slew rate, RL = 150Ωto V+/2 • Single-supply operation from +3V to +5.5V • Rail-to-rail output • Input ground sensing • Pb-free (RoHS compliant) Applications The ISL55033 is available in a 12 Ld TQFN package. Operation is specified over the -40°C to +85°C temperature range. • Video amplifiers • Set-top boxes • Video distribution Pin Configuration 2 IN+_3 3 EN V+_OUTPUT 10 -+ IN+_2 11 -+ 1 12 9 OUTPUT_1 8 OUTPUT_2 7 OUTPUT_3 -+ IN+_1 V+ ISL55033 (12 LD TQFN) TOP VIEW 4 5 6 GND_IN-(1,2,3) GND_PWR GND_OUTPUT EP EACH CHANNEL AV = +2 June 29, 2015 FN6346.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2008, 2015. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL55033 Pin Descriptions PIN NUMBER PIN NAME EQUIVALENT CIRCUIT 1 IN+_1 Circuit 1 Amplifier 1 noninverting input 2 IN+_2 Circuit 1 Amplifier 2 noninverting input 3 IN+_3 Circuit 1 Amplifier 3 noninverting input 4 GND_IN-(1, 2, 3) Circuit 4 Common input for amplifiers 1, 2, 3 inverting inputs 5 GND_PWR 6 GND_OUTPUT Circuit 3 Output power supply ground 7 OUTPUT_3 Circuit 3 Amplifier 3 output 8 OUTPUT_2 Circuit 3 Amplifier 2 output DESCRIPTION Circuits 1, 2, 4, 5 Power supply ground. This is also the potential of the exposed metal pad on the package bottom. 9 OUTPUT_1 Circuit 3 Amplifier 1 output 10 V+_OUTPUT Circuit 3 Output power supply 11 EN Circuit 2 Enable pin with internal pull-down: Logic “1” selects the disabled state; Logic “0” selects the enabled state 12 V+ Circuits 1, 2, 4 EP EP Circuit 5 Positive power supply Package’s exposed thermal pad. Connect to GND_PWR. V+ V+ IN+ V+_OUTPUT EN dV/dt CLAMP OUTPUT (1, 2, 3) GND_OUTPUT GND_PWR GND_PWR CIRCUIT 3 CIRCUIT 2 - + CIRCUIT 1 500 DIE SUBSTRATE GND_PWR ~1MΩ - + - + GND_IN-(1, 2, 3) V+ THERMAL HEAT SINK PAD (EP) 500k GND_PWR CIRCUIT 5 CIRCUIT 4 Ordering Information PART NUMBER (Note 1, 2, 3) PART MARKING ISL55033IRTZ 5033 TEMP RANGE (°C) -40 to +85 PACKAGE (RoHS Compliant) 12 Ld TQFN PKG. DWG. # L12.3x3A NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL55033. For more information on MSL, please see tech brief TB363. Submit Document Feedback 2 FN6346.1 June 29, 2015 ISL55033 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+) + 0.3V to GND - 0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V Charge Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV Thermal Resistance (Typical) . . . . . . . . . . . . . JA (°C/W) JC (°C/W) 12 Ld TQFN Package (Notes 4, 5) . . . . . . . . . 57 10 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Operating Conditions Ambient Operating Temperature Range (TA) . . . . . . . . . . -40°C to +85°C Maximum Operating Junction Temperature (TJ) . . . . . . . . . . . . . . . +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER V+ = V+_OUTPUT = 5V, TA = +25°C, RL = 1kΩ to V+/2, VIN = 0.1VDC, unless otherwise specified. DESCRIPTION TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT -9 -1 9 mV INPUT CHARACTERISTICS VOS Output Offset Voltage (Note 6) TCVOS Offset Voltage Temperature Coefficient Measured from -40°C to +85°C IB Input Bias Current VIN = 0V RIN Input Resistance CIN Input Capacitance -8.5 -3 µV/°C -6 µA 7 MΩ 0.5 pF OUTPUT CHARACTERISTICS ACL Closed Loop Gain VOUT = 0.5V to 4V, RL = 150Ω ROUT Output Resistance AV = +2 VOH Positive Output Voltage Swing RL = 1kΩ to 2.5V RL = 150Ω to 2.5V VOL Negative Output Voltage Swing 1.97 1.99 2.014 V/V 30 mΩ 4.7 4.75 V 4.5 4.55 V RL = 1kΩ to 2.5V RL = 150Ω to 2.5V 27 50 mV 130 200 mV ISC (source) Output Short-circuit Current RL = 10Ωto GND, VIN = 1.5V 50 mA ISC (sink) Output Short-circuit Current RL = 10Ωto + 2.5V, VIN = 0V 50 mA PSRR Power Supply Rejection Ratio V+ = 3V to 5.5V, RL = Open 65 83 IS-ON Supply Current - Enabled VIN = 0.1V, RL = Open 18.5 21.3 24.5 mA IS-OFF Supply Current - All Amplifiers Disabled RL = Open 275 486 900 µA tEN Enable Time RL = 150ΩVIN = 0.5V 250 ns tDS Disable Time RL = 150ΩVIN = 0.5V 25 ns VIL-ENB EN Pin Low Voltage for Power-up 0.8 V VIH-ENB EN Pin High Voltage for Shut-Down 2 V IIH-ENB EN Pin Input Current High VEN = 5V 1 7 15 µA IIL-ENB EN Pin Input Current Low VEN = 0V -10 2 10 µA POWER SUPPLY dB ENABLE Submit Document Feedback 3 FN6346.1 June 29, 2015 ISL55033 Electrical Specifications PARAMETER V+ = V+_OUTPUT = 5V, TA = +25°C, RL = 1kΩ to V+/2, VIN = 0.1VDC, unless otherwise specified. (Continued) DESCRIPTION TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNIT AC PERFORMANCE BW -3dB Bandwidth VOUT = 100mVP-PRL = 150Ω, CL = 2pF, VIN = 1.0 VDC 400 MHz BW ±0.1dB Bandwidth VOUT = 100mVP-PRL = 150Ω, CL = 2pF 60 MHz Peak Gain Peaking VOUT = 100mVP-PRL = 150Ω, CL = 3.2pF 1.5 dB dG Differential Gain 0.012 % dP Differential Phase VIN = 0.1V to 2.0V, VOUT = 100mVP-P, f = 3.58MHz, RL = 150Ω 0.11 ° eN-OUT Output Voltage Noise Density f = 10kHz 35 nV/Hz iN Input Current Noise Density f = 10kHz 2.9 pA/Hz ISO Off-state Isolation fO = 10MHz VIN = 0.8VDC + 1VP-P, CL = 2pF, RL = 150Ω -80 dB X-TALK Channel-to-channel Crosstalk, fO = 10MHz VIN = 0.8VDC + 1VP-P, CL = 2pF, RL = 150Ω -65 dB PSRR Power Supply Rejection Ratio fO = 10MHz VIN = 0.2VDC, VSOURCE = 1VP-P, CL = 2pF, RL = 150Ω -55 dB 2350 V/µs 0.8 ns 0.7 ns 0.6 ns 0.6 ns 0.55 ns 0.55 ns TRANSIENT RESPONSE SR Slew Rate 25% to 75% RL = 150Ω, VOUT = 0.5V to 3.5V tr, tf Large Signal Rise Time, tr 20% to 80% VOUT = 3VP-P RL = 150ΩCL = 2pF Fall Time, tf 80% to 20% Rise Time, tr 20% to 80% VOUT = 2VP-P RL = 150ΩCL = 2pF Fall Time, tf 80% to 20% VOUT = 100mVP-P RL = 150ΩCL = 2pF tr, tf, Small Signal Rise Time, tr 20% to 80% OS Overshoot 100mV step 13 % tPD Propagation Delay 100mV step; RL = 150Ω 1 ns tS 0.1% Settling Time 2V step 65 ns Fall Time, tf 80% to 20% NOTES: 6. VOS is extrapolated from 2 output voltage measurements, with VIN = 62.5mV and VIN = 125mV, RL = 1k. 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Submit Document Feedback 4 FN6346.1 June 29, 2015 ISL55033 Typical Performance Curves 3 2 1 0 -1 -2 -3 -4 -5 RL = 150 V+ = V+_OUT = 5V AV = +2 CL = 2pF VOUT = 100mVP-P VIN(DC) = 0.1V -6 100k RL = 100 100M 10M CL = 7.8pF 4 CL = 5.7pF 2 CL = 4.3pF 0 -2 -4 -6 1M CL = 9.2pF 6 RL = 499 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 8 RL = 1k -8 100k 1G 1M FREQUENCY (Hz) 1G 2 -1 -2 VOUT = 0.1VP-P -3 VOUT = 0.5VP-P -4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 100M 4 0 VOUT = 1.0VP-P -5 VOUT = 1.5VP-P -6 V+ = V+_OUT = 5V AV = +2 -7 RL = 150Ω CL = 2pF -8 VIN(DC) = 0.1V -9 1M 100M 100k 10M FREQUENCY (Hz) 1G 0 -2 -4 VIN(DC) = 2.3V VIN(DC) = 2.2V VIN(DC) = 2.0V VIN(DC) = 1.0V VIN(DC) = 0.1V -6 V+ = V+_OUT = 5V AV = +2 R = 150Ω -8 L CL = 2pF VOUT = 100mVP-P -10 1M 100M 100k 10M FREQUENCY (Hz) 1G FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS DC INPUT VOLTAGES FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS VOUT 7 0.2 0.1 NORMALIZED GAIN (dB) 6 GAIN (dB) 10M FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD 1 ALL CHANNELS 4 3 V+ = V+_OUT = 5V 2 AV = +2 RL = 150Ω CL = 2pF 1 V OUT = 100mVP-P VIN(DC) = 0.1V 0 1M 10k 100k 10M 100M FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS 5 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 FREQUENCY (Hz) Submit Document Feedback CL = 2.0pF FREQUENCY (Hz) FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD 5 CL = 3.2pF V+ = V+_OUT = 5V AV = +2 RL = 150Ω VOUT = 100mVP-P VIN(DC) = 0.1V 1G -0.8 10k V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2pF VOUT = 100mVP-P VIN(DC) = 0.1V 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 6. 0.1 dB GAIN FLATNESS FN6346.1 June 29, 2015 ISL55033 Typical Performance Curves (Continued) 0 0 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2pF VSOURCE = 1VP-P -20 ALL INPUTS = +0.2V DC -40 -50 -60 -70 -40 ALL INPUTS = +0.8VDC -60 -80 -100 -120 -80 -90 10k 100k 10M 1M -140 10k 100M 1M 100k 1G 10000 0 -20 -30 OUTPUT VOLTAGE NOISE (nV/Hz) V+ V V+_OUT = 5V + = 5V +4 AV = +2 150 RL = 150Ω CL = 2pF 3pF CHANNEL) ==2V 4VP-P VOUT (DRIVEN CHANNEL) P- -10 CROSSTALK (dB) 100M FIGURE 8. OFF-ISOLATION vs FREQUENCY FIGURE 7. PSRR vs FREQUENCY P ALL INPUTS = +0.8V DC -40 -50 -60 -70 -80 10k 1M 100k 10M 100M 1000 100 10 1 1G 10 100 FREQUENCY (Hz) 1k 10k 1M 100k 10M FREQUENCY (Hz) FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY FIGURE 10. OUTPUT VOLTAGE NOISE DENSITY vs FREQUENCY 5.5 1000 1.8 5.0 DISABLE 4.5 1.5 4.0 100 ENABLE (V) INPUT CURRENT NOISE (pA/Hz) 10M FREQUENCY (Hz) FREQUENCY (Hz) 10 VOUT 3.5 0.9 2.5 V+ = 5V AV = +2 RL = 150Ω CL = 2pF VIN = 0.5V 2.0 1.5 1.0 0.5 0 1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 11. INPUT CURRENT NOISE DENSITY vs FREQUENCY Submit Document Feedback 6 1.2 3.0 -0.5 0 EN 0.2 0.4 0.6 ENABLE 0.6 0.8 1.0 1.2 1.4 1.6 1.8 OUTPUT (V) PSRR (dB) -30 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2pF VIN = 0.8VDC+1VP-P -20 OFF- ISOLATION (dB) -10 0.3 0 2.0 TIME (µs) FIGURE 12. ENABLE/DISABLE TIMING FN6346.1 June 29, 2015 ISL55033 Typical Performance Curves (Continued) 0.62 3.0 0.60 2.5 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2.0pF VOUT = 100mVP-P 0.56 0.54 2.0 VOLTAGE (V) VOLTAGE (V) 0.58 0.52 1.0 0.5 0.50 0.48 0 5 10 15 20 25 30 35 40 45 0 50 TIME (ns) 5 10 20 25 30 35 40 45 50 0.014 0.012 NORMALIZED GAIN (dB) 3.5 3.0 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2.0pF VOUT = 3VP-P 2.5 2.0 1.5 1.0 0.5 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2pF F = 3.58MHz VOUT = 100mVP-P 0.010 0.008 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 0 5 10 15 20 25 30 35 40 45 50 -0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 TIME (ns) INPUT DC OFFSET (V) FIGURE 15. LARGE SIGNAL (3VP-P) STEP RESPONSE FIGURE 16. DIFFERENTIAL GAIN 1000 0.1 0 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2pF F = 3.58MHz VOUT = 100mVP-P -0.05 -0.10 -0.15 -0.20 ZOUT ENABLED (Ω) 0.05 NORMALIZED PHASE (°) 15 FIGURE 14. LARGE SIGNAL (2VP-P) STEP RESPONSE 4.0 VOLTAGE (V) 0 TIME (ns) FIGURE 13. SMALL SIGNAL STEP RESPONSE 0 V+ = V+_OUT = 5V AV = +2 RL = 150Ω CL = 2.0pF VOUT = 2VP-P 1.5 100 V+ = V+_OUT = 5V AV = +2 CL = 2.0pF VIN = 1.25V DC VSOURCE = 1VP-P 10 1 -0.25 -0.3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 INPUT DC OFFSET (V) FIGURE 17. DIFFERENTIAL PHASE Submit Document Feedback 7 0.1 100k 1M 10M 100M FREQUENCY (Hz) 1G FIGURE 18. ZOUT (ENABLED) vs FREQUENCY FN6346.1 June 29, 2015 ISL55033 Typical Performance Curves (Continued) 1M 100k 1000 100 ZIN (Ω) ZOUT DISABLED (Ω) 10000 V+ = V+_OUT = 5V AV = +2 CL = 2.0pF VIN = 1.25V DC VSOURCE = 1VP-P 10 100k 1M 10k 1k V+ = 5V AV = +2 RL = 150Ω CL = 3.0pF VIN = 1.25V DC VSOURCE = 1VP-P 100 10M 100M FREQUENCY (Hz) 10 100k 1G 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 19. ZOUT (DISABLED) vs FREQUENCY FIGURE 20. ZIN vs FREQUENCY TOTAL SUPPLY CURRENT (mA) 24 20 16 12 8 4 RL = OPEN 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8 SUPPLY VOLTAGE (V) FIGURE 21. SUPPLY CURRENT vs SUPPLY VOLTAGE 720 MAX 7.20 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 1kΩ 7.15 7.10 DISABLED CURRENT (µA) CURRENT PER AMPLIFIER (mA) 7.25 MEDIAN 7.05 7.00 6.95 6.90 MIN 6.85 6.80 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 22. ENABLED SUPPLY CURRENT vs TEMPERATURE Submit Document Feedback 8 MAX 670 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 1kΩ 620 570 520 MEDIAN 470 MIN 420 370 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 23. DISABLED SUPPLY CURRENT vs TEMPERATURE FN6346.1 June 29, 2015 ISL55033 Typical Performance Curves (Continued) 7 4 MAX 6 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 150Ω VOS (mV) 4 3 MEDIAN 2 1 0 1 0 MEDIAN -1 -2 MIN -1 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 1kΩ 2 VOS (mV) 5 MAX 3 MIN -3 -2 -3 -40 -20 0 20 40 60 80 100 -4 -40 120 -20 0 20 TEMPERATURE (°C) FIGURE 24. OUTPUT OFFSET VOLTAGE VOS vs TEMPERATURE -4.5 80 100 120 115 SAMPLE SIZE = 100 VS = 3V to 5.5V MAX MAX 105 PSRR (dB) IBIAS+ (µA) 60 FIGURE 25. OUTPUT OFFSET VOLTAGE VOS vs TEMPERATURE SAMPLE SIZE = 100 V+ = V+_OUT = 5V -5.0 40 TEMPERATURE (°C) -5.5 MEDIAN -6.0 MIN 95 85 MEDIAN -6.5 75 MIN -7.0 -40 -20 0 20 40 60 80 100 65 -40 120 -20 0 20 160 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 150Ω 4.60 4.59 150 VOUT (m V) VOUT (V) MAX 4.56 MEDIAN 4.54 135 MEDIAN 130 MIN 120 4.52 115 MIN 4.50 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 28. VOUT HIGH vs TEMPERATURE Submit Document Feedback 9 120 140 125 4.53 -40 100 MAX 145 4.57 4.51 80 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 150Ω 155 4.58 4.55 60 FIGURE 27. PSRR vs TEMPERATURE FIGURE 26. IBIAS vs TEMPERATURE 4.61 40 TEMPERATURE (°C) TEMPERATURE (°C) 120 110 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 29. VOUT LOW vs TEMPERATURE FN6346.1 June 29, 2015 ISL55033 Typical Performance Curves (Continued) 34 4.78 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 1kΩ 4.77 MAX 30 MAX VOUT (mV) VOUT (V) 4.76 32 SAMPLE SIZE = 100 V+ = V+_OUT = 5V RL = 1kΩ 4.75 MEDIAN 4.74 MEDIAN 28 26 MIN MIN 24 4.73 4.72 -40 -20 0 20 40 60 80 100 120 22 -40 -20 TEMPERATURE (°C) 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 31. VOUT LOW vs TEMPERATURE FIGURE 30. VOUT HIGH vs TEMPERATURE DECOUPLING CAPACITORS (0.1µF || 1nF FOR EACH PIN) V+ EN V+_OUT GND_OUTPUT IN+_3 - + RIN 1 RIN 2 - + IN+_2 - + IN+_1 RIN 3 ROUT 1 OUT_1 OUT_2 ROUT 2 ROUT 3 OUT_3 GND_IN-(1, 2, 3) FIGURE 32. BASIC APPLICATION CIRCUIT Submit Document Feedback 10 FN6346.1 June 29, 2015 ISL55033 Application Information General The ISL55033 single supply, fixed gain, triple amplifier is intended for use in a variety of video and other high speed applications. The device features a ground-sensing PNP input stage and a bipolar rail-to-rail output stage. The three amplifiers have an internally fixed gain of 2 and share a single enable pin as shown in Figure 32. Ground Connections For the best isolation performance and crosstalk rejection, all GND pins must connect directly to the GND plane. In addition, the electrically conductive thermal pad (EP) must also connect directly to ground. Power Considerations Separate V+ power supply and GND pins for the input and output stages are provided to maximize PSRR. Providing separate power pins provides a way to prevent high speed transient currents in the output stage from bleeding into the sensitive amplifier input and gain stages. To maximize crosstalk isolation, each power supply pin should have its own decoupling capacitors connected as close to the pin as possible as shown in Figure 32 (0.1µF in parallel with 1nF recommended). The ESD protection circuits use internal diodes from all pins to the V+ and ground pins. In addition, a dV/dt-triggered clamp is connected between the V+ and V- pins, as shown in Equivalent Circuit 1 on page 2. The dV/dt triggered clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply slew rates in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the maximum supply slew rate is not exceeded. Single Supply Input/Output Considerations For best performance, the input signal voltage range should be maintained between 0.1V to 2.1V. These input limits correspond to an output voltage range of 0.2V to 4.2V and define the limits of linear operation. Figure 4 shows the frequency response versus the input DC voltage level. Figures 16 and 17 show the differential gain-phase performance over the input range of 0V to 2.4V operating into a 150Ω load. The 0.1V to 2.1V input levels corresponds to a 0.2V to 4.2V output levels, which define the minimum and maximum range of output linear operation. Composite video with sync requires care to ensure that the negative sync tip voltage (typically -300mV) is properly level-shifted up into the ISL55033 input linear operating region of +0.1V to 2.1V. The high input impedance enables AC coupling using low values of coupling capacitance with relatively high input voltage divider resistances. amplifiers off. The output presents a relatively high impedance (~2kΩ) to the output pin. Multiplexing several outputs together is possible using the enable/disable function as long as the application can tolerate the limited power-down output impedance. Limiting the Output Current No output short-circuit current limit exists on these parts. All applications need to limit the output current to less than 40mA. Adequate thermal heat sinking of the parts is also required. PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless controlled impedance (50Ωor75Ωstrip lines or microstrips are used. • Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC decoupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Input termination resistors should be as close to the input terminal as possible and output termination resistors as close to the receiving device as possible. • When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • A minimum of two, high frequency, power supply decoupling capacitors (1000pF, 0.1µF), on each V+ pin, are recommended as close to the devices as possible. Avoid vias between the capacitor and the device because vias add unwanted inductance. Larger capacitors (e.g., electrolytics) can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. EN and Power-down States The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 25ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three Submit Document Feedback 11 FN6346.1 June 29, 2015 ISL55033 The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad The thermal pad (EP) is electrically connected to power supply ground (GND_PWR) through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the power ground pins through the substrate, the thermal pad must be tied to the power supply ground to prevent unwanted current flow through the thermal pad. Maximum AC performance is achieved if the thermal pad has good contact to the IC ground pins. Heat sinking requirements can be satisfied using thermal vias directly beneath the thermal pad to a heat dissipating layer of a square at least 1” on a side. Fill the PCB pad under the EP with vias and connect those vias to a substantial ground plane. Reference TB379, section 3) on page 2 and Appendix A, or JEDEC JESD51-5, for more information. l Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION June 29, 2015 FN6346.1 CHANGE -Pin Descriptions table on page 2, updated equivalent circuit as follows: Pin number 4: from Circuit 1 to Circuit 4. Pin number 5: from Circuit 4 to Circuits 1, 2, 4, 5 and added sentence to the description. Pin number 6: from Circuit 4 to Circuit 3. Pin number 10: from Circuit 4 to Circuit 3. Pin number 12: from Circuit 4 to Circuits 1, 2, 4. Added EP details to the table. Updated Circuits 3 and 4 figure. -Ordering information table on page 2: Removed ISL55033EVAL1Z. - Ordering information table on page 2: Added MSL note. -Thermal Information table on page 3, added “Theta jc” and reference “Note 5”. -“Electrical Specification” table on page 3, test condition from V+ = 5V to V+_VOUT = 5V. -Electrical Specification” table on page 3, under enable section changed “Parameter” name “VIH-ENB” to “VIL-ENB” for the 0.8V typical value and changed “Parameter” name “VIL-ENB” to “VIH-ENB” for the 2V typical value. -“PC Board Layout” on page 11, changed reference from “0.01µF” cap to “0.1µF”, removed paragraph referencing “NIC” pins. -updated “The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad” on page 12 paragraph. - Added revision history and about Intersil verbiage. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. 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For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 12 FN6346.1 June 29, 2015 ISL55033 Package Outline Drawing L12.3x3A 12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE Rev 0, 09/07 3.00 0.5 BSC A B 6 12 10 PIN #1 INDEX AREA 6 PIN 1 INDEX AREA 1 4X 1.45 3.00 9 7 3 0.10 M C A B (4X) 0.15 4 6 0.25 +0.05 / -0.07 4 12X 0 . 4 ± 0 . 1 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 75 C BASE PLANE ( 2 . 8 TYP ) 1.45 ) SEATING PLANE 0.08 C ( SIDE VIEW 0.6 C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. 0 . 50 0 . 25 TYPICAL RECOMMENDED LAND PATTERN NOTES: DETAIL "X" 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. Submit Document Feedback 13 FN6346.1 June 29, 2015