ISL55036 ® Data Sheet September 11, 2008 400MHz Slew Rate Enhanced Rail-to-Rail Output Gain Block The ISL55036 is a hex, rail-to-rail output, fixed gain amplifier (G = 4) with a -3dB bandwidth of 400MHz and slew rate of 2500V/µs into a 150Ω load. The ISL55036 features single supply operation over a voltage range of 3VDC to 5.5VDC. The inputs are capable of sensing ground with an output swing of VCC - 0.3V into a 150Ω load tied to V+/2. The part includes a fast-acting global disable/power-down circuit. The ISL55036 is available in a 24 Ld TQFN package. Operation is specified over the -40°C to +85°C temperature range. PACKAGE (Pb-free) PKG. DWG. # 55036 IRTZ 24 Ld TQFN L24.4x5C ISL55036IRTZ-T13* 55036 IRTZ 24 Ld TQFN L24.4x5C ISL55036IRTZ Features • 400MHz -3dB Bandwidth • 2500V/µs Typical Slew Rate, RL = 150Ω • Supplies from 3V to 5.5V • Rail-to-Rail Output (RL = 1k) • Input Ground Sensing • Fast 25ns Disable • Low Cost • Pb-Free (RoHS Compliant) Applications Ordering Information PART MARKING PART NUMBER • Video RGB Line Driver • LCD Based Projectors Pixel Control Pinout ISL55036 24 LD TQFN TOP VIEW 2 GND_IN(1, 2, 3) 3 EN(4, 5, 6) 4 V+(4, 5, 6) 5 IN+_4 6 IN+_5 7 0.70 V+ (1, 2, 3) EN(1, 2, 3) V+ OUT(1,2,3) OUT_1 DIE 1 18 OUT_3 17 GND_OUT(1, 2, 3) 16 GND_PWR(1, 2, 3) 15 V+_OUT(4,5,6) 14 OUT_4 13 OUT_5 -+ 0.60 19 OUT_2 -+ V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VOUT = 250mVP-P 20 DIE 2 5 10 15 20 25 30 35 40 45 TIME (ns) FIGURE 1. SMALL SIGNAL STEP RESPONSE 1 50 10 11 12 OUT_6 0 9 GND_OUT(4, 5, 6) 0.45 8 GND_PWR(4, 5, 6) 0.50 GND_IN(4, 5, 6) 0.55 IN+_6 SMALL SIGNAL (V) 0.75 21 -+ IN+_3 22 -+ 1 23 -+ 0.80 IN+_2 24 -+ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. IN+_1 *Please refer to TB347 for details on reel specifications. 0.65 FN6640.1 AV EACH CHANNEL EQUALS +4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL55036 Pin Descriptions 24 LD TQFN PIN NAME EQUIVALENT CIRCUIT DESCRIPTION 1 IN+_2 Circuit 1 Amplifier 2 non-inverting input 2 IN+_3 Circuit 1 Amplifier 3 non-inverting input 3 GND_IN(1, 2, 3) Circuit 4 Common reference input for Amplifiers 1, 2, 3 4 EN(4, 5, 6) Circuit 2 Enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. Channels 4, 5, 6 5 V+(4, 5, 6) Circuit 5 Positive power supply for Channels 4, 5, 6. 6 IN+_4 Circuit 1 Amplifier 4 non-inverting input 7 IN+_5 Circuit 1 Amplifier 5 non-inverting input 8 IN+_6 Circuit 1 Amplifier 6 non-inverting input 9 GND_IN(4, 5, 6) Circuit 5 Common reference input for Amplifiers 4, 5, 6 10 GND_PWR(4, 5, 6) Circuit 5 Power supply ground for Channels 4, 5, 6. 11 GND_OUT(4, 5, 6) Circuit 3 Output power supply ground for Channels 4, 5, 6. 12 OUT_ 6 Circuit 3 Amplifier 6 output 13 OUT_ 5 Circuit 3 Amplifier 5 output 14 OUT_4 Circuit 3 Amplifier 4 output 15 V+_OUT(4, 5, 6) Circuit 3 Output power supply for Channels 4, 5, 6. 16 GND_PWR(1, 2, 3) Circuit 4 Power supply ground Channels 1, 2, 3. 17 GND_OUT(1, 2, 3) Circuit 3 Output power supply ground Channels 1, 2, 3. 18 OUT_3 Circuit 3 Amplifier 3 output 19 OUT_2 Circuit 3 Amplifier 2 output 20 OUT_1 Circuit 3 Amplifier 1 output 21 V+_OUT(1, 2, 3) Circuit 3 Output power supply Channels 1, 2, 3. 22 EN(1, 2, 3) Circuit 2 Enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects the enabled state. Channels 1, 2, 3 23 V+(1, 2, 3) Circuit 4 Positive power supply for Channels 1, 2, 3. 24 IN+_1 Circuit 1 Amplifier 1 non-inverting input Thermal Pad Circuit 6 Thermal heat sink pad makes electrical contact the IC substrate and must be connected to same ground potential as the ground pins. V+ IN+ 21k EN dv/dt CLAMP + 1.2V - V+ V+_OUT(1, 2, 3) V+_OUT(4, 5, 6) GND_PWR OUT(1, 2, 3) OUT(4, 5, 6) GND_OUT(1, 2, 3) GND_OUT(4, 5, 6) GND_PWR CIRCUIT 1 CIRCUIT 2 GND_PWR(1,2,3) - + - + 500 - + 500 1.5k GND_PWR(4, 5, 6) CIRCUIT 4 CIRCUIT 5 2 V+(4,5,6) SUBSTRATE 1 GND_IN-(4, 5, 6) - + GND_IN-(1,2,3) - + - + V+(1, 2, 3) CIRCUIT 3 1.5k SUBSTRATE 2 GND_PWR (1,2,3) ~1MΩ ~1MΩ GND(4, 5, 6) THERMAL HEAT SINK PAD CIRCUIT 6 FN6640.1 September 11, 2008 ISL55036 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . V+ + 0.3V to GND - 0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Resistance (Typical, Note 1) θJA (°C/W) 24 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . . 42 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER V+ = 5V, TA = +25°C, RL = 1k to V+/2, AV = 4, VIN = 0.1VDC, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT INPUT CHARACTERISTICS TCVOS Offset Voltage Temperature Coefficient Measured from -40°C to +85°C -3 IB Input Bias Current VIN = 0V RIN Input Resistance 7 MΩ CIN Input Capacitance 0.5 pF -10 -5.5 µV/°C -2.5 µA OUTPUT CHARACTERISTICS VOS Output Offset Voltage Note 2 -14 -2 10 mV ACL Closed Loop Gain RL = 1k, 150Ω, VOUT = 0.5V to 4V 3.9 4 4.1 V/V ROUT Output Resistance AV = +4 VOP Positive Output Voltage Swing VON Negative Output Voltage Swing 30 mΩ RL = 1kΩ to 2.5V 4.86 V RL = 150Ω to 2.5V 4.65 V RL = 1kΩ to 2.5V 27 mV RL = 150Ω to 2.5V 140 mV ISC (source) Output Short Circuit Current RL = 10Ω to GND, VIN = 1.5V 60 95 mA ISC (sink) Output Short Circuit Current RL = 10Ω to + 2.5V, VIN = 0V 70 105 mA 78 dB POWER SUPPLY PSRR Power Supply Rejection Ratio @ 1kHz V+ = 5V; VSOURCE = 1VP-P; f = 1kHz sine wave IS-ON Supply Current - Enabled per Amplifier RL = Open 6.0 7.2 8.5 mA IS-OFF Supply Current - All Amplifiers Disabled RL = Open 0.5 1.1 2 mA ENABLE tEN Enable Time RL = 150Ω, VIN = 0.25V 250 ns tDS Disable Time RL = 150Ω, VIN = 0.25V 25 ns VIH-ENB ENABLE Pin Voltage for Power-Up 0.8 V VIL-ENB ENABLE Pin Voltage for Shut-Down 2 V 3 FN6640.1 September 11, 2008 ISL55036 Electrical Specifications PARAMETER V+ = 5V, TA = +25°C, RL = 1k to V+/2, AV = 4, VIN = 0.1VDC, Unless Otherwise Specified. (Continued) DESCRIPTION CONDITIONS MIN (Note 3) TYP MAX (Note 3) UNIT 5.5 20 µA 4 µA IIH-ENB ENABLE Pin Input Current High VEN = 5V 1 IIL-ENB ENABLE Pin Input for Current Low VEN = 0V -4 AC PERFORMANCE BW -3dB Bandwidth RL = 150Ω, CL = 3pF 400 MHz BW ±0.1dB Bandwidth RL = 150Ω, CL = 3pF 40 MHz Peak Peaking RL = 150Ω, CL = 3pF 1 dB dG Differential Gain 0.06 % dP Differential Phase VIN = 0.1V to 1.0V, VOUT = 100mVP-P, f = 3.58MHz, RL = 150Ω 0.01 ° eN-OUT Output Noise Voltage f = 10kHz 50 nV/√Hz iN Input Noise Current f = 10kHz 0.9 pA/√Hz ISO Off-State Isolation fO = 10MHz VIN = 0.6VDC + 1VP-P, CL = 3pF, RL = 150Ω -100 dB X-TALK Die to Die Crosstalk fO = 10MHz VIN = 0.6VDC + 1VP-P, CL = 3pF, RL = 150Ω -85 dB -65 dB -55 dB 2500 V/µs 1.4 ns 1 ns 0.8 ns 0.7 ns 0.75 ns 0.7 ns Same Die Channel-to-Channel Crosstalk, fO = 10MHz PSRR Power Supply Rejection Ratio fO = 10MHz VSOURCE = 1VP-P, CL = 3pF, RL = 150Ω TRANSIENT RESPONSE SR Slew Rate 25% to 75% RL = 150Ω, VOUT = 0.5V to 4.5V tr, tf Large Signal Rise Time, tr 20% to 80% VOUT = 4VP-P, RL = 150Ω, CL = 3pF Fall Time, tf 20% to 80% Rise Time, tr 20% to 80% VOUT = 2VP-P, RL = 150Ω, CL = 3pF Fall Time, tf 20% to 80% tr, tf, Small Signal Rise Time, tr 20% to 80% VOUT = 0.2VP-P, RL = 150Ω, CL = 3pF Fall Time, tf 20% to 80% OS Overshoot 200mV step 5 % tPD Propagation Delay 200mV step 0.6 ns tS 1% Settling Time 2V step 12 ns tEN ENABLE to Output Turn-on Delay Time; 10% EN - 10% VOUT VOUT = 1VDC, RL = 150Ω, CL = 3pF 250 ns ENABLE to Output Turn-off Delay Time; VOUT = 1VDC, RL = 150Ω, CL = 3pF 10% EN - 10% VOUT 25 ns NOTES: 2. VOS is extrapolated from 2 output voltage measurements, with VIN = 62.5mV and VIN = 125mV, RL = 1k. 3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 4 FN6640.1 September 11, 2008 ISL55036 Typical Performance Curves 5 5 RL = 1k 4 4 RL = 499 3 CL = 11.2pF 2 CL = 7.7pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 6 3 -2 -1 0 -1 V+ = 5V AV = +4 CL = 3pF VOUT = 100mVP-P -2 -3 -4 -5 100k RL = 150 RL = 100 1M 10M 100M 1 0 -1 CL = 5.2pF -2 -3 -7 100k 1G 1M FREQUENCY (Hz) 15 14 VOUT = 4VP-P 13 VOUT = 3VP-P -2 VOUT = 100mVP-P -3 VOUT = 1VP-P -4 VOUT = 2VP-P 12 GAIN (dB) NORMALIZED GAIN (dB) 0 -5 -6 -8 10 9 7 6 1M 100M 10M FREQUENCY (Hz) ALL CHANNELS 11 8 V+ = 5V AV = +4 RL = 150Ω CL = 3pF -9 100k V+ = 5V AV = +4 RL = 150Ω CL = 3pF VOUT = 100mVP-P 5 10k 1G 100k 1M 0.1 0 -20 -0.1 -30 V+ = 5V AV = +4 RL = 150Ω CL = 3pF VSOURCE = 1VP- P -40 ALL INPUTS = +0.2V DC PSRR (dB) 0 -10 -0.2 -0.3 -0.4 -0.6 -0.7 -0.8 10k 100M 1G FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS 0.2 -0.5 10M FREQUENCY (Hz) FIGURE 4. -3dB BANDWIDTH vs VOUT NORMALIZED GAIN (dB) 1G FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS CLOAD 1 -7 100M 10M FREQUENCY (Hz) FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS RLOAD -1 CL = 3.0pF -4 V+ = 5V AV = +4 -5 RL = 150Ω -6 VOUT = 100mVP-P -50 -60 V+ = 5V AV = +4 RL = 150Ω CL = 3pF VOUT = 100mVP-P -70 -80 1M 100k 10M FREQUENCY (Hz) FIGURE 6. 0.1 dB GAIN FLATNESS 5 100M -90 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 7. PSRR vs FREQUENCY FN6640.1 September 11, 2008 ISL55036 Typical Performance Curves (Continued) 0 0 OFF ISOLATION (dB) -20 -40 OFF ISOLATION (dB) V+ = 5V AV = +4 RL = 150Ω CL = 3pF VIN = 0.6VDC+1VP-P ALL INPUTS = +0.6VDC -60 -80 V+ = 5V AV = +4 -20 RL = 150Ω CL = 3pF CHANNEL) == 4V 4VP-P VOUT (DRIVEN CHANNEL) P-40 P ALL INPUTS = +0.6V DC -60 CHANNELS ON SAME DIE -80 -100 -100 -120 10k -120 10k CHANNELS ON DIFFERENT DIE 100k 1M 10M FREQUENCY (Hz) 100M 1G 1M 10M FREQUENCY (Hz) 100M 1G FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY FIGURE 8. OFF ISOLATION vs FREQUENCY 100.0 INPUT CURRENT NOISE (pA/√Hz) 10000 OUTPUT VOLTAGE NOISE (nV/√Hz) 100k 1000 100 10 1 10 100 1k 10k 100k 1M 10.0 1.0 0.1 1 10M 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. INPUT REFERRED NOISE CURRENT vs FREQUENCY FIGURE 10. OUTPUT NOISE VOLTAGE vs FREQUENCY 5.5 1.8 0.80 1.5 0.75 DISABLE 4.5 VOUT 3.5 1.2 3.0 0.9 2.5 2.0 V+ = 5V AV = +4 1.5 RL = 150Ω 1.0 CL = 3pF 0.5 VIN = 0.25V 0.6 ENABLE 0.3 OUTPUT (V) ENABLE (V) 4.0 SMALL SIGNAL (V) 5.0 0.70 V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VOUT = 250mVP-P 0.65 0.60 0.55 0.50 0 -0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 TIME (µs) FIGURE 12. ENABLE/DISABLE TIMING 6 0 2.0 0.45 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) FIGURE 13. SMALL SIGNAL STEP RESPONSE FN6640.1 September 11, 2008 ISL55036 Typical Performance Curves (Continued) 4.5 3.0 4.0 2.5 LARGE SIGNAL (V) SMALL SIGNAL (V) 3.5 2.0 V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VOUT = 2VP-P 1.5 1.0 3.0 V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VOUT = 4VP-P 2.5 2.0 1.5 1.0 0.5 0.5 0 0 5 10 15 20 25 30 35 40 45 0 50 0 5 10 15 30 35 40 45 50 0.002 0.02 NORMALIZED PHASE (°) 0.04 0 -0.002 V+ = 5V AV = +4 RL = 150Ω CL = 3pF 0 -0.02 V+ = 5V AV = +4 RL = 150Ω CL = 3pF -0.04 -0.06 -0.08 -0.008 -0.10 -0.010 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 INPUT DC OFFSET (V) INPUT DC OFFSET (V) FIGURE 17. DIFFERENTIAL PHASE FIGURE 16. DIFFERENTIAL GAIN 100k 10k ZIN (Ω) NORMALIZED GAIN (dB) 0.004 -0.006 25 FIGURE 15. LARGE SIGNAL (4VP-P) STEP RESPONSE FIGURE 14. SMALL SIGNAL (2VP-P) STEP RESPONSE -0.004 20 TIME (ns) TIME (ns) 1k 100 100k V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VSOURCE = 100mVP-P 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 18. ZIN vs FREQUENCY 7 FN6640.1 September 11, 2008 ISL55036 Typical Performance Curves (Continued) 10k V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VSOURCE = 100mVP-P 10.00 ZOUT DISABLED (Ω) ZOUT ENABLED (Ω) 100.00 1.00 0.10 0.01 100k 1M 10M 100M FREQUENCY (Hz) 100 V+ = 5V AV = +4 RL = 150Ω CL = 3.0pF VSOURCE = 100mVP-P 10 100k 1G FIGURE 19. ZOUT (ENABLED) vs FREQUENCY 1M 1G 1.21 n = 100 n = 100 MAX 7.7 MAX 1.16 CURRENT (mA) 7.6 7.5 MEDIAN 7.4 7.3 7.2 MIN 1.11 MEDIAN 1.06 MIN 1.01 7.1 7.0 -40 -20 0 20 40 60 0.96 -40 80 -20 TEMPERATURE (°C) 0 20 40 60 80 TEMPERATURE (°C) FIGURE 21. ENABLED SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V FIGURE 22. DISABLED SUPPLY CURRENT vs TEMPERATURE, VS = ±2.5V 6 -4.7 n = 100 MAX -4.9 4 n = 100 MAX -5.1 2 -5.3 0 IBIAS (µA) OUTPUT OFFSET VOLTAGE VOS (µV) 10M 100M FREQUENCY (Hz) FIGURE 20. ZOUT (DISABLED) vs FREQUENCY 7.8 CURRENT PER AMPLIFIER (mA) 1k MEDIAN -2 -5.7 MIN -5.9 -6.1 -4 MIN -6.3 -6 -8 -40 MEDIAN -5.5 -6.5 -20 0 20 40 60 TEMPERATURE (°C) FIGURE 23. OUTPUT OFFSET VOLTAGE VOS vs TEMPERATURE, VS = ±2.5V, RL = 1k 8 80 -6.7 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 24. IBIAS vs TEMPERATURE, VS = ±2.5V FN6640.1 September 11, 2008 ISL55036 Typical Performance Curves (Continued) 120 MAX 115 n = 100 PSRR (dB) 110 105 100 MEDIAN 95 90 MIN 85 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 25. PSRR vs TEMPERATURE 4.5V TO 5.5V Application Information General The ISL55036 single supply, fixed gain hex amplifier is well suited for a variety of video applications. The device features a PNP ground-sensing input stage and a bipolar rail-to-rail output stage. The ISL55036 is designed for general purpose video, communication, instrumentation, and industrial applications. The 6 fixed gain amplifiers operate independently, however, they are organized into 2 triple amplifier groups as shown in Figure 26. Each group has its own set of power supply pins, ground pins, enable-disable logic and input ground reference pins. Ground Connections For the best isolation performance and crosstalk rejection, all GND pins must connect directly to the GND plane. In addition, the electrically conductive thermal pad should also connect directly to ground. Power Considerations Each triple amplifier group has its own power supply and ground pins. There are dedicated V+ OUT and GND VOUT pins to power only the output stage. A separate set of power and ground pins power the rest of each of the triple op amps (V+ and PWR GND). Providing separate power pins provides a way to prevent high speed transient currents in the output stage from bleeding into the sensitive amplifier input and gain stages. To maximize crosstalk isolation, each power supply pin should have its own de-coupling capacitors connected as close to the pin as possible (0.1µF in parallel with 1nF recommended). The ESD protection circuits use internal diodes from all pins to the V+ and ground pins. In addition, a dv/dt-triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 on page 2. The dv/dt triggered 9 clamp imposes a maximum supply turn-on slew rate of 1V/µs. Damaging currents can flow for power supply rates-of-rise in excess of 1V/µs, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the maximum rate of rise is not exceeded. EN and Power-Down States The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 25ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a relatively high impedance (~2kΩ) to the output pin. Multiplexing several outputs together is possible using the enable/disable function as long as the application can tolerate the limited power-down output impedance. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 40mA. Adequate thermal heat sinking of the parts is also required. PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be FN6640.1 September 11, 2008 ISL55036 DECOUPLING CAPACITORS V+(1,2,3) EN(1,2,3) V+_OUT(1,2,3) GND_OUT(4,5,6) -+ IN+_1 -+ RIN 4 IN+_2 RIN 5 -+ IN+_3 RIN 6 DIE 1 GND_IN(1,2,3) DECOUPLING CAPACITORS ROUT 1 OUT_1 OUT_2 ROUT 2 ROUT 3 OUT_3 GND_PWR(1,2,3) V+ (4,5,6) V+_OUT(4,5,6) GND_OUT(4,5,6) -+ IN+_4 IN+_5 -+ RIN 4 RIN 5 -+ IN+_6 RIN 6 DIE 2 GND_IN(4,5,6) ROUT 4 ROUT 5 ROUT 6 OUT_4 OUT_5 OUT_6 GND_PWR(4,5,6) EN(4,5,6) FIGURE 26. BASIC APPLICATION CIRCUIT degraded for traces greater than one inch, unless controlled impedance (50Ω or 75Ω) strip lines or microstrips are used. • Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible. Avoid vias between the capacitor and the device because vias add unwanted inductance. Larger capacitors can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad The thermal pad is electrically connected to power supply ground through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the power ground pins through the substrate, the thermal pad must be tied to the power supply ground to prevent unwanted current flow through the thermal pad. Maximum AC performance is achieved if the thermal pad has good contact to the IC ground pins. Heat sinking requirements can be satisfied using thermal vias directly beneath the thermal pad to a heat dissipating layer of a square at least 1” on a side. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6640.1 September 11, 2008 ISL55036 Package Outline Drawing L24.4x5C 24 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 10/07 4.00 PIN 1 A 2.65 24X0.40 PIN #1 INDEX AREA CHAMFER 0.400 × X 45° INDEX AREA B 6 20 24 6 1 0.50 19 5.00 3.65 0.5x6=3.00 REF 7 13 12 0.10 8 0.23±0.05 4X 0.50 TOP VIEW 0.10 M C A B 0.5x4=2.00 REF BOTTOM VIEW SEE DETAIL X'' 0.10 C C 0.75 SEATING PLANE 0.08 C (24x0.25) SIDE VIEW (4.80 TYP) (3.65) (20x0.50) 0 . 20 REF 5 C (24x0.60) (2.65) (3.80 TYP) 0 . 00 MIN. 0 . 05 MAX. TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.28mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 11 FN6640.1 September 11, 2008