VS-P100 Series Datasheet

VS-P100 Series
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Vishay Semiconductors
Power Modules,
Passivated Assembled Circuit Elements, 25 A
FEATURES
• Glass passivated junctions for greater reliability
• Electrically isolated base plate
• Available up to 1200 VRRM/VDRM
• High dynamic characteristics
• Wide choice of circuit configurations
• Simplified mechanical design and assembly
• UL E78996 approved
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
PACE-PAK (D-19)
DESCRIPTION
PRODUCT SUMMARY
IO
25 A
Type
Modules - Thyristor, Standard
Package
PACE-PAK (D-19)
Circuit
Single phase, hybrid bridge common cathode,
Single phase, hybrid bridge doubler connection,
Single phase, all SCR bridge
The VS-P100 series of integrated power circuits consists of
power thyristors and power diodes configured in a single
package. With its isolating base plate, mechanical designs
are greatly simplified giving advantages of cost reduction
and reduced size.
Applications include power supplies, control circuits and
battery chargers.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
IO
ITSM
I2t
VALUES
UNITS
85 °C
CHARACTERISTICS
25
A
50 Hz
357
60 Hz
375
50 Hz
637
60 Hz
580
I2t
A2s
A2s
6365
VDRM, VRRM
VISOL
TJ
A
Range
TStg
400 to 1200
V
2500
V
-40 to 125
°C
-40 to 125
°C
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
VRRM/VDRM, MAXIMUM
REPETITIVE PEAK REVERSE AND
PEAK OFF-STATE VOLTAGE
V
VRSM, MAXIMUM
NON-REPETITIVE PEAK
REVERSE VOLTAGE
V
VS-P101, VS-P121, VS-P131
400
500
VS-P102, VS-P122, VS-P132
600
700
TYPE NUMBER
VS-P103, VS-P123, VS-P133
800
900
VS-P103, VS-P124, VS-P134
1000
1100
VS-P105, VS-P125, VS-P135
1200
1300
IRRM MAXIMUM
AT TJ MAXIMUM
mA
10
Revision: 27-Mar-14
Document Number: 93754
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VS-P100 Series
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ON-STATE CONDUCTION
PARAMETER
Maximum DC output current at case
temperature
SYMBOL
IO
TEST CONDITIONS
Full bridge
t = 10 ms
Maximum peak, one-cycle non-repetitive
on-state or forward current
ITSM,
IFSM
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
Maximum I2t for fusing
I2t
t = 8.3 ms
t = 10 ms
t = 8.3 ms
Maximum I2t for fusing
Maximum value of threshold voltage
Maximum level value of on-state slope
resistance
I2t
VT(TO)
rt1
VALUES
UNITS
25
A
85
°C
357
No voltage
reapplied
375
300
100 % VRRM
reapplied
Sinusoidal half wave,
initial TJ = TJ maximum
No voltage
reapplied
315
637
580
450
100 % VRRM
reapplied
A
A2s
410
t = 0.1 ms to 10 ms, no voltage reapplied
I2t for time tx = I2t · tx
6365
A2s
TJ = 125 °C
0.82
V
12
m
TJ = 125 °C, average power = VT(TO) x IT(AV) + rt + (IT(RMS))2
Maximum on-state voltage drop
VTM
ITM =  x IT(AV)
TJ = 25 °C
1.35
V
Maximum forward voltage drop
VFM
IFM =  x IF(AV)
TJ = 25 °C
1.35
V
dI/dt
TJ = 125 °C from 0.67 VDRM
ITM =  x IT(AV), Ig = 500 mA, tr < 0.5 μs, tp > 6 μs
200
A/μs
Maximum non-repetitive rate of rise of
turned-on current
Maximum holding current
IH
TJ = 25 °C anode supply = 6 V, resistive load, gate open
130
Maximum latching current
IL
TJ = 25 °C anode supply = 6 V, resistive load
250
mA
BLOCKING
PARAMETER
SYMBOL
VALUES
UNITS
TJ = 125 °C, exponential to 0.67 VDRM gate open
200
V/μs
IRRM,
IDRM
TJ = 125 °C, gate open circuit
10
mA
Maximum peak reverse leakage current
IRRM
TJ = 25 °C
100
μA
RMS isolation voltage
VISOL
50 Hz, circuit to base, all terminals shorted, 
TJ = 25 °C, t = 1 s
2500
V
VALUES
UNITS
Maximum critical rate of rise of off-state
voltage
dV/dt
Maximum peak reverse and off-state
leakage current at VRRM, VDRM
TEST CONDITIONS
TRIGGERING
PARAMETER
Maximum peak gate power
Maximum average gate power
Maximum peak gate current
Maximum peak negative gate voltage
Maximum gate voltage required to trigger
SYMBOL
TEST CONDITIONS
PGM
8
PG(AV)
2
W
IGM
2
A
-VGM
10
V
VGT
TJ = - 40 °C
3
TJ = 25 °C
2
TJ = 125 °C
TJ = - 40 °C
Maximum gate current required to trigger
IGT
Maximum gate voltage that will not trigger
VGD
Maximum gate current that will not trigger
IGD
Anode supply =
6 V resistive load
TJ = 25 °C
TJ = 125 °C
TJ = 125 °C, rated VDRM applied
V
1
90
60
mA
35
0.2
V
2
mA
Revision: 27-Mar-14
Document Number: 93754
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
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THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
-40 to 125
°C
Maximum junction operating
and storage temperature range
TJ, TStg
Maximum thermal resistance,
junction to case per junction
RthJC
DC operation
2.24
Maximum thermal resistance,
case to heatsink
RthCS
Mounting surface, smooth and greased
0.10
K/W
Mounting torque, base to heatsink (1)
Approximate weight
Case style
4
Nm
58
g
2.0
oz.
PACE-PAK (D-19)
Note
(1) A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound
60
+
Maximum Total Power Loss (W)
Maximum Total Power Loss (W)
60
~
50
40
180°
(sine)
30
20
10
TJ = 125 °C
R
50
th
SA
2K
/W
40
=
15
K/
W
3K
/W
30
-Δ
R
5 K/
W
20
7 K/W
10
10 K/W
0
0
0
5
10
15
20
Total Output Current (A)
93754_01a
0
25
25
50
75
100
125
Maximum Allowable
Ambient Temperature (°C)
93754_01b
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)
20
180°
120°
90°
60°
30°
10
Maximum Average On-State
Power Loss (W)
Maximum Average On-State
Power Loss (W)
15
RMS limit
5
Ø
Conduction angle
TJ = 125 °C
Per junction
15
RMS limit
10
Ø
5
Conduction period
TJ = 125 °C
Per junction
0
0
0
93754_02
DC
180°
120°
90°
60°
30°
5
10
15
Average On-State Current (A)
Fig. 2 - On-State Power Loss Characteristics
0
93754_03
5
10
15
20
Average On-State Current (A)
Fig. 3 - On-State Power Loss Characteristics
Revision: 27-Mar-14
Document Number: 93754
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VS-P100 Series
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350
130
At any rated load condition and with
rated VRRM applied following surge.
Initial TJ = 125 °C
at 60 Hz 0.0083 s
at 50 Hz 0.0100 s
120
110
Peak Half Sine Wave
On-State Current (A)
Maximum Allowable Case
Temperature (°C)
Fully turned-on
180°
(Rect.)
100
180°
(Sine)
90
300
250
200
80
Per junction
Per module
70
150
0
5
10
15
20
25
30
1
Total Output Current (A)
93754_04
Fig. 6 - Maximum Non-Repetitive Surge Current
1000
400
TJ = 25 °C
350
Peak Half Sine Wave
On-State Current (A)
Instantaneous On-State Current (A)
100
Number of Equal Amplitude Half
Cycle Current Pulses (N)
93754_06
Fig. 4 - Current Ratings Characteristics
10
TJ = 125 °C
100
10
2
3
4
5
100
0.01
6
Instantaneous On-State Voltage (V)
93754_05
200
Per junction
1
1
250
150
Per junction
0
300
Maximum non-repetitive surge current
versus pulse train duration. Control of
conduction may not be maintained.
Initial TJ = 125 °C
No voltage reapplied
Rated VRRM reapplied
1
Pulse Train Duration (s)
93754_07
Fig. 5 - On-State Voltage Drop Characteristics
0.1
Fig. 7 - Maximum Non-Repetitive Surge Current
ZthJC - Transient Thermal
Impedance (K/W)
10
Steady state value
RthJC = 2.24 K/W
(DC operation)
1
0.1
Per junction
0.01
0.0001
93754_08
0.001
0.01
0.1
1
10
Square Wave Pulse Duration (s)
Fig. 8 - Thermal Impedance ZthJC Characteristics
Revision: 27-Mar-14
Document Number: 93754
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
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Instantaneous Gate Voltage (V)
100
10
(1) PGM = 10 W, tp = 5 ms
(2) PGM = 20 W, tp = 25 ms
(3) PGM = 50 W, tp = 1 ms
(4) PGM = 100 W, tp = 500 μs
Rectangular gate pulse
(a) Recommended load line for
rated dI/dt: 10 V, 20 Ω, tr ≤ 1 μs
(b) Recommended load line for
rated dI/dt: 10 V, 65 Ω, tr ≤ 1 μs
(a)
(b)
0.1
0.001
TJ = 40 °C
VGD
TJ = 25 °C
TJ = 125 °C
1
(1)
(2)
(3)
(4)
Frequency limited by PG(AV)
IGD
0.01
0.1
1
10
100
Instantaneous Gate Current (A)
93754_09
Fig. 9 - Gate Characteristics
ORDERING INFORMATION TABLE
Device code
VS-
P
1
0
2
K
W
1
2
3
4
5
6
7
1
-
Vishay Semiconductors product
2
-
Module type
3
-
Current rating
1 = 25 A DC (P100 Series)
4 = 40 A DC (P400 Series)
4
-
Circuit configuration
0 = Single Phase, Hybrid Bridge Common Cathode
2 = Single Phase, Hybrid Bridge Doubler Connection
3 = Single Phase, all SCR Bridge
5
-
Voltage code
1 = 400 V
2 = 600 V
3 = 800 V
4 = 1000 V
5 = 1200 V
6
-
K = Optional Voltage Suppression
7
-
W = Optional Freewheeling Diode
Revision: 27-Mar-14
Document Number: 93754
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
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CIRCUIT CONFIGURATION
CIRCUIT DESCRIPTION
CIRCUIT
CONFIGURATION
CODE
SCHEMATIC DIAGRAM
TERMINAL POSITIONS
G1
AC1
Single phase, hybrid bridge
common cathode
AC2
0
AC1 G1
-
AC2 G2
+
AC1 G1
-
AC2 G2
+
G2
(-)
(+)
G1
G2
AC2
Single phase, hybrid bridge
doubler connection
AC1
2
(-)
(+)
G3
G1
AC1
Single phase, all SCR bridge
AC2 G2
G1 G4
AC1 G3 +
AC2
3
G4
G2
(-)
CODING
(+)
(1)
CIRCUIT
CONFIGURATION
CODE
BASIC
SERIES
WITH VOLTAGE
SUPPRESSION
WITH
FREEWHEELING
DIODE
WITH BOTH
VOLTAGE SUPPRESSION
AND FREEWHEELING
DIODE
Single phase, hybrid bridge
common cathode
0
P10.
P10.K
P10.W
P10.KW
Single phase, hybrid bridge
doubler connection
2
P12.
P12.K
-
-
Single phase, all SCR bridge
3
P13.
P13.K
-
-
CIRCUIT DESCRIPTION
Note
(1) To complete code refer to Voltage Ratings table, i.e.: For 600 V P10.W complete code is P102W
LINKS TO RELATED DOCUMENTS
Dimensions
www.vishay.com/doc?95335
Revision: 27-Mar-14
Document Number: 93754
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Outline Dimensions
Vishay Semiconductors
D-19 PACE-PAK
DIMENSIONS in millimeters (inches)
0.9 x 45°
(0.035 x 45°)
12.7 (0.50) 12.7 (0.50)
Ø 1.65 (0.06)
4.6 (0.18)
25 (0.98) MAX.
15.5 (0.61)
MAX.
2.5 (0.10)
MAX.
63.5 (2.50)
45 (1.77)
23.2 (0.91)
Fast-on 6.35 x 0.8 (0.25 x 0.03)
5.2 (0.20)
32.5 (1.28) MAX.
33.8 (1.33)
48.7 (1.91)
Document Number: 95335
Revision: 24-Jul-08
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Revision: 02-Oct-12
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