VS-P400 Series www.vishay.com Vishay Semiconductors Power Modules, Passivated Assembled Circuit Elements, 40 A FEATURES • Glass passivated junctions for greater reliability • Electrically isolated base plate • Available up to 1200 VRRM/VDRM • High dynamic characteristics • Wide choice of circuit configurations • Simplified mechanical design and assembly • UL E78996 approved PACE-PAK (D-19) • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 PRODUCT SUMMARY DESCRIPTION IO 40 A Type Modules - Thyristor, Standard Package PACE-PAK (D-19) Circuit Single phase, hybrid bridge common cathode, Single phase, hybrid bridge doubler connection, Single phase, all SCR bridge The VS-P400 series of integrated power circuits consists of power thyristors and power diodes configured in a single package. With its isolating base plate, mechanical designs are greatly simplified giving advantages of cost reduction and reduced size. Applications include power supplies, control circuits and battery chargers. MAJOR RATINGS AND CHARACTERISTICS SYMBOL CHARACTERISTICS VALUES UNITS A IO 80 °C 40 ITSM, IFSM 50 Hz 385 60 Hz 400 50 Hz 745 60 Hz 680 7450 A2s Range 400 to 1200 V 2500 V -40 to 125 °C VRRM/VDRM, MAXIMUM REPETITIVE PEAK REVERSE AND PEAK OFF-STATE VOLTAGE V VRSM, MAXIMUM NON-REPETITIVE PEAK REVERSE VOLTAGE V IRRM MAXIMUM AT TJ MAXIMUM mA VS-P401, VS-P421, VS-P431 400 500 VS-P402, VS-P422, VS-P432 600 700 VS-P403, VS-P423, VS-P433 800 900 VS-P404, VS-P424, VS-P434 1000 1100 VS-P405, VS-P425, VS-P435 1200 1300 I2t I2t VRRM VISOL TJ TStg A A2s ELECTRICAL SPECIFICATIONS VOLTAGE RATINGS TYPE NUMBER 10 Revision: 27-Mar-14 Document Number: 93755 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-P400 Series www.vishay.com Vishay Semiconductors ON-STATE CONDUCTION PARAMETER Maximum DC output current at case temperature SYMBOL IO TEST CONDITIONS Full bridge circuits t = 10 ms Maximum peak, one-cycle non-repetitive on-state or forward current ITSM, IFSM t = 8.3 ms t = 10 ms t = 8.3 ms t = 10 ms Maximum I2t for fusing Maximum I2t for fusing I2t I2t VALUES UNITS 40 A 80 °C 385 No voltage reapplied 400 325 100 % VRRM reapplied Sinusoidal half wave, initial TJ = TJ maximum 340 745 t = 8.3 ms No voltage reapplied t = 10 ms 100 % VRRM 530 t = 8.3 ms reapplied 480 680 t = 0.1 ms to 10 ms, no voltage reapplied I2t for time tx = I2t · tx A 7450 Low level value of threshold voltage VT(TO)1 (16.7 % x x IT(AV) < I < x IT(AV)), TJ = TJ maximum 0.83 High level value of threshold voltage VT(TO)2 (I > x IT(AV)), TJ = TJ maximum 1.03 Low level value of on-state slope resistance rt1 (16.7 % x x IT(AV) < I < x IT(AV)), TJ = TJ maximum 9.61 High level value of on-state slope resistance rt2 (I > x IT(AV)), TJ = TJ maximum 7.01 A2s A2s V m Maximum on-state voltage drop VTM ITM = x IT(AV) TJ = 25 °C 1.4 V Maximum forward voltage drop VFM IFM = x IF(AV) TJ = 25 °C 1.4 V Maximum non-repetitive rate of rise of turned-on current dI/dt TJ = 125 °C from 0.67 VDRM ITM = x IT(AV), Ig = 500 mA, tr < 0.5 μs, tp > 6 μs 200 A/μs Maximum holding current IH Maximum latching current IL TJ = 25 °C anode supply = 6 V, resistive load 130 250 mA BLOCKING PARAMETER SYMBOL VALUES UNITS TJ = 125 °C, exponential to 0.67 VDRM gate open 200 V/μs IRRM, IDRM TJ = 125 °C, gate open circuit 10 mA IRRM TJ = 25 °C 100 μA VISOL 50 Hz, circuit to base, all terminals shorted, TJ = 25 °C, t = 1 s 2500 V VALUES UNITS Maximum critical rate of rise of off-state voltage dV/dt Maximum peak reverse and off-state leakage current at VRRM, VDRM Maximum peak reverse leakage current RMS isolation voltage TEST CONDITIONS TRIGGERING PARAMETER Maximum peak gate power Maximum average gate power Maximum peak gate current Maximum peak negative gate voltage Maximum gate voltage required to trigger SYMBOL TEST CONDITIONS PGM 8 PG(AV) 2 IGM 2 A -VGM 10 V VGT TJ = - 40 °C 3 TJ = 25 °C 2 TJ = 125 °C TJ = - 40 °C Maximum gate current required to trigger W IGT Maximum gate voltage that will not trigger VGD Maximum gate current that will not trigger IGD Anode supply = 6 V resistive load 1 90 TJ = 25 °C 60 TJ = 125 °C 35 TJ = 125 °C, rated VDRM applied V mA 0.2 V 2 mA Revision: 27-Mar-14 Document Number: 93755 2 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-P400 Series www.vishay.com Vishay Semiconductors THERMAL AND MECHANICAL SPECIFICATIONS PARAMETER SYMBOL TEST CONDITIONS VALUES UNITS -40 to 125 °C Maximum junction operating and storage temperature range TJ, TStg Maximum thermal resistance, junction to case per junction RthJC DC operation 1.05 Maximum thermal resistance, case to heatsink RthCS Mounting surface, smooth and greased 0.10 K/W Mounting torque, base to heatsink (1) 4 Approximate weight Nm 58 g 2.0 oz. Case style PACE-PAK (D-19) Note (1) A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound 120 + Maximum Total Power Loss (W) Maximum Total Power Loss (W) 120 ~ 100 80 180° (sine) 60 40 TJ = 125 °C 20 100 R th SA 1K = /W 80 1.5 60 0. 7 K/ W K/W 2K -Δ R /W 3 K/W 40 5 K/W 20 10 K/W 0 0 0 5 10 15 20 25 30 35 Total Output Current (A) 93755_01a 0 40 25 50 75 100 125 Maximum Allowable Ambient Temperature (°C) 93755_01b Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink) 40 25 180° 120° 90° 60° 30° 20 15 RMS limit 10 Ø Conduction angle TJ = 125 °C Per junction 5 Maximum Average On-State Power Loss (W) Maximum Average On-State Power Loss (W) 30 0 DC 180° 120° 90° 60° 30° 30 25 20 RMS limit 15 Ø 10 Conduction period TJ = 125 °C Per junction 5 0 0 93755_02 35 5 10 15 20 Average On-State Current (A) Fig. 2 - On-State Power Loss Characteristics 0 93755_03 5 10 15 20 25 30 35 Average On-State Current (A) Fig. 3 - On-State Power Loss Characteristics Revision: 27-Mar-14 Document Number: 93755 3 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-P400 Series www.vishay.com Vishay Semiconductors 350 130 120 180° (Rect.) 110 100 180° (Sine) 90 80 300 275 250 225 200 175 Per module 70 Per junction 150 0 5 10 15 20 25 30 35 40 45 1 Total Output Current (A) 93755_04 10 100 Number of Equal Amplitude Half Cycle Current Pulses (N) 93755_06 Fig. 4 - Current Ratings Characteristics Fig. 6 - Maximum Non-Repetitive Surge Current 1000 400 Maximum non-repetitive surge current versus pulse train duration. Control of conduction may not be maintained. Initial TJ = 125 °C No voltage reapplied Rated VRRM reapplied TJ = 25 °C Peak Half Sine Wave On-State Current (A) Instantaneous On-State Current (A) At any rated load condition and with rated VRRM applied following surge. Initial TJ = 125 °C at 60 Hz 0.0083 s at 50 Hz 0.0100 s 325 Peak Half Sine Wave On-State Current (A) Maximum Allowable Case Temperature (°C) Fully turned-on TJ = 125 °C 100 10 350 300 250 200 Per junction 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Per junction 150 0.01 5.0 Instantaneous On-State Voltage (V) 93755_05 0.1 1 Pulse Train Duration (s) 93755_07 Fig. 7 - Maximum Non-Repetitive Surge Current Fig. 5 - On-State Voltage Drop Characteristics ZthJC - Transient Thermal Impedance (K/W) 10 Steady state value RthJC = 1.05 K/W (DC operation) 1 Per junction 0.1 0.01 0.0001 93755_08 0.001 0.01 0.1 1 Square Wave Pulse Duration (s) Fig. 8 - Thermal Impedance ZthJC Characteristics Revision: 27-Mar-14 Document Number: 93755 4 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-P400 Series www.vishay.com Vishay Semiconductors Instantaneous Gate Voltage (V) 100 10 (1) PGM = 10 W, tp = 5 ms (2) PGM = 20 W, tp = 25 ms (3) PGM = 50 W, tp = 1 ms (4) PGM = 100 W, tp = 500 μs Rectangular gate pulse (a) Recommended load line for rated dI/dt: 10 V, 20 Ω, tr ≤ 1 μs (b) Recommended load line for rated dI/dt: 10 V, 65 Ω, tr ≤ 1 μs (a) (b) 0.1 0.001 TJ = 40 °C VGD TJ = 25 °C TJ = 125 °C 1 (1) (2) (3) (4) Frequency limited by PG(AV) IGD 0.01 0.1 1 10 100 Instantaneous Gate Current (A) 93755_09 Fig. 9 - Gate Characteristics ORDERING INFORMATION TABLE Device code VS- P 4 0 2 K W 1 2 3 4 5 6 7 1 - Vishay Semiconductors product 2 - Module type 3 - Current rating 1 = 25 A DC (P100 Series) 4 = 40 A DC (P400 Series) 4 - Circuit configuration 0 = Single Phase, Hybrid Bridge Common Cathode 2 = Single Phase, Hybrid Bridge Doubler Connection 3 = Single Phase, all SCR Bridge 5 - Voltage code 1 = 400 V 2 = 600 V 3 = 800 V 4 = 1000 V 5 = 1200 V 6 - K = Optional Voltage Suppression 7 - W = Optional Freewheeling Diode Revision: 27-Mar-14 Document Number: 93755 5 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-P400 Series www.vishay.com Vishay Semiconductors CIRCUIT CONFIGURATION CIRCUIT DESCRIPTION CIRCUIT CONFIGURATION CODE SCHEMATIC DIAGRAM TERMINAL POSITIONS G1 AC1 Single phase, hybrid bridge common cathode AC2 0 AC1 G1 - AC2 G2 + AC1 G1 - AC2 G2 + G2 (-) (+) G1 G2 AC2 Single phase, hybrid bridge doubler connection AC1 2 (-) (+) G3 G1 AC1 Single phase, all SCR bridge AC2 G2 G1 G4 AC1 G3 + AC2 3 G4 G2 (-) CODING (+) (1) CIRCUIT CONFIGURATION CODE BASIC SERIES WITH VOLTAGE SUPPRESSION WITH FREEWHEELING DIODE WITH BOTH VOLTAGE SUPPRESSION AND FREEWHEELING DIODE Single phase, hybrid bridge common cathode 0 P40. P40.K P40.W P40.KW Single phase, hybrid bridge doubler connection 2 P42. P42.K - - Single phase, all SCR bridge 3 P43. P43.K - - CIRCUIT DESCRIPTION Note (1) To complete code refer to Voltage Ratings table, i.e.: For 600 V P40.W complete code is P402W LINKS TO RELATED DOCUMENTS Dimensions www.vishay.com/doc?95335 Revision: 27-Mar-14 Document Number: 93755 6 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Outline Dimensions Vishay Semiconductors D-19 PACE-PAK DIMENSIONS in millimeters (inches) 0.9 x 45° (0.035 x 45°) 12.7 (0.50) 12.7 (0.50) Ø 1.65 (0.06) 4.6 (0.18) 25 (0.98) MAX. 15.5 (0.61) MAX. 2.5 (0.10) MAX. 63.5 (2.50) 45 (1.77) 23.2 (0.91) Fast-on 6.35 x 0.8 (0.25 x 0.03) 5.2 (0.20) 32.5 (1.28) MAX. 33.8 (1.33) 48.7 (1.91) Document Number: 95335 Revision: 24-Jul-08 For technical questions, contact: [email protected] www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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