VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF www.vishay.com Vishay Semiconductors Thyristor/Diode and Thyristor/Thyristor, 500 A (SUPER MAGN-A-PAK Power Modules) FEATURES • High current capability • High surge capability • Industrial standard package • 3000 VRMS isolating voltage with non-toxic substrate • UL approved file E78996 • Designed and qualified for industrial level • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 SUPER MAGN-A-PAK TYPICAL APPLICATIONS • Motor starters • DC motor controls - AC motor controls PRODUCT SUMMARY IT(AV) , IF(AV) 500 A Type Modules - Thyristor, Standard Package SUPER MAGN-A-PAK Circuit Two SCRs doubler circuit • Uninterruptible power supplies MAJOR RATINGS AND CHARACTERISTICS SYMBOL CHARACTERISTICS VALUES UNITS IT(AV) , IF(AV) TC = 82 °C 500 A IT(RMS) TC = 82 °C 785 A 50 Hz 17.8 60 Hz 18.7 ITSM I2t 50 Hz 1591 60 Hz 1452 I2√t kA kA2s 15 910 kA2√s V VRRM Range 800 to 1600 TStg Range -40 to +150 TJ Range -40 to +130 °C ELECTRICAL SPECIFICATIONS VOLTAGE RATINGS TYPE NUMBER VS-VSK.500 VOLTAGE CODE VRRM/VDRM, MAXIMUM REPETITIVE PEAK REVERSE VOLTAGE V VRSM, MAXIMUM NON-REPETITIVE PEAK REVERSE VOLTAGE V 08 800 900 12 1200 1300 14 1400 1500 16 1600 1700 IRRM/IDRM MAXIMUM AT TJ = TJ MAXIMUM mA 100 Revision: 29-Apr-15 Document Number: 94420 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF www.vishay.com Vishay Semiconductors ON-STATE CONDUCTION PARAMETER SYMBOL TEST CONDITIONS A 82 °C 180° conduction, half sine wave at TC = 82 °C 785 A t = 10 ms No voltage reapplied 17.8 100 % VRRM reapplied 15.0 IT(AV), IF(AV) 180° conduction, half sine wave Maximum RMS on-state current IT(RMS) ITSM, IFSM t = 8.3 ms t = 10 ms t = 8.3 ms t = 10 ms Maximum I2t for fusing I2t t = 8.3 ms t = 10 ms t = 8.3 ms Maximum I2√t for fusing I2√t UNITS 500 Maximum average on-state current at case temperature Maximum peak, one-cycle, non-repetitive on-state surge current VALUES No voltage reapplied 18.7 Sinusoidal half wave, initial TJ = TJ maximum 100 % VRRM reapplied t = 0.1 ms to 10 ms, no voltage reapplied kA 15.7 1591 1452 1125 kA2s 1027 15 910 Low level value or threshold voltage VT(TO)1 (16.7 % x π x IT(AV) < I < π x IT(AV)), TJ = TJ maximum 0.85 High level value of threshold voltage VT(TO)2 (I > π x IT(AV)), TJ = TJ maximum 0.93 Low level value on-state slope resistance rt1 (16.7 % x π x IT(AV) < I < π x IT(AV)), TJ = TJ maximum 0.36 High level value on-state slope resistance rt2 (I > π x IT(AV)), TJ = TJ maximum 0.32 kA2√s V mΩ Maximum on-state voltage drop VTM Ipk = 1500 A, TJ = 25 °C, tp = 10 ms sine pulse 1.50 V Maximum forward voltage drop VFM Ipk = 1500 A, TJ = 25 °C, tp = 10 ms sine pulse 1.50 V Maximum holding current IH Maximum latching current IL TJ = 25 °C, anode supply 12 V resistive load 500 1000 mA SWITCHING PARAMETER Maximum rate of rise of turned-on current SYMBOL dI/dt TEST CONDITIONS TJ = TJ maximum, ITM = 400 A, VDRM applied Typical delay time td Gate current 1 A, dIg/dt = 1 A/μs Vd = 0.67 % VDRM, TJ = 25 °C Typical turn-off time tq ITM = 750 A; TJ = TJ maximum, dI/dt = - 60 A/μs, VR = 50 V, dV/dt = 20 V/μs, gate 0 V 100 Ω VALUES UNITS 1000 A/μs 2.0 200 μs BLOCKING PARAMETER Maximum critical rate of rise of off-state voltage SYMBOL dV/dt TEST CONDITIONS VALUES UNITS TJ = 130 °C, linear to VD = 80 % VDRM 1000 V/μs RMS insulation voltage VINS t=1s 3000 V Maximum peak reverse and off-state leakage current IRRM, IDRM TJ = TJ maximum, rated VDRM/VRRM applied 100 mA Revision: 29-Apr-15 Document Number: 94420 2 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF www.vishay.com Vishay Semiconductors TRIGGERING PARAMETER SYMBOL Maximum peak gate power PGM Maximum peak average gate power PG(AV) Maximum peak positive gate current +IGM Maximum peak positive gate voltage +VGM Maximum peak negative gate voltage -VGM Maximum DC gate current required to trigger IGT DC gate voltage required to trigger VGT DC gate current not to trigger IGD DC gate voltage not to trigger VGD TEST CONDITIONS VALUES TJ = TJ maximum, tp ≤ 5 ms 10 TJ = TJ maximum, f = 50 Hz, d% = 50 2.0 3.0 TJ = TJ maximum, tp ≤ 5 ms 20 5.0 200 TJ = 25 °C, Vak 12 V UNITS W A V mA 3.0 V 10 mA 0.25 V VALUES UNITS TJ = TJ maximum THERMAL AND MECHANICAL SPECIFICATIONS PARAMETER SYMBOL Maximum junction operating temperature range TEST CONDITIONS TJ -40 to +130 Maximum storage temperature range TStg -40 to +150 Maximum thermal resistance, junction to case per junction RthJC Maximum thermal resistance, case to heatsink per module RthC-hs DC operation 0.065 Mounting surface smooth, flat and greased 0.02 °C K/W SMAP to heatsink Mounting torque ± 10 % busbar to SMAP A mounting compound is recommended and the torque should be rechecked after a period of 3 hours to allow for the spread of the compound. 6 to 8 Nm 12 to 15 Approximate weight 1500 Case style See dimensions - link at the end of datasheet g SUPER MAGN-A-PAK ΔRthJC CONDUCTION CONDUCTION ANGLE SINUSOIDAL CONDUCTION RECTANGULAR CONDUCTION 180° 0.009 0.006 120° 0.011 0.011 90° 0.014 0.015 60° 0.021 0.022 30° 0.037 0.038 TEST CONDITIONS UNITS TJ = TJ maximum K/W Note • Table shows the increment of thermal resistance RthJC when devices operate at different conduction angles than DC Revision: 29-Apr-15 Document Number: 94420 3 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF 130 VSK.500.. Series R thJC (DC) = 0.065 K/ W 120 110 Conduc tion Angle 100 90 30° 80 60° 90° 120° 70 180° 60 0 100 200 300 400 500 600 Maximum Average On-state Power Loss (W) Vishay Semiconductors DC 180° 120° 90° 60° 30° 900 800 700 600 500 400 RMS Limit Conduction Period 300 VSK.500.. Series Per Junc tion TJ = 130°C 200 100 0 0 100 200 300 400 500 600 700 800 Average On-state Current (A) Average On-state Current (A) Fig. 4 - On-State Power Loss Characteristics 130 VSK.500.. Series R thJC (DC) = 0.065 K/ W 120 110 Conduction Period 100 90 80 30° 60° 90° 120° 180° 70 DC 60 0 180° 120° 90° 60° 30° 400 RMSLimit 300 Conduc tion Angle 200 VSK.500.. Series Per Junction TJ= 130°C 100 0 0 14000 100 200 300 400 @60 Hz 0.0083 s @50 Hz 0.0100 s 13000 12000 11000 10000 9000 VSK.500.. Series Per Junction 8000 7000 1 10 100 Fig. 5 - Maximum Non-Repetitive Surge Current 500 Average On-state Current (A) Fig. 3 - On-State Power Loss Characteristics Peak Half Sine Wave On-state Current (A) 700 500 At Any Rated Loa d Cond ition And With Rated VRRM Ap p lied Following Surge. Initial TJ = 130°C 15000 Number Of Equal Amplitude Half Cycle Current Pulses (N) Fig. 2 - Current Ratings Characteristics 600 16000 100 200 300 400 500 600 700 800 900 Average On-state Current (A) Maximum Average On-state Power Loss (W) 1000 Fig. 1 - Current Ratings Characteristics Peak Half Sine Wave On-state Current (A) Maximum Allowable Case Temperature (°C) Maximum Allowable Case Temperature (°C) www.vishay.com 18000 16000 14000 Ma ximum Non Rep etitive Surge Current Versus Pulse Train Dura tion. Control Of Cond uc tion Ma y Not Be Maintained. Initial TJ = 130°C No Voltage Reapplied Rated VRRMReapplied 12000 10000 8000 VSK.500.. Series Per Junction 6000 0.01 0.1 1 Pulse Train Duration (s) Fig. 6 - Maximum Non-Repetitive Surge Current Revision: 29-Apr-15 Document Number: 94420 4 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF Vishay Semiconductors = W K/ W K/ SA R th 09 0. 750 700 180° 650 120° 0. 16 90° 600 K/ 60° W 550 0.2 30° K/ 500 Conduction Angle W 450 400 0.3 K/ W 350 0 .4 K 300 /W 250 0.6 K 200 /W 150 VSK.500.. Series Per Module 100 TJ = 130°C 50 0 0 100 200 300 400 500 600 700 800 0 20 12 0. 07 0. W K/ e lt -D a R Maximum Total On-state Power Loss (W) www.vishay.com 40 60 80 100 120 Maximum Allowable Ambient Temperature (°C) Total RMSOutput Current (A) Fig. 7 - On-State Power Loss Characteristics 0. 02 K/ W 1000 0.0 8K /W 0.12 K/ W 0.2 K /W 2 x VSK.500.. Series Single Phase Bridge Connected T J = 130°C 500 R K/ W ta el -D 1500 W K/ 0.0 5 01 0. 2000 K/ W = 0. 03 A hS 180° (Sine) 180° (Rect) 2500 Rt Maximum Total Power Loss (W) 3000 0 0 200 400 600 800 0 1000 Total Output Current (A) 20 40 60 80 100 120 Maximum Allowable Ambient Temperature (°C) Fig. 8 - On-State Power Loss Characteristics R 4000 120° (Rect) 3500 SA th Maximum Total Power Loss (W) 4500 0. 02 K/ W 0.0 3K /W 3000 2500 2000 1500 3 x VSK.500.. Series Three Phase Bridge Connected T J = 130°C 1000 500 = 0. 01 K/ W -D el ta R 0.0 5K /W 0.08 K/ W 0.2 K/ W 0 0 250 500 750 0 1000 1250 1500 Total Output Current (A) 20 40 60 80 100 120 Maximum Allowable Ambient Temperature (°C) Fig. 9 - On-State Power Loss Characteristics Revision: 29-Apr-15 Document Number: 94420 5 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF www.vishay.com Vishay Semiconductors Transient Thermal Impedance Z thJC (K/ W) Instantaneous On-state Current (A) 10000 TJ= 25°C 1000 TJ= 130°C VSK.500.. Series Per Junction 100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0.1 VSK.500.. Series Per Junc tion 0.01 Steady State Value: RthJC = 0.065 K/ W (DC Operation) 0.001 0.001 0.01 0.1 1 10 100 Instantaneous On-state Voltage (V) Square Wave Pulse Duration (s) Fig. 10 - On-State Voltage Drop Characteristics Fig. 11 - Thermal Impedance ZthJC Characteristics Rectangular gate pulse a) Recommended load line for rated di/ dt : 20V, 10ohms; tr<=1 µs b) Recommended load line for <=30% rated di/ dt : 10V, 10ohms 10 tr<=1 µs (1) PGM (2) PGM (3) PGM (4) PGM = 10W, = 20W, = 40W, = 60W, tp tp tp tp = 4ms = 2ms = 1ms = 0.66ms (a) (b) 1 VGD IGD 0.1 0.001 Tj=-40 °C Tj=25 °C Tj=130 °C Instantaneous Gate Voltage (V) 100 (1) VSK.500.. Series 0.01 0.1 (2) (3) (4) Frequency Limited by PG(AV) 1 10 100 Instantaneous Gate Current (A) Fig. 12 - Gate Characteristics ORDERING INFORMATION TABLE Device code VS- VSK 1 2 T 500 3 4 - 16 PbF 5 6 1 - Vishay Semiconductors product 2 - Module type 3 - Circuit configuration (see end of datasheet) 4 - Current rating 5 - Voltage code x 100 = VRRM (see Voltage Ratings table) 6 - Lead (Pb)-free Note • To order the optional hardware go to www.vishay.com/doc?95172 Revision: 29-Apr-15 Document Number: 94420 6 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VS-VSKT500-..PbF, VS-VSKH500-..PbF, VS-VSKL500-..PbF www.vishay.com Vishay Semiconductors CIRCUIT CONFIGURATION CIRCUIT DESCRIPTION CIRCUIT CONFIGURATION CODE CIRCUIT DRAWING VSKT... 1 ~ Two SCRs doubler circuit + T 2 - 3 4 (K1) 7 (K2) 5 (G1) 6 (G2) VSKH... 1 ~ SCR/diode doubler circuit, positive control + H 2 - 3 4 (K1) 5 (G1) VSKL... 1 ~ SCR/diode doubler circuit, negative control + L 2 3 - 7 (K2) 6 (G2) LINKS TO RELATED DOCUMENTS Dimensions www.vishay.com/doc?95283 Revision: 29-Apr-15 Document Number: 94420 7 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Outline Dimensions www.vishay.com Vishay Semiconductors Super MAGN-A-PAK Thyristor/Diode DIMENSIONS in millimeters (inches) 52 (2.05) 16 (0.63) 9.9 ± 0.5 (0.39 ± 0.02) Ø 6.5 mm ± 0.3 mm x 4 Holes (Typ.) 31.0 (1.22) 44.0 (1.73) 50.0 (1.97) Fast-on tabs 2.8 x 0.8 (0.11 x 0.03) 3 2 26.0 (0.98) 26.0 (0.98) 4 6 7 20.1 (0.78) 1 5 28.0 (1.10) 48.0 (1.89) 60.0 (2.36) M10 36.4 (1.14) 4.5 (0.20) 112.0 (4.41) 124.0 (4.88) 5, 6 = Gate 4, 7 = Cathode 1.0 (0.039) 149.0 (5.67) Revision: 09-Mar-15 Document Number: 95283 1 For technical questions within your region: [email protected], [email protected], [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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