CCD Delay Line Series MN3890S NTSC-Compatible CCD 1 H Video Signal Delay Element Overview The MN3890S is a 1 H image delay element of a 4 fSC CMOS CCD and suitable for video signal processing applications. It contains such components as a frequency-doubler circuit, a shift register clock driver, a 906-stage CCD analog shift register, and a resampling output amplifier. The MN3885S drives and samples the 906-stage analog shift register using a redoubled version of the supplied clock signal with a frequency 7.16 MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces a delay of 1 H (the horizontal scan period). Pin Assignment VIN 1 8 VO VBB 2 7 VGC VDD 3 6 PCOUT & VCOIN VSS 4 5 XI ( TOP VIEW ) SOP008-P-0225A Features Single 5.0 V power supply Energy-saving design based on CMOS process Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MN3890S consists of the operational blocks shown in the block diagram. Frequency-doubler circuit When the 7.16 MHz of the doubled NTSC color signal subcarrier frequency is inputted from the clock input pin XI, 14.32 MHz clock of fourfold frequency of color signal subcarrier is generated by this circuit. The shift register samples the shift register input with the sampling clock øS, and converts the results to charges, and uses transfer clocks ø1 and ø2 to transfer the results to the following block, the charge detection block, where the charges is converted into a voltage signal. Resampling output amplifier In the output amplifier, this voltage signal is done Sample-and-Hold by resampling, and Y-signal as it is outputted at Vo. Clock driver This block generates two transfer clock signals, ø1 and ø2, synchronized with the 14.32 MHz clock signal from the frequency-doubler circuit. It also generates the sampling clock signals øS and øS', resampling clock signal øSH, and reset clock signal øR that have adjusted timing relations with ø1 and ø2. CCD analog shift register This block first converts the analog signal from the VIN input signal pin into a voltage signal, and inputs it into 906-stage analog shift register. Operation The following is an explanation of delay line operation. The waveforms driving the shift registers are as shown in the timing chart on page 622. The input signal voltage sampled during the interval between t=0 and t=τc (where τc is one-half the sampling interval) appears at the V O output pin at the point t=1813τc. 1 MN3890S CCD Delay Line Series 3 7 V GC VDD Block Diagram Booster circuit Bias circuit VIN Charge input block 1 CCD 906 stages Charge detection block Resampling output amplifier øS driver Waveform adjustment block øR driver ø1 driver øSH driver Timing adjustment 1/2nd frequency doubler Phase comparator 4 PCOUT & VCOIN 6 2 Substrate bias generator VCO 2 Waveform amplifier adjustment block øSH driver VBB 5 VSS XI ø2 driver 8 VO CCD Delay Line Series MN3890S Pin Descriptions Pin No. 1 Symbol VIN Function Description Signal input pin 2 VBB Substrate connection pin 3 VDD Power supply 4 VSS Ground 5 XI 7.16 MHz clock input pin 6 PCOUT & VCOIN 7 VGC Output gate connection pin 8 VO Signal output pin Remarks Negative voltage pin Phase comparator output and voltage controlled oscillator input Operating Conditions Parameter Power supply voltage Symbol VDD Input clock frequency min 4.75 fck Signal bandwidth Input clock amplitude (sine wave) Ambient temperature typ 5.00 max 5.25 Unit V 7.15909 Vck 0.2 Ta –20 MHz 0.3 1.0 VP–P 60 ˚C Electrical Characteristics VDD=5.0V, Vck=0.3VP-P (sine wave), Vin=0.5VP-P (sine wave), fck=7.15909MHz, fsig=200kHz, Ta=25˚C Parameter Power supply current Conditions Symbol min IDD typ 23 max 46 Unit mA Signal bandwidth BW –3 dB for 200 kHz value 2.5 5.5 Insertion gain IG fsig=200kHz –1.5 1.5 4.5 MHz Total harmonic distortion THD fsig=200kHz 1 4.5 Signal-to-noise ratio S/N Signal output (VP-P)/noise output (rms) 48 56 Clock leak 1 NC1 7.16 MHz component/main output signal –50 –40 dB Clock leak 2 NC2 14.32 MHz component/main output signal –20 –10 dB 0.9 kΩ dB % dB Delay τD 63.32 Output impedance Zo 0.5 µs Input bias voltage VBIN Applied to input from VIN signal input pin 2.85 V Output bias voltage VBO Applied to output from VO signal output pin 2.85 V Substrate voltage –VBB –2.8 V 3 MN3890S CCD Delay Line Series Timing Chart 906 stages t=0 t=τc t=1813τc ø1 ø2 øS øSH øR A2 VIN A1 A2 VO A1 4 CCD Delay Line Series MN3890S Application Circuit Example + 5V 10µF 7 VGC 3 VDD – 0.1µF Booster circuit Bias circuit Signal input – + VIN Charge input block 1 0.47µF 0.01µF CCD 906 stages Charge detection block Resampling output amplifier Signal output 8 VO 330Ω øS driver Waveform adjustment block øR driver ø1 driver øSH driver Timing adjustment Phase comparator 1/2nd frequency doubler 0.01µF 820Ω Substrate bias generator VCO 2 amplifier adjustment block øSH driver VBB 1000pF VSS 4 XI 5 Waveform PCOUT & 6 VCOIN Clock input ø2 driver 0.01µF 4700pF 5 MN3890S CCD Delay Line Series Package Dimensions (Unit:mm) 0.4 0.4±0.25 SOP008-P-0225A 5.0±0.3 8 4 5 4.2±0.3 6.5±0.3 6 0.15 0.65 0.3 1.5±0.2 0.1±0.1 1.27 1