CCD Delay Line Series MN38662S NTSC-Compatible CCD Video Signal Delay Element Overview The MN38662S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 681 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38662S samples the input using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. When the switch input is "H" level, the MN38662S disables the threefold-frequency circuit and samples the input with the image sensor drive frequency (9.53496 MHz or 9.545454 MHz) for the camera's 510 horizontal pixels and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment XIC 1 20 XIV VSS3 2 19 PCOUT & VCOIN VDD3 3 18 –VBB VINC1 4 17 VSS2 N.C. 5 16 VDD2 VINVC 6 15 VINVY VGC1 7 14 SW VO1C 8 13 VINC2 VDD1 9 12 VGC2 VSS1 10 11 VO2Y ( TOP VIEW ) SOP020-P-0300 Features Single 4.8 V power supply Choice of camera and VCR modes, so that both the camera and VCR portions of a video camera with 510 horizontal pixels can use the same MN38662S for signal processing Applications Video cameras 1 MN38662S CCD Delay Line Series L 6 VINC1 H L VGC2 7 Mode switch 79-stage analog shift register 12 VGC1 SW VSS3 2 14 VDD3 Charge input block H 4 3 Clamp circuit Bias circuit VINVC 17 V SS2 16 V DD2 9 10 VSS1 VDD1 Block Diagram Booster circuit Voltage generator Voltage generator L H 602-stage analog shift register Charge input block 3-stage analog shift register Charge input block 3-stage analog shift register H 79-stage analog shift register L Charge detector Resampling output amplifier 8 VO1C L H L 15 H Charge input block L XIV 20 L 1 1/3rd frequency divider Waveform amplifier adjustment block L øS driver L Waveform adjustment block ø1 driver øR driver øSH driver VCO H Phase comparator Timing adjustment 19 L H VSS PCOUT & VCOIN 2 H Resampling output amplifier H H XIC Charge detector ø2 driver Substrate bias generator –VBB VINC2 H 13 602-stage analog shift register 18 VINVY L 11 VO2Y CCD Delay Line Series MN38662S Application Circuit Example + 4.8V – 10µF Signal input VINVY 15 – + 0.47µF Signal input VINC2 13 – + 0.47µF Clock input XIV 20 1000pF Clock input XIC 1000pF Charge input block H H L Mode switch 79-stage analog shift register Charge input block 3-stage analog shift register Charge input block 3-stage analog shift register 0.01µF 0.01µF VGC1 12 VGC2 7 14 SW VDD3 VSS3 2 9 L VINVC 6 – + 0.47µF Signal input VINC1 4 – + 0.47µF 3 Clamp circuit Bias circuit Signal input 0.1µ 17 VSS2 16 VDD2 0.1µ 10 VSS1 VDD1 0.1µ 4.8V or GND Booster circuit Voltage generator Voltage generator L H 602-stage analog shift register Charge detector Resampling output amplifier L 8 VO1C Signal output (1C) H L H H Charge input block L L L H 602-stage analog shift register 79-stage analog shift register Charge detector Resampling output amplifier L H 11 VO2Y Signal output (2Y) øS driver H H 1 1/3rd frequency divider Waveform amplifier adjustment block L L Waveform adjustment block ø1 driver øR driver øSH driver VCO H Phase comparator Timing adjustment ø2 driver 0.01µF Substrate bias generator –VBB 18 PCOUT & VCOIN 19 L H 0.01µF 1000pF 820Ω Note: If the capacitor attached to pin 18 has a polarity, attach the negative pole to pin 18. 3 MN38662S CCD Delay Line Series Package Dimensions (Unit:mm) SOP020-P-0300 12.60±0.20 20 11 +0.10 0.15 -0.05 7.70±0.30 5.50±0.20 1.10±0.20 0 to 10° 0.30min. 1.27 0.40±0.10 SEATING PLANE 4 0.10±0.10 (0.6) 1.90max. 10 1.50±0.20 1