Si8406DB www.vishay.com Vishay Siliconix N-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 20 RDS(on) () MAX. ID (A) 0.033 at VGS = 4.5 V 16 e 0.037 at VGS = 2.5 V 16 e 0.042 at VGS = 1.8 V 15 MICRO FOOT® 1.5 x 1 x xxx xx x 1 m m S 3 D 4 Qg (TYP.) 7.5 nC S 2 TrenchFET® power MOSFET Ultra-small 1.5 mm x 1 mm maximum outline Ultra-thin 0.59 mm maximum height Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Available APPLICATIONS 1 G 6 S mm 1.5 1 Backside View • • • • • Load switch • Battery management • Boost converter D 5 D Bump Side View G Marking Code: xxxx = 8406 xxx = Date / lot traceability code N-Channel MOSFET Ordering Information: Si8406DB-T2-E1 (Lead (Pb)-free and halogen-free) S ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 20 Gate-Source Voltage VGS ±8 TC = 70 °C TA = 25 °C 13.5 ID 7.8 a,b 6.2 a,b TA = 70 °C Pulsed Drain Current (t = 300 μs) Continuous Source-Drain Diode Current Maximum Power Dissipation IDM TC = 25 °C TA = 25 °C 11 IS 2.3 a,b 13 TC = 70 °C 8.4 PD Package Reflow Conditions c W 2.77 a,b 1.77 a,b TA = 70 °C Operating Junction and Storage Temperature Range A 30 TC = 25 °C TA = 25 °C V 16 e TC = 25 °C Continuous Drain Current (TJ = 150 °C) UNIT TJ, Tstg -55 to +150 IR/Convection °C 260 Notes a. Surface mounted on 1" x 1" FR4 board. b. t = 10 s. c. Refer to IPC/JEDEC® (J-STD-020), no manual or hand soldering. d. Case in defined as the top surface of the package. e. TC = 25 °C package limited. THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient a,b Maximum Junction-to-Case (Drain) c Steady State SYMBOL TYPICAL MAXIMUM RthJA 37 45 RthJC 7 9.5 UNIT °C/W Notes a. Surface mounted on 1" x 1" FR4 board. b. Maximum under steady state conditions is 85 °C/W. c. Case is defined as top surface of the package. S15-0932-Rev. B, 20-Apr-15 Document Number: 62530 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8406DB www.vishay.com Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = 250 μA 20 - - V - 18 - - -3 - Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS/TJ VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage ID = 250 μA mV/°C VGS(th) VDS = VGS, ID = 250 μA 0.4 - 0.85 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 8 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS On-State Drain Current a ID(on) Drain-Source On-State Resistance a VDS = 20 V, VGS = 0 V - - 1 VDS = 20 V, VGS = 0 V, TJ = 70 °C - - 10 VDS 5 V, VGS = 4.5 V 5 - - VGS = 4.5 V, ID = 1 A - 0.026 0.033 VGS = 2.5 V, ID = 1 A - 0.028 0.037 VGS = 1.8 V, ID = 1 A - 0.030 0.042 VDS = 10 V, ID = 1 A - 20 RDS(on) Forward Transconductance a gfs μA A S Dynamic b Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg Turn-On Delay Time - - 61 - VDS = 10 V, VGS = 8 V, ID = 1 A - 13 20 pF 7.5 12 - 1.1 - - 0.8 - VGS = 0.1 V, f = 1 MHz - 3.6 - - 7 15 - 18 40 - 30 60 tf - 10 20 td(on) - 5 10 - 17 35 - 25 50 - 10 20 TC = 25 °C - - 20 - - 30 IS = 1 A, VGS = 0 - 0.7 1.2 V - 15 30 ns - 5 10 nC - 8 - - 7 - td(on) tr td(off) Rise Time Turn-Off Delay Time - 146 - Fall Time Turn-On Delay Time 830 - VDS = 10 V, VGS = 4.5 V, ID = 1 A Rise Time Turn-Off Delay Time VDS = 10 V, VGS = 0 V, f = 1 MHz VDD = 10 V, RL = 10 ID 1 A, VGEN = 4.5 V, Rg = 1 VDD = 10 V, RL = 10 ID 1 A, VGEN = 8 V, Rg = 1 tr td(off) Fall Time tf nC ns ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb IF = 1 A, dI/dt = 100 A/μs, TJ = 25 °C A ns Notes a. Pulse test; pulse width 300 μs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S15-0932-Rev. B, 20-Apr-15 Document Number: 62530 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8406DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 30 VGS = 5 V thru 2 V 25 8 ID - Drain Current (A) ID - Drain Current (A) VGS = 1.5 V 20 15 10 6 TC = 25 °C 4 TC = 125 °C 2 5 TC = - 55 °C VGS = 1 V 0 0 0.0 0.5 1.0 1.5 2.0 2.5 VDS - Drain-to-Source Voltage (V) 0.0 3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 1200 0.040 900 C - Capacitance (pF) RDS(on) - On-Resistance (Ω) 0.036 VGS = 1.8 V 0.032 VGS = 2.5 V 0.028 VGS = 4.5 V Ciss 600 300 Coss 0.024 Crss 0.020 0 0 5 10 15 20 25 30 0 8 12 16 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 20 1.6 ID = 1 A RDS(on) - On-Resistance (Normalized) 8 VGS - Gate-to-Source Voltage (V) 4 ID - Drain Current (A) VDS = 10 V 6 VDS = 5 V 4 VDS = 16 V 2 0 0 3 6 9 12 15 ID = 1 A VGS = 2.5 V, 1.8 V 1.4 1.2 VGS = 4.5 V 1.0 0.8 0.6 - 50 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature S15-0932-Rev. B, 20-Apr-15 150 Document Number: 62530 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8406DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 0.08 100 RDS(on) - On-Resistance (Ω) IS - Source Current (A) ID = 1 A TJ = 150 °C 10 TJ = 25 °C 1 0.06 0.04 TJ = 125 °C 0.02 TJ = 25 °C 0.00 0.1 0.0 0.2 0.4 0.6 0.8 1.0 VSD - Source-to-Drain Voltage (V) 0 1.2 0.7 25 0.6 20 Power (W) VGS(th) (V) 30 0.5 ID = 250 μA 10 0.3 5 25 50 75 100 TJ - Temperature (°C) 125 4 5 15 0.4 0 3 On-Resistance vs. Gate-to-Source Voltage 0.8 - 25 2 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage 0.2 - 50 1 0 0.001 150 Threshold Voltage 0.01 0.1 1 Pulse (s) 10 100 1000 Single Pulse Power, Junction-to-Ambient 100 Limited by RDS(on)* ID - Drain Current (A) 10 100 μs 1 ms 1 10 ms 100 ms,1 s 10 s DC 0.1 TA = 25 °C BVDSS Limited 0.01 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient S15-0932-Rev. B, 20-Apr-15 Document Number: 62530 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8406DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 15 20 12 Package Limited Power Dissipation (W) ID - Drain Current (A) 16 12 8 9 6 3 4 0 0 0 25 50 75 100 TC - Ambient Temperature (°C) Current Derating* 125 150 25 50 75 100 125 150 T C - Case Temperature (°C) Power Derating * The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S15-0932-Rev. B, 20-Apr-15 Document Number: 62530 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si8406DB www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 P DM 0.05 t1 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 85 °C/W 0.02 Single Pulse 3. T JM - TA = PDMZthJA(t) 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.05 0.02 Single Pulse 0.1 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62530. S15-0932-Rev. B, 20-Apr-15 Document Number: 62530 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix MICRO FOOT®: 6-Bump (1.5 mm x 1 mm, 0.5 mm Pitch, 0.250 mm Bump Height) S S S G e XXXX D s XXX D D s 6x Ø b1 s Mark on Backside of Die e e s E 6x Ø 0.24 to 0.26 (Note 3) Solder mask ~ Ø 0.25 C NOTE 5 b A2 B A1 A e A e K e Bump (Note 2) Recommended Land Pattern Notes (unless otherwise specified) 1. Six (6) solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu. 2. Backside surface is coated with a Ti/Ni/Ag layer. 3. Non-solder mask defined copper landing pad. 4. Laser marks on the silicon die back. 5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined. 6. • is the location of pin 1 DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.510 0.575 0.590 0.0201 0.0226 0.0232 A1 0.220 0.250 0.280 0.0087 0.0098 0.0110 A2 0.290 0.300 0.310 0.0114 0.0118 0.0122 b 0.297 0.330 0.363 0.0116 0.0129 0.0143 b1 0.250 0.0098 e 0.500 0.0197 s 0.210 0.230 0.250 0.0082 0.0090 0.0098 D 0.920 0.960 1.000 0.0362 0.0378 0.0394 E 1.420 1.460 1.500 0.0559 0.0575 0.0591 K 0.028 0.065 0.102 0.0011 0.0025 0.0040 Note • Use millimeters as the primary measurement. ECN: T15-0140-Rev. A, 20-Apr-15 DWG: 6035 Revison: 20-Apr-15 Document Number: 69426 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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