Si5999EDU Vishay Siliconix Dual P-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) - 20 RDS(on) () ID (A) 0.059 at VGS = - 4.5 V - 6a 0.096 at VGS = - 2.5 V - 6a • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • New Thermally Enhanced PowerPAK® ChipFET® Package - Small Footprint Area - Low On-Resistance - Thin 0.8 mm Profile • Typical ESD Performance 1500 V in HBM • Compliant to RoHS Directive 2002/95/EC Qg (Typ.) 6.9 nC PowerPAK ChipFET Dual 1 2 S1 D1 8 APPLICATIONS 4 S2 D1 7 S1 S2 G2 D2 6 • Load Switch and Charger Switch for Portable Devices • DC/DC Converters 3 G1 Marking Code D2 OA XXX 5 Lot Traceability and Date Code G1 G2 Part # Code Bottom View D1 D2 P-Channel MOSFET P-Channel MOSFET Ordering Information: Si5999EDU-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Symbol VDS VGS TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Continuous Drain Current (TJ = 150 °C) TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Continuous Source-Drain Diode Current Maximum Power Dissipation ID TJ, Tstg Operating Junction and Storage Temperature Range d, e V A - 6a - 1.9b, c 10.4 6.7 IS PD Unit - 6a - 6a - 5b, c - 4b, c - 20 IDM Pulsed Drain Current (t = 300 µs) Soldering Recommendations (Peak Temperature) Limit - 20 ± 12 2.3b, c 1.5b, c - 55 to 150 260 W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambientb, f Maximum Junction-to-Case (Drain) t5s Steady State Symbol RthJA RthJC Typical 43 9.5 Maximum 55 12 Unit °C/W Notes: a. Package limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. See solder profile (www.vishay.com/ppg?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 105 °C/W. Document Number: 67019 S10-2428-Rev. A, 25-Oct-10 www.vishay.com 1 Si5999EDU Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min. VDS VGS = 0 V, ID = - 250 µA - 20 Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS/TJ VDS Temperature Coefficient VGS(th) Temperature Coefficient VGS(th)/TJ Gate-Source Threshold Voltage VGS(th) IGSS Gate-Source Leakage Zero Gate Voltage Drain Current a On-State Drain Current Drain-Source On-State Resistancea Forward Transconductancea IDSS ID(on) RDS(on) gfs ID = - 250 µA VDS = VGS, ID = - 250 µA V - 16 mV/°C 3 - 0.6 - 1.5 VDS = 0 V, VGS = ± 12 V ± 10 VDS = 0 V, VGS = ± 4.5 V ±1 VDS = - 20 V, VGS = 0 V -1 VDS = - 20 V, VGS = 0 V, TJ = 55 °C VDS - 5 V, VGS = - 4.5 V V µA - 10 - 20 A VGS = - 4.5 V, ID = - 3.5 A 0.047 0.059 VGS = - 2.5 V, ID = - 1.5 A 0.077 0.096 VDS = - 10 V, ID = - 3.5 A 11 VDS = - 10 V, VGS = 0 V, f = 1 MHz 141 VDS = - 10 V, VGS = - 10 V, ID = - 5 A 13.2 20 6.9 10.5 VDS = - 10 V, VGS = - 4.5 V, ID = - 5 A 1.6 S b Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Rg 496 121 td(off) f = 1 MHz VDD = - 10 V, RL = 2.5 ID - 4 A, VGEN = - 4.5 V, Rg = 1 2 8 16 17 26 21 32 26 40 tf 13 20 td(on) 6 12 11 22 tr td(off) nC 1.8 td(on) tr pF VDD = - 10 V, RL = 2.5 ID - 4 A, VGEN = - 10 V, Rg = 1 tf 23 35 11 22 ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C -6 - 20 IS = - 4 A, VGS = 0 V IF = - 4 A, dI/dt = 100 A/µs, TJ = 25 °C A - 0.85 - 1.2 V 24 48 ns 10 20 nC 14 10 ns Notes: a. Pulse test; pulse width 300 µs, duty cycle 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 67019 S10-2428-Rev. A, 25-Oct-10 Si5999EDU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10-4 0.04 0.03 IGSS - Gate Current (A) IGSS - Gate Current (mA) 10-5 0.02 IGSS at 150 °C 10-6 10-7 IGSS at 25 °C 10-8 0.01 10-9 10-10 0 0 4 8 12 0 16 4 8 12 16 VGS - Gate-Source Voltage (V) VGS - Gate-Source Voltage (V) Gate Current vs. Gate-Source Voltage Gate Current vs. Gate-Source Voltage 5 20 V GS = 5 V thru 3.5 V V GS = 3 V 4 V GS = 2.5 V 10 ID - Drain Current (A) ID - Drain Current (A) 15 3 2 T C = 25 °C V GS = 2 V 5 1 T C = 125 °C V GS = 1.5 V 0 0.0 0.5 1.0 1.5 T C = - 55 °C 0 0.0 2.0 0.6 1.2 1.8 2.4 VGS - Gate-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) Transfer Characteristics Output Characteristics 1000 0.10 750 0.08 C - Capacitance (pF) RDS(on) - On-Resistance (Ω) V GS = 2.5 V 0.06 V GS = 4.5 V Ciss 500 Coss 250 0.04 Crss 0 0.02 0 5 10 15 20 0 5 10 15 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance Document Number: 67019 S10-2428-Rev. A, 25-Oct-10 20 www.vishay.com 3 Si5999EDU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.5 10 V GS = 4.5 V ID = 5 A V DS = 10 V 6 V DS = 16 V 4 1.3 (Normalized) V DS = 5 V RDS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) ID = 5 A 8 V GS = 2.5 V 1.1 0.9 2 0.7 - 50 0 0 3 6 9 12 15 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 100 150 0.20 RDS(on) - On-Resistance (Ω) IS - Source Current (A) ID = 5 A T J = 150 °C 10 T J = 25 °C 1 0.15 0.10 T J = 125 °C 0.05 T J = 25 °C 0.1 0.0 0.00 0.3 0.6 0.9 0 1.2 2 4 6 8 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 10 30 1.25 25 1.05 Power (W) VGS(th) (V) 20 0.85 ID = 250 μA 15 10 0.65 5 0.45 - 50 - 25 0 25 50 75 TJ - Temperature (°C) Threshold Voltage www.vishay.com 4 100 125 150 0 0.001 0.01 0.1 1 10 100 1000 Time (s) Single Pulse Power, Junction-to-Ambient Document Number: 67019 S10-2428-Rev. A, 25-Oct-10 Si5999EDU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 Limited by R DS(on)* ID - Drain Current (A) 10 100 μs 1 ms 1 10 ms 100 ms 1 s, 10 s 0.1 TA = 25 °C Single Pulse 0.01 0.1 DC BVDSS Limited 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient 12 15 12 Power (W) ID - Drain Current (A) 9 Package Limited 6 9 6 3 3 0 0 0 25 50 75 100 125 150 0 25 50 75 100 125 TC - Case Temperature (°C) TC - Case Temperature (°C) Current Derating* Power Derating, Junction-to-Case 150 1.5 Power (W) 1.2 0.9 0.6 0.3 0.0 0 25 50 75 100 125 TA - Ambient Temperature (°C) Power Derating, Junction-to-Ambient Document Number: 67019 S10-2428-Rev. A, 25-Oct-10 150 * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. www.vishay.com 5 Si5999EDU Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Thermal Impedance Normalized Effective Transient Duty Cycle = 0.5 0.2 0.1 Notes: 0.1 PDM t1 0.05 t2 t 1. Duty Cycle, D = t1 2 2. Per Unit Base = R thJA = 87 °C/W 0.02 3. TJM - TA = PDM Z thJA(t) 4. Surface Mounted Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.05 Single Pulse 0.01 10-4 0.02 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67019. www.vishay.com 6 Document Number: 67019 S10-2428-Rev. A, 25-Oct-10 Package Information www.vishay.com Vishay Siliconix PowerPAK® ChipFET® Case Outline D (7) (6) (5) (1) (2) (3) (4) E (8) Pin #1 indicator Side view of single e b H D1 D(2) D2 K D(3) L G(4) K1 D2 SI(1) GI(2) S2(3) D1(8) D1(7) D2(6) Detail Z G2(4) K2 L D(1) A1 C A Z Side view of dual E1 E2 E3 H D3 D(8) D(7) D(6) S(5) K3 Backside view of dual pad Backside view of single pad DIM. D2(5) MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.85 0.028 0.030 0.033 A1 0 - 0.05 0 - 0.002 b 0.25 0.30 0.35 0.010 0.012 0.014 C 0.15 0.20 0.25 0.006 0.008 0.010 D 2.92 3.00 3.08 0.115 0.118 0.121 D1 1.75 1.87 2.00 0.069 0.074 0.079 D2 1.07 1.20 1.32 0.042 0.047 0.052 D3 0.20 0.25 0.30 0.008 0.010 0.012 E 1.82 1.90 1.98 0.072 0.075 0.078 E1 1.38 1.50 1.63 0.054 0.059 0.064 E2 0.92 1.05 1.17 0.036 0.041 0.046 E3 0.45 0.50 0.55 0.018 0.020 0.022 e 0.65 BSC 0.026 BSC H 0.15 0.20 0.25 0.006 0.008 0.010 K 0.25 - - 0.010 - - K1 0.30 - - 0.012 - - K2 0.20 - - 0.008 - - K3 0.20 - - 0.008 - - L 0.30 0.35 0.40 0.012 0.014 0.016 C14-0630-Rev. E, 21-Jul-14 DWG: 5940 Note • Millimeters will govern Document Number: 73203 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revision: 21-Jul-14 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® ChipFET® Dual 2.700 (0.106) 0.300 (0.012) 0.350 (0.014) 0.650 (0.026) 1.900 (0.075) 0.300 (0.012) 1.050 (0.041) 0.350 (0.014) 0.200 (0.008) 0.300 (0.012) 0.225 (0.009) 0.650 (0.026) 1.175 (0.046) 1.525 (0.060) Recommended Minimum Pads Dimensions in mm/(Inches) APPLICATION NOTE Note: This is Flipped Mirror Image Pin #1 Location is Top Left Corner Return to Index www.vishay.com 10 Document Number: 69949 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000