Protection Devices TVS (Transient Voltage Suppressor) ESD102-U1-02ELS Uni-directional, 3.3 V, 0.4 pF, 0201, RoHS ESD102-U1-02ELS Data Sheet Revision 1.2, 2015-12-14 Final Power Management & Multimarket Edition 2015-12-14 Published by Infineon Technologies AG 81726 Munich, Germany © 2015 Infineon Technologies AG All Rights Reserved. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com) Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. ESD102-U1-02ELS Product Overview 1 Product Overview 1.1 Features • • • • • • • ESD / transient protection of high speed data lines according to: – IEC61000-4-2 (ESD): ±20 kV (air / contact) – IEC61000-4-4 (EFT): ±2.5 kV / 50 A (5/50 ns) – IEC61000-4-5 (surge): ±3 A (8/20 μs) Uni-directional working voltage: VRWM = 3.3 V Ultra low capacitance: CL = 0.4 pF (typical) Very low clamping voltage: VCL = 8 V (typical) at IPP = 16 A Low reverse current: IR = 1 nA (typical) Very low dynamic resistance: RDYN = 0.19 Ω (typical) Pb-free (RoHS compliant) and halogen free package, very small form factor 0.62 x 0.32 x 0.31 mm3 1.2 • • Application Examples USB 3.0, 10/100/1000 Ethernet, Firewire, DVI, HDMI, S-ATA, DisplayPort Mobile HDMI Link, MDDI, MIPI, SWP / NFC 1.3 Product Description Pin 1 Pin 1 marking (lasered) Pin 1 Pin 2 Pin 2 a) Pin configuration b) Schematic diagram PG-TS(S)LP-2_Single_Diode_PinConf_and_SchematicDiag.vsd Figure 1 Pin Configuration and Schematic Diagram Table 1 Part Information Type Package Configuration Marking code ESD102-U1-02ELS TSSLP-2-3 1 line, uni-directional F Final Data Sheet 3 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Maximum Ratings 2 Maximum Ratings Table 2 Maximum Rating at TA = 25 °C, unless otherwise specified Parameter Symbol 1) Values Unit ESD air discharge ESD contact discharge1) VESD ±20 ±20 kV Peak pulse current2) IPP ±3 A Operating temperature TOP -55 to 125 °C Storage temperature Tstg -65 to 150 °C 1) VESD according to IEC61000-4-2 2) Stress pulse: 8/20μs current waveform according to IEC61000-4-5 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 3 Electrical Characteristics at TA = 25 °C, unless otherwise specified " Figure 2 " () % )+ * " ")# %# %# !" !"! !#$%!& ' Definitions of Electrical Characteristics Final Data Sheet 4 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Electrical Characteristics at TA = 25 °C, unless otherwise specified Table 3 DC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Reverse working voltage VRWM Values Min. Typ. Max. – – 3.3 Trigger voltage Vt1 – 6.2 – Holding voltage Vh 3.35 4 4.4 Reverse current IR – 1 50 Unit Note / Test Condition V Pin 1 to Pin 2 Pin 1 to Pin 2, IR = 10 mA nA VR = 3.3 V, from Pin 1 to Pin 2 Table 4 AC Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol CL Line capacitance LS Series inductance Table 5 Values Unit Note / Test Condition Min. Typ. Max. – 0.4 0.65 pF VR = 0 V, f = 1 MHz – 0.4 0.65 pF VR = 0 V, f = 1 GHz – 0.2 – nH ESD and Surge Characteristics at TA = 25 °C, unless otherwise specified Parameter Symbol Clamping voltage1) VCL Values Min. Typ. Max. – 8 – Unit Note / Test Condition V ITLP = 16 A, tp = 100 ns, from Pin 1 to Pin 2 VFC Forward clamping voltage1) – 11 – ITLP = 30A, tp = 100 ns from Pin 1 to Pin 2 – 6 – ITLP = 16 A, tp = 100 ns, from Pin 2 to Pin 1 – 9 ITLP = 30 A, tp = 100 ns, – from Pin 2 to Pin 1 Dynamic resistance 1) RDYN – 0.19 – Ω tp = 100 ns from Pin 1 to Pin 2 – 0.23 – Ω tp = 100 ns from Pin 2 to Pin 1 1) Please refer to Application Note AN210[1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 0.6 ns. Final Data Sheet 5 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Typical Characteristics at TA=25°C, unless otherwise specified 4 Typical Characteristics at TA=25°C, unless otherwise specified -7 10 10-8 -9 IR [A] 10 Figure 3 10 -10 10 -11 10 -12 0 1 2 VR [V] 3 4 Reverse leakage current, IR = (VR) -6 10 IR [A] 10-7 -8 10 -9 10 25 50 75 100 125 150 TA [°C] Figure 4 Reverse current IR = f(TA), VR = 3.3 V Final Data Sheet 6 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Typical Characteristics at TA=25°C, unless otherwise specified 0 10 10-1 -2 10 10-3 -4 IF [A] 10 -5 10 10-6 -7 10 -8 10 -9 10 Figure 5 0 0.1 0.2 0.3 0.4 0.5 VF [V] 0.6 0.7 0.8 0.9 1 Forward current, IF = (VF) 0.8 CL [pF] 0.6 0.4 0.2 0 0.5 1 1.5 2 2.5 3 3.5 VR [V] Figure 6 Line capacitance CL = f(VR), f = 1MHz, from pin 1 to pin 2 Final Data Sheet 7 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Typical Characteristics at TA=25°C, unless otherwise specified 80 Scope: 6 GHz, 20 GS/s 60 VCL [V] VCL-max-peak = 81 [V] VCL-30ns-peak = 7 [V] 40 20 0 -20 -100 Figure 7 0 100 200 300 400 tp [ns] 500 600 700 800 900 Clamping voltage (ESD): VCL = f(t), 8 kV positive pulse from pin 1 to pin 2 20 Scope: 6 GHz, 20 GS/s 0 VCL [V] -20 VCL-max-peak = -72 [V] -40 VCL-30ns-peak = -3 [V] -60 -80 -100 Figure 8 0 100 200 300 400 tp [ns] 500 600 700 800 900 Clamping voltage (ESD): VCL = f(t), 8 kV negative pulse from pin 1 to pin 2 Final Data Sheet 8 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Typical Characteristics at TA=25°C, unless otherwise specified 100 Scope: 6 GHz, 20 GS/s VCL [V] 80 VCL-max-peak = 104 [V] VCL-30ns-peak = 9 [V] 60 40 20 0 -20 -100 Figure 9 0 100 200 300 400 tp [ns] 500 600 700 800 900 Clamping voltage (ESD): VCL = f(t), 15 kV positive pulse from pin 1 to pin 2 20 Scope: 6 GHz, 20 GS/s 0 VCL [V] -20 -40 VCL-max-peak = -98 [V] VCL-30ns-peak = -7 [V] -60 -80 -100 -100 Figure 10 0 100 200 300 400 tp [ns] 500 600 700 800 900 Clamping voltage (ESD): VCL = f(t), 15 kV negative pulse from pin 1 to pin 2 Final Data Sheet 9 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Typical Characteristics at TA=25°C, unless otherwise specified 50 ESD102-U1-02ELS RDYN 20 40 15 30 RDYN = 0.19 Ω ITLP [A] 10 5 0 0 -10 -5 -20 Equivalent VIEC [kV] 10 20 -10 RDYN = 0.23 Ω -30 -15 -40 -20 -50 -20 -10 0 10 20 VTLP [V] Figure 11 Clamping voltage (TLP): ITLP = f(VTLP) [1], pin 1 to pin 2 Final Data Sheet 10 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Typical Characteristics at TA=25°C, unless otherwise specified 0 Insertion Loss (|S21|) [dB] -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 10-2 Figure 12 ESD102-B1-02ELS 0.1 1 Frequency [GHz] 10 Insertion loss vs. frequency in a 50 Ω system Final Data Sheet 11 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Application Information 5 Application Information Application_ESD102-U1-02ELS.vsd Figure 13 Single line, uni-directional ESD / Transient protection[2] Final Data Sheet 12 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Package Information 6 Package Information 6.1 TSSLP-2-3 Top view Bottom view 0.31 +0.01 -0.02 0.32 ±0.05 0.355 0.62 ±0.05 2 Pin 1 marking 0.05 MAX. 0.26 ±0.035 0.2 ±0.035 1) 1 1) 1) Dimension applies to plated terminals TSSLP-2-3, -4-PO V01 TSSLP-2-3 Package outline (dimension in mm) 0.19 0.24 Solder mask 0.19 0.57 0.62 Copper 0.19 0.27 0.14 0.32 0.24 Figure 14 Stencil apertures TSSLP-2-1,-2-FP V02 Figure 15 TSSLP-2-3 Footprint (dimension in mm) 0.35 4 8 Ey Tape type Ex Ey Punched Tape 0.43 0.73 Embossed Tape 0.37 0.67 Pin 1 marking Figure 16 Deliveries can be both tape types (no selection possible). Specification allows identical processing (pick & place) by users. Ex TSSLP-2-3, -4-TP V03 TSSLP-2-3 Packing (dimension in mm) 1 Type code Pin 1 marking TSSLP-2-3, -4-MK V01 Figure 17 TSSLP-2-3 Marking example Table 1 “Part Information” on Page 3 Final Data Sheet 13 Revision 1.2, 2015-12-14 ESD102-U1-02ELS References References [1] On-chip ESD protection for integrated circuits, Albert Z. H. Wang, ISBN:0-7923-7647-1 [2] Infineon AG - Application Note AN210: Effective ESD Protection Design at System Level Using VF-TLP Characterization Methodology [3] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Package Final Data Sheet 14 Revision 1.2, 2015-12-14 ESD102-U1-02ELS Revision History: Revision 1.1, 2014-02-13 Page or Item Subjects (major changes since previous revision) Revision 1.2, 2015-12-14 All Layout change Trademarks of Infineon Technologies AG AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™, CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™, PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™, SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™, XPOSYS™. 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