5962F0721401V

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Make a correction to the maximum input clock frequency test, move the
1.5 GHz limit from the minimum column to the maximum column as specified
under Table IA. Make corrections to paragraphs 4.2.1a(1) and 4.4.2.1a. - ro
08-04-02
R. HEBER
B
Add VIN+ and VIN- limits to paragraph 1.3. Make changes to VIN+ and VINlimits as specified under paragraph 1.4. Make changes to VIL and VIH tests as
specified under Table IA. - ro
09-06-23
C. SAFFLE
REV
SHEET
REV
B
B
B
B
B
SHEET
15
16
17
18
19
REV STATUS
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Dan Wonnell
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Rajesh Pithadia
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
Robert M. Heber
DRAWING APPROVAL DATE
08-01-09
REVISION LEVEL
B
MICROCIRCUIT, DIGITAL-LINEAR,
A/D CONVERTER, DUAL 8-BIT 1.5 GSPS,
SINGLE 8-BIT 3.0 GSPS, MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-07214
1 OF 19
5962-E349-09
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
F
07214
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
Z
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
Generic number
Circuit function
ADC08D1520
Dual 8-bit, 1.5 GSPS A/D converter;
single 8-bit, 3.0 GSPS A/D converter
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Z
Descriptive designator
Terminals
See figure 1
128
Package style
Gullwing lead chip carrier
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage (VA, VDR) ................................................................................ 2.2 V
Supply difference (VDR – VA) .......................................................................... 0 V to 100 mV
Voltage on any input pin .................................................................................. -0.15 V to (VA + 0.15 V)
Voltage on VIN+, VIN- (maintaining common mode) ......................................
Ground difference (|GND – DR GND|) ............................................................
Input current at any pin ...................................................................................
Package input current .....................................................................................
Junction temperature (TJ) ...............................................................................
Storage temperature range ..............................................................................
Thermal resistance, junction-to-ambient (θJA) ................................................
-0.15 V to 2.5 V
0 V to 100 mV
25 mA
50 mA
+175C
-65C to +175C
11.5C/W
Thermal resistance, junction-to-case (θJC) ..................................................... 3.8C/W
Thermal pad resistance (θJ-PAD) .................................................................... 2.0C/W
1.4 Recommended operating conditions.
Ambient operating temperature range (TA) ..................................................... -55C to +125C
Supply voltage (VA) ......................................................................................... +1.8 V to +2.0 V
VA/2 tolerance for supply 1.9 V ....................................................................... 650 mV  VA / 2  1.2 V
Driver supply voltage (VDR) ............................................................................ +1.8 V to VA
Analog input common mode voltage ............................................................... VCMO 50 mV
VIN+, VIN- voltage range (maintaining common mode) :
100% duty cycle ...........................................................................................
10% duty cycle ............................................................................................
Ground difference (|GND – DR GND|) ............................................................
CLK pins voltage range ...................................................................................
Differential CLK amplitude ..............................................................................
0 V to 2.15 V
0 V to 2.5 V
0V
0 V to VA
0.4 Vp-p to 2.0 Vp-p
1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads(Si)/s) .................... 300 krads(Si)
2
Single event latch-up (SEL) ............................................................................  120 MeV-cm /mg 2/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Limits are based on characterization, but not production tested unless specified on the purchase order or contract.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
3
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full
ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
4
TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/, 2/
-55C  TA +125C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
STATIC CONVERTER CHARACTERISTICS
Integral Non-linearity
INL
DC coupled, 1 MHz sine
wave overanged
1, 2, 3
01
0.9
LSB
Differential Non-linearity
DNL
DC coupled, 1 MHz sine
wave overanged
1, 2, 3
01
0.6
LSB
Resolution with no missing
codes
RES
1, 2, 3
01
8
Bits
Offset error
VOFF
1, 2, 3
01
+1.5
LSB
Positive full-scale error
PFSE
3/
1, 2,3
01
25
mV
Negative full-scale error
NFSE
3/
1, 2,3
01
25
mV
1, 2, 3
01
530
650
mVp-p
840
960
-1.5
ANALOG INPUT AND REFERENCE CHARACTERISTICS
Full-scale analog differential
input range
VIN
Differential input resistance
RIN
FSR pin 14 low
FSR pin 14 high
1, 2, 3
01
94
106

IBG = 100 A
1, 2, 3
01
1.20
1.33
V
Sine wave clock
1, 2, 3
01
0.5
2.0
Vp-p
0.5
2.0
ANALOG OUTPUT CHARACTERISTICS
Bandgap reference output
voltage
VBG
CLOCK INPUT CHARACTERISTICS
Differential clock input level
VID
Square wave clock
DIGITAL CONTROL PIN CHARACTERISTICS
Logic high input voltage
VIH
OutV, DCLK_RST, PD,
PDQ CAL
1, 2, 3
0.67 x
VA
01
0.77 x
VA
OutEdge, FSR, DES/ SCS
Logic low input voltage
VIL
V
OutV, DCLK_RST, PD,
PDQ CAL
1, 2, 3
0.33 x
VA
01
V
0.23 x
VA
OutEdge, FSR
DES/ SCS
M,D,P,L,R
1
0.23 x
VA
DES/ SCS
F only
1
0.15 x
VA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
5
TABLE IA. Electrical performance characteristics - continued.
Test
Symbol
Conditions 1/, 2/
-55C  TA +125C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Unit
Min
Max
580
920
380
720
DIGITAL OUTPUT CHARACTERISTICS
LVDS differential output
voltage
VOD
Measured differentially, 4/
OutV = VA, VBG = floating
1, 2, 3
01
Measured differentially, 4/,
VBG = floating, OutV = GND
mVp-p
POWER SUPPLY CHARACTERISTICS
Analog supply current
Output driver supply current
Power consumption
IA
IDR
PD
1:2 demux
output
1:2 demux
output
1:2 demux
output
PD = PDQ =
low
1, 2, 3
01
875
PD = low,
PDQ = high
mA
615
PD = PDQ =
low
1, 2, 3
01
290
PD = low,
PDQ = high
mA
170
PD = PDQ =
low
1, 2, 3
01
2.2
PD = low,
PDQ = high
W
1.49
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
Effective number of bits
ENOB
Signal-to-noise plus
distortion ratio
SINAD
Signal-to-noise ratio
SNR
Total harmonic distortion
THD
Spurious-free dynamic
range
Out of range output code
SFDR
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
(VIN+) – (VIN-)  + fullscale
4, 5, 6
01
7
Bits
4, 5, 6
01
43.9
dB
4, 5, 6
01
43.9
dB
4, 5, 6
01
4, 5, 6
01
47.5
4, 5, 6
01
255
-47.5
(VIN+) – (VIN-)  - full-scale
dB
dB
0
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
6
TABLE IA. Electrical performance characteristics - continued.
Test
Symbol
Conditions 1/, 2/
-55C  TA +125C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
INTERLEAVE MODE (DES pin 127 = VA / 2) DYNAMIC CONVERTER CHARACTERISTICS.
Effective number of bits
ENOB
Signal-to-noise plus
distortion ratio
SINAD
Signal-to-noise ratio
SNR
Total harmonic distortion
THD
Spurious-free dynamic
range
SFDR
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
fIN = 373 MHz,
VIN = FSR – 0.5 dB
4, 5, 6
01
6.6
Bits
4, 5, 6
01
41.5
dB
4, 5, 6
01
41.5
dB
4, 5, 6
01
4, 5, 6
01
9, 10, 11
01
-45.2
dB
44.1
dB
AC TIMING CHARACTERISTICS
Maximum input clock
frequency
fCLK(MAX)
Normal mode (non DES) or
DES mode in 1:2 output
demux
1.5
Normal mode (non DES) or
DES mode in non-demux
outout
GHz
1.0
DCLK duty cycle
9, 10, 11
01
9, 10, 11
01
45
55
%
4
CLK 
cycles
(min)
Pulse width DCLK_RST
tPWR
CAL pin low time
tCAL-L
See figure 5
9, 10, 11
01
1280
CLK 
cycles
CAL pin high time
tCAL-H
See figure 5
9, 10, 11
01
1280
CLK 
cycles
1/
The following specifications apply after calibration for VA = VDR = +1.9 V dc; OutV = 1.9 V;
VIN FSR (a.c. coupled) = differential 870 mVp-p; CL = 10 pF; Differential, a.c. coupled sine wave input clock,
fCLK = 1.5 GHz at 0.5 Vp-p with 50% duty cycle; VBG = floating; Non-extended control mode; SDR mode;
2/
3/
4/
REXT = 3300  ±0.1%; Analog signal source impedance = 100  differential; 1:2 output demultiplex,
duty cycle stabilizer on.
RHA devices supplied to this drawing are tested at all levels M, D, P, L, R, F of irradiation. Pre and Post irradiation values
are identical as listed in table IA. When performing post irradiation electrical measurements for any RHA level,
TA = +25C.
Calculation of full-scale error for this device assumes that the actual reference voltage is exactly its nominal value.
Full-scale error for this device, therefore, is a combination of full-scale error and reference voltage error.
Tying VBG to the supply rail will increase the output offset voltage (VOS) by 300 mV (normal), as shown in the VOS
specification. Tying VBG to the supply rail will also affect the differential LVDS voltage (VOD), causing it to increase
by 30 mV (normally).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
7
FIGURE 1. Case outline Z.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
8
Dimensions
Inches
Symbol
Millimeters
Min
Max
Min
Max
A
0.054
0.066
1.371
1.676
A1
0.102
0.134
2.590
3.403
A2
0
0.006
0
0.152
b
0.006
0.009
0.152
0.228
c
0.005
0.007
0.127
0.177
D/E
1.38
1.42
35.052
36.068
D1/E1
0.760
0.780
19.304
19.812
D2/E2
0.602
0.608
15.290
15.443
e
0.020 BSC
0.508 BSC
L
0.29
0.34
7.366
8.636
L1
0.26
0.28
6.604
7.112
NOTES:
1. Controlling dimensions are inch, millimeter dimensions are given for reference only.
2. The bottom of package must be soldered to ground plane to ensure rated performance.
FIGURE 1. Case outline Z - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
9
Device type
01
Device type
01
Case outline
Z
Case outline
Z
Terminal
number
1
Terminal
symbol
GND
Terminal
number
33
Terminal
symbol
2
VA
OutV/SCLK
OutEdge/DDR/
SDATA
34
VA
Tdiode_P
35
Tdiode_N
36
DQd0+
3
4
37
DQd0-
6
7
VA
GND
GND
38
39
DQd1+
DQd1-
8
VA
40
VDR
9
5
GND
41
10
VINI-
42
ECE
DR GND
11
VINI+
GND
43
DQd2+
44
DQd2-
VA
FSR/ALT_ECE
/ DCLK_RSTDCLK_RST/
DCLKRST+
45
DQd3+
46
DQd3-
47
DQd4+
12
13
14
15
16
VA
48
DQd4-
17
VA
CLK+
49
DQd5+
18
50
DQd5-
19
CLK-
51
VA
GND
52
VDR
DRST_SEL
53
DR GND
22
VINQ+
54
DQd6+
23
VINQGND
55
DQd6-
56
DQd7+
VA
PD
GND
57
DQd7-
58
59
DQ0+
DQ0-
60
DQ1+
29
VA
PDQ
61
DQ1-
30
CAL
62
31
VBG
REXT
63
VDR
NC
64
DR GND
20
21
24
25
26
27
28
32
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
10
Device type
01
Device type
01
Case outline
Z
Case outline
Z
Terminal
number
65
66
Terminal
symbol
DQ2+
DQ2-
Terminal
number
97
98
Terminal
symbol
DR GND
NC
67
DQ3+
99
68
69
70
71
72
DQ3DQ4+
DQ4DQ5+
DQ5-
100
101
102
103
104
VDR
D11D11+
D10D10+
DId7-
73
105
DId7+
74
75
76
77
VDR
DR GND
DQ6+
DQ6DQ7+
106
107
108
109
DId6DId6+
DR GND
NC
78
DQ7-
110
79
80
81
82
83
84
85
86
87
OR+/DCLK2+
OR-/DCLK2DCLKDCLK+
D17D17+
D16D16+
DR GND
111
112
113
114
115
116
117
118
119
VDR
DId5DId5+
DId4DId4+
DId3DId3+
DId2DId2+
DR GND
88
120
NC
89
VDR
D15-
121
90
91
92
93
94
D15+
D14D14+
D13D13+
122
123
124
125
126
VDR
DId1DId1+
DId0DId0+
CalRun
95
D12-
127
DES/ SCS
96
D12+
128
VA
FIGURE 2. Terminal connections - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
11
FIGURE 3. Block diagram.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
12
FIGURE 4. Input/output transfer characteristic.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
13
SDR Clocking in 1:2 Demultiplexed Mode
DDR Clocking in 1:2 Demultiplexed Mode
FIGURE 5. Timing waveforms.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
14
Serial Interface Timing
Clock Reset Timing in DDR Mode
Clock Reset Timing in SDR Mode with OUTEDGE Low
FIGURE 5. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
15
Clock Reset Timing in SDR Mode with OUTEDGE High
Self Calibration and On-Command Calibration Timing
FIGURE 5. Timing waveforms - continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
16
TABLE IB. SEL test limits.
Device type
Single event
latch-up
Temperature (TC)
VCC
Effective linear energy
transfer (LET)
01
SEL
+85C
2.0 V
 120 MeV-cm /mg
2
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 57 (see MIL-PRF-38535, appendix A).
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table II herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
17
TABLE II. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
---
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class Q
1,2,3,4,5,6, 1/
9,10,11
1,2,3,4,5,6,9,10,11
1,2,3,4,5,6,9,10,11
1,2,3,4,5,6,9,10,11
1,4,9
Device
class V
1
1
1,2,3,4,5, 1/
6,9,10,11
1,2,3,4,5,6,
9,10,11
1,2,3,4,5,6,
9,10,11
1,2,3,4,5,6,
9,10,11
1,4,9
1,2,3,4,5, 1/
6,9,10,11
1,2,3,4,5,6,
9,10,11
1,2,3,4,5,6,
9,10,11
1,2,3,4,5,6,
9,10,11
1,4,9
1/ PDA applies to subgroup 1.
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table II herein.
b.
Subgroups 7 and 8 in table IA, method 5005 of MIL-STD-883 shall be omitted.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
18
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table II herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested.
All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at
TA = +25C 5C, after exposure, to the subgroups specified in table II herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019 condition B and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than
5 krads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the preirradiation end-point electrical parameter limit at +25C 5C.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614)
692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-07214
A
REVISION LEVEL
B
SHEET
19
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 09-06-23
Approved sources of supply for SMD 5962-07214 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-0721401VZC
3/
ADC08D1520WG-QV
5962F0721401VZC
27014
ADC08D1520WGFQV
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE
number
27014
Vendor name
and address
National Semiconductor
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-8090
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.