IRL630S, SiHL630S Datasheet

IRL630S, SiHL630S
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Logic-Level Gate Drive
• RDS(on) Specified at VGS = 4 V and 5 V
• 150 °C Operating Temperature
• Compliant to RoHS Directive 2002/95/EC
200
RDS(on) ()
VGS = 5 V
0.40
Qg (Max.) (nC)
40
Qgs (nC)
5.5
Qgd (nC)
24
Configuration
Single
D
DESCRIPTION
D2PAK (TO-263)
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
G
G D
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
D2PAK (TO-263)
SiHL630S-GE3
IRL630SPbF
SiHL630S-E3
D2PAK (TO-263)
SiHL630STRR-GE3a
IRL630STRRPbFa
SiHL630STR-E3a
D2PAK (TO-263)
SiHL630STRL-GE3a
IRL630STRLPbFa
SiHL630STL-E3a
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
VDS
VGS
200
± 10
9.0
5.7
36
0.59
0.025
250
9.0
7.4
74
3.1
5.0
- 55 to + 150
300d
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
VGS at 5 V
TC = 25 °C
TC = 100 °C
Currenta
Pulsed Drain
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
ID
IDM
EAS
IAR
EAR
TC = 25 °C
TA = 25 °C
PD
dV/dt
TJ, Tstg
for 10 s
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25V, starting TJ = 25 °C, L = 4.6 mH, Rg = 25 , IAS = 9.0 A (see fig. 12).
c. ISD  9.0 A, dI/dt  120 A/μs, VDD  VDS, TJ  150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 90390
S11-1044-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL630S, SiHL630S
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
62
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0, ID = 250 μA
200
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.27
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
1.0
-
2.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
IGSS
IDSS
RDS(on)
gfs
VGS = ± 10 V
-
-
± 100
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
250
VGS = 5.0 V
ID = 5.4 Ab
-
-
0.40
VGS = 4.0 V
Ab
-
-
0.50
4.8
-
-
-
1100
-
-
220
-
-
70
-
-
-
40
ID = 4.5
VDS = 50 V, ID = 5.4 Ab
μA

S
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
pF
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
-
5.5
Gate-Drain Charge
Qgd
-
-
24
Turn-On Delay Time
td(on)
-
8.0
-
tr
-
57
-
-
38
-
-
33
-
-
4.5
-
-
7.5
-
-
-
9.0
-
-
36
-
-
2.0
-
230
350
ns
-
1.7
2.6
μC
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
ID = 9.0 A, VDS = 160 V,
see fig. 6 and 13b
VDD = 100 V, ID = 9.0 A,
Rg = 6.0 , RD = 11 , see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
nC
ns
D
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 9.0 A, VGS = 0 Vb
TJ = 25 °C, IF = 9.0 A, dI/dt = 100 A/μsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.
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Document Number: 90390
S11-1044-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL630S, SiHL630S
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
100
VGS
7.50V
5.00V
4.00V
3.50V
3.00V
2.75V
2.50V
BOTTOM 2.25V
I D , Drain-to-Source Current (A)
I , Drain-to-Source Current (A)
D
TOP
10
1
2.25V
20μs PULSE WIDTH
Tc = 25°C
0.1
0.1
1
10
100
A
10
TJ = 150°C
1
TJ = 25°C
0.1
0.01
2.0
VDS , Drain-to-Source Voltage (V)
R DS(on) , Drain-to-Source On Resistance
(Normalized)
VGS
7.50V
5.00V
4.00V
3.50V
3.00V
2.75V
2.50V
BOTTOM 2.25V
I , Drain-to-Source Current (A)
D
10
2.25V
1
20μs PULSE WIDTH
TC = 150°C
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Document Number: 90390
S11-1044-Rev. C, 30-May-11
3.0
3.5
4.0
4.5
A
5.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.1
2.5
VGS , Gate-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
100
V DS = 50V
20μs PULSE WIDTH
A
2.5
ID = 9.0A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 5.0V
0
20
40
60
A
80 100 120 140 160
TJ , Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRL630S, SiHL630S
Vishay Siliconix
100
V GS = 0V,
f = 1MHz
C iss = C gs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
ISD , Reverse Drain Current (A)
C, Capacitance (pF)
2000
1500
Ciss
1000
C oss
500
10
TJ = 150°C
TJ = 25°C
1
Crss
A
0
1
10
VGS = 0V
0.1
0
100
V DS , Drain-to-Source Voltage (V)
1.2
A
1.6
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
I D = 9.0A
OPERATION IN THIS AREA LIMITED
BY R DS(on)
VDS = 160V
VDS = 100V
VDS = 40V
8
10μs
I D , Drain Current (A)
V GS , Gate-to-Source Voltage (V)
0.8
V SD , Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
10
0.4
6
4
10
100μs
1ms
1
10ms
100ms
2
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
20
30
40
A
Q G , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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T C = 25°C
T J = 150°C
Single Pulse
0.1
1
10
100
1000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 90390
S11-1044-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL630S, SiHL630S
Vishay Siliconix
RD
VDS
10
ID, Drain Current (Amps)
VGS
D.U.T.
Rg
8
+
- VDD
5V
6
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
4
VDS
2
90 %
0
25
50
75
100
A
125
150
TC , Case Temperature (°C)
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
PD M
0.05
t
0.02
0.01
t
N o te s :
1 . D u ty fa c to r D = t
SINGLE PULSE
(THERMAL RESPONSE)
0.01
0.00001
1
1
/ t
2
2 . P e a k TJ = P D M x Z th J C + T C
0.0001
0.001
0.01
0.1
2
1
A
10 A
t 1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 90390
S11-1044-Rev. C, 30-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL630S, SiHL630S
Vishay Siliconix
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
Rg
D.U.T.
+
-
I AS
V DD
VDS
5V
0.01 Ω
tp
IAS
EAS , Single Pulse Avalanche Energy (mJ)
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
600
ID
9.0A
5.7A
BOTTOM 4.0A
TOP
500
400
300
200
100
0
VDD = 50V
25
50
A
75
100
125
150
Starting TJ , Juntion Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
5V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 90390
S11-1044-Rev. C, 30-May-11
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRL630S, SiHL630S
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?90390.
Document Number: 90390
S11-1044-Rev. C, 30-May-11
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Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
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the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
1
Document Number: 91000