IRF830AS, IRF830AL, SiHF830AS, SiHF830AL Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Halogen-free According to IEC 61249-2-21 Definition • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness • Fully Characterized Capacitance and Avalanche Voltage and Current • Effective Coss specified • Compliant to RoHS Directive 2002/95/EC 500 RDS(on) (Max.) () VGS = 10 V 1.40 Qg (Max.) (nC) 24 Qgs (nC) 6.3 Qgd (nC) 11 Configuration Single D D2PAK (TO-263) I2PAK (TO-262) APPLICATIONS • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High speed power switching G G S D G D S TYPICAL SMPS TOPOLOGIES S • Two Transistor Forward • Half Bridge and Full Bridge N-Channel MOSFET ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262) Lead (Pb)-free and Halogen-free SiHF830AS-GE3 SiHF830ASTRL-GE3a SiHF830AL-GE3a IRF830ASPbF IRF830ASTRLPbFa IRF830ALPbF SiHF830AS-E3 SiHF830ASTL-E3a SiHF830AL-E3 Lead (Pb)-free Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage SYMBOL VDS VGS Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Currenta, e Pulsed Drain Linear Derating Factor Single Pulse Avalanche Energyb, e Avalanche Currenta Repetiitive Avalanche Energya Maximum Power Dissipation IDM EAS IAR EAR TA = 25 °C TC = 25 °C dV/dtc, e Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) ID PD dV/dt TJ, Tstg for 10 s LIMIT 500 ± 30 5.0 3.2 20 0.59 230 5.0 7.4 3.1 74 5.3 - 55 to + 150 300d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 18 mH, Rg = 25 , IAS = 5.0 A (see fig. 12). c. ISD 5.0 A, dI/dt 370 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. e. Uses SiHF830A data and test conditions. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91062 S11-1049-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF830AS, IRF830AL, SiHF830AS, SiHF830AL Vishay Siliconix THERMAL RESISTANCE RATINGS SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mounted, Steady-State)a PARAMETER RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0, ID = 250 μA 500 - - V VDS/TJ Reference to 25 °C, ID = 1 mAd - 0.60 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.5 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 3.0 Ab VGS = 10 V VDS = 50 V, ID = 3.0 Ad μA - - 1.4 2.8 - - S - 620 - - 93 - - 4.3 - - 886 - Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Output Capacitance Effective Output Capacitance Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5d VDS = 1.0 V, f = 1.0 MHz VGS = 0 V Coss eff. Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V VDS = 400 V, f = 1.0 MHz - 27 - VDS = 0 V to 400 Vc, d - 39 - - - 24 - - 6.3 ID = 5.0 A, VDS = 400 V, see fig. 6 and 13b, d pF nC Gate-Drain Charge Qgd - - 11 Turn-On Delay Time td(on) - 10 - - 21 - - 21 - - 15 - - - 5.0 - - 20 - - 1.5 - 430 650 ns - 2.0 3.0 μC Rise Time Turn-Off Delay Time Fall Time tr td(off) VDD = 250 V, ID = 5.0 A, Rg = 14 , RD = 49 , see fig. 10b, d tf ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 5.0 A, VGS = 0 Vb TJ = 25 °C, IF = 5.0 A, dI/dt = 100 A/μsb, d V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. d. Uses SiHF830A data and test conditions. www.vishay.com 2 Document Number: 91062 S11-1049-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF830AS, IRF830AL, SiHF830AS, SiHF830AL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 102 VGS Top 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 10 1 4.5 V 0.1 20 µs Pulse Width TJ = 25 °C 10-2 0.1 VDS, Drain-to-Source Voltage (V) 91062_01 10 TJ = 150 °C TJ = 25 °C 1 20 µs Pulse Width VDS = 50 V 0.1 102 10 1 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 102 4.0 ID, Drain-to-Source Current (A) 102 VGS 15 V 10 V 8.0 V 7.0 V 10 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top 4.5 V 20 µs Pulse Width TJ = 150 °C 0.1 1 91062_02 10 VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics Document Number: 91062 S11-1049-Rev. C, 30-May-11 6.0 7.0 8.0 Fig. 3 - Typical Transfer Characteristics RDS(on), Drain-to-Source On Resistance (Normalized) Fig. 1 - Typical Output Characteristics 1 5.0 VGS, Gate-to-Source Voltage (V) 91062_03 102 91062_04 2.5 ID = 5.0 A VGS = 10 V 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF830AS, IRF830AL, SiHF830AS, SiHF830AL Vishay Siliconix VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 103 Ciss 102 Coss 10 Crss 102 ISD, Reverse Drain Current (A) C, Capacitance (pF) 104 1 102 10 1 TJ = 25 °C 16 VDS = 250 V 8 For test circuit see figure 13 0 8 12 16 20 100 µs QG, Total Gate Charge (nC) 1 ms 1 0.1 91062_08 10 ms TC = 25 °C TJ = 150 °C Single Pulse 10 24 Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage www.vishay.com 4 1.2 10 µs 10 4 91062_06 1.0 Operation in this area limited by RDS(on) VDS = 100 V 4 0.8 VSD, Source-to-Drain Voltage (V) VDS = 400 V 0 0.6 102 ID = 5.0 A 12 VGS = 0 V 0.4 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 1 91062_07 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 20 TJ = 150 °C 0.1 0.2 103 VDS, Drain-to-Source Voltage (V) 91062_05 10 102 103 104 VDS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating Area Document Number: 91062 S11-1049-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF830AS, IRF830AL, SiHF830AS, SiHF830AL Vishay Siliconix RD VDS VGS 5.0 4.0 ID, Drain Current (A) D.U.T. Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 3.0 Fig. 10a - Switching Time Test Circuit 2.0 VDS 1.0 90 % 0.0 25 50 75 100 125 150 10 % VGS TC, Case Temperature (°C) 91062_09 td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.50 0.20 PDM 0.10 0.1 0.05 t1 t2 0.02 0.01 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 10-4 10-3 10-2 0.1 1 t1, Rectangular Pulse Duration (s) 91062_11 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp L VDS D.U.T. Rg IAS 20 V tp Driver + A - VDD IAS 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91062 S11-1049-Rev. C, 30-May-11 Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF830AS, IRF830AL, SiHF830AS, SiHF830AL 500 ID Top 2.2 A 3.2 A Bottom 5.0 A 400 300 200 100 0 790 VDSav, Avalanche Voltage (V) EAS, Single Pulse Avalanche Energy (mJ) Vishay Siliconix 785 780 775 770 25 50 75 100 125 150 Starting TJ, Junction Temperature (°C) 91062_12c Fig. 12c - Maximum Avalanche Energy vs. Drain Current 1.0 0.0 2.0 3.0 4.0 5.0 IAV, Avalanche Current (A) 91062_12d Fig. 12d - Basic Gate Charge Waveform Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Maximum Avalanche Energy vs. Drain Current www.vishay.com 6 Fig. 13b - Gate Charge Test Circuit Document Number: 91062 S11-1049-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF830AS, IRF830AL, SiHF830AS, SiHF830AL Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91062. Document Number: 91062 S11-1049-Rev. C, 30-May-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000