GWS2350S

DATASHEET
Dual 20V N-Channel Power MOSFET
GWS2350S
Features
Intersil’s low cost, state of the art MOSFET process technology
in bond-wireless packaging minimizes PCB space and rDS(ON),
plus it reduces overall system cost. The chip scale package of
the GWS2350S offers very small size and low profile, and is
fully compatible with standard SMT assembly processes.
• 3.0A, 4.5V rSS(ON) = 36mΩ maximum
• 3.0A, 4.0V rSS(ON) = 38mΩ maximum
• 3.0A, 3.1V rSS(ON) = 45mΩ maximum
• 3.0A, 2.5V rSS(ON) = 55mΩ maximum
• Low profile package: less than 0.8mm height when
mounted on PCB
• Excellent thermal characteristics
• Rated for high electrical overstress performance of 15A
short-circuit and overcurrent
• Integrated gate diodes provide Electro-Static Discharge
(ESD) protection of 2.5kV HBM
FET1
FET2
Gate1
Gate2
.
Source1
. .
.
.
.
. .
FIGURE 1. INTERNAL CONFIGURATION
December 18, 2015
FN8783.1
1
Source2
FIGURE 2. CHIP SCALE PACKAGE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
GWS2350S
Ordering Information
PART NUMBER
TEMP RANGE
(°C)
PART MARKING
GWS2350S
AB
Pin Configuration
GWS2350S
(4 BUMP WLCSP)
TOP VIEW
Submit Document Feedback
1
2
S1
S2
G1
G2
4
3
2
PACKAGE
(RoHS Compliant)
-55 to +150
4 BUMP WLCSP
Pin Descriptions
PIN #
PIN NAME
DESCRIPTION
1
S1
Source of FET1
2
S2
Source of FET2
3
G2
Gate of FET2
4
G1
Gate of FET1
FN8783.1
December 18, 2015
GWS2350S
Absolute Maximum Ratings
Thermal Information
(Note 1)
Source-to-Source Voltage (VSSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20V
Gate-to-Source Voltage (VGSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12V
Drain Current (Note 2)
Continuous, TC = +25°C (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6A
Continuous, TC = +100°C (ID). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3A
Pulsed (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60A
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5kV
Maximum Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Junction and Storage Temperature Range (TJ, Tstg) . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
1. TJ = +25°C unless otherwise noted.
2. When mounted on ceramic board of 50cm2 x1.0mm.
Electrical Characteristics
SYMBOL
TJ = +25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
TYP
(Note 4)
MAX
(Note 3)
UNIT
STATIC
IDSS
Zero Gate Voltage Drain Current
VGS = 0V, VDS = 20V
1
µA
IGSS
Gate Body Leakage
VDS = 0V VGS = ±8V
±10
µA
Gate Threshold Voltage
VDS = VGS, ID = 1mA
0.5
1.0
1.5
V
Source1-to-Source2
On-State Resistance
VGS = 4.5V, ISS = 3A
22
32
36
mΩ
VGS = 4.0V, ISS = 3A
23
33
38
mΩ
VGS = 3.1V, ISS = 3A
24
37
45
mΩ
VGS = 2.5V, ISS = 3A
30
45
55
mΩ
1.2
V
VGS(th)
rS1S2(ON)
VSD
Source-Drain Diode Voltage
VGS = 0, ID = 6A
1.0
Qg
Total Gate Charge
VDS = 16V, ID = 6.0A, VGS = 4.0V
3.5
nC
Ciss
Input Capacitance
VDS = 10V, VGS = 0V, f = 1MHz
400
pF
Coss
Output Capacitance
120
pF
Crss
Reverse Transfer Capacitance
100
pF
DYNAMIC
NOTES:
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
4. Typical values are for TA = +25°C.
Submit Document Feedback
3
FN8783.1
December 18, 2015
GWS2350S
Test Circuits
S2
S2
A
G2
G2
G1
G1
+V
A
±V
S1
S1
FIGURE 3. ISSS TEST CIRCUIT
FIGURE 4. IGSS TEST CIRCUIT
S2
S2
A
G2
G2
V
V
G1
G1
+V
±V
S1
S1
FIGURE 6. rSS(ON) TEST CIRCUIT
FIGURE 5. VGS(th) TEST CIRCUIT
S2
4.5V
G2
V
V
G1
S1
FIGURE 7. VFS-S TEST CIRCUIT
Submit Document Feedback
4
FN8783.1
December 18, 2015
GWS2350S
Typical Performance Curves
60
10
9
IS-SOURCE CURRENT (A)
IS-SOURCE CURRENT (A)
50
VGS = 4.5V
40
VGS = 4.0V
30
20
VGS = 3.1V
10
VGS = 2.5V
8
7
6
5
TJ = 125°C
4
-25°C
75°C
3
2
25°C
1
0
0
0
1
1
2
2
3
0
3
1
VSS - S OURCE-TO-SOURCE VOLTAGE (V)
90
VGS = 2.5V
70
VGS = 3 .1V
60
VGS = 4.0V
50
40
30
VGS = 4.5V
20
10
0
1
10
140
120
100
80
60
I S = 3A
40
20
0
0
100
VGS = 2.5V
VGS = 3.1V
VGS = 4.0V
50
40
30
VGS = 4.5V
20
10
-50
-25
0
25
50
75
100
125
TJ - JUNCTION TEMPERATURE (°C)
FIGURE 12. SOURCE-TO-SOURCE ON-STATE RESISTANCE vs
JUNCTION TEMPERATURE
Submit Document Feedback
5
10
15
150
FIGURE 11. SOURCE-TO-SOURCE ON-STATE RESISTANCE vs
GATE-TO-SOURCE VOLTAGE
VGS(th) - GATE THRESHOLD VOLTAGE (V)
rSS(ON) - ON-STATE RESISTANCE (m)
90
60
5
VGS - GATE-TO-SOURCE VOLTAGE (V )
FIGURE 10. SOURCE-TO-SOURCE ON-STATE RESISTANCE vs SOURCE
CURRENT
70
4
160
I S- SOURCE CURRENT (A)
80
3
FIGURE 9. TRANSFER CHARACTERISTICS
rSS(ON) - ON-STATE RESISTANCE (m)
rSS(ON) - ON-STATE RESISTANCE (m)
FIGURE 8. OUTPUT CHARACTERISTICS
80
2
VGS - GATE-TO-SOURCE (V)
1.2
1.0
I S = 1mA
0.8
0.6
0.4
0.2
-50
-25
0
25
50
75
100
125
150
TJ - JU NCTION TEMPERATURE (°C)
FIGURE 13. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FN8783.1
December 18, 2015
GWS2350S
100
4.0
3.5
VSS = 16V
I S = 6A
VGS = 0 TO 4.0V
3.0
IS-SOURCE CURRENT (A)
VGS - GATE-TO-SOURCE VOLTAGE
Typical Performance Curves (Continued)
2.5
2.0
1.5
1.0
0.5
TJ = +75°C
TJ = +25°C
TJ = -25°C
0.0
0
1
2
3
QG - TOTAL GATE CHARGE (nC)
1
4
0.0
0.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VSS-SOURCE-TO-SOU RCE VOLTAGE (V)
2.2
FIGURE 15. SOURCE-TO-SOURCE DIODE FORWARD VOLTAGE
FIGURE 14. GATE CHARGE
100 00
100
IS-SOURCE CURRENT (A)
C-CAPACITANCE (pF)
TJ = +125°C
10
Ciss
100 0
Coss
100
Crss
10
r SS(ON)
LIMITED
VGS = 4.5V
1ms
1
10ms
o
TA = +25 C,
SINGLE PULS E
0.1
100ms
DC
0.01
10
0
5
10
15
0.1
20
1
10
100
VSS - SOURCE-TO-SOURCE VOLTAGE (V)
VSS - SOURCE-TO-SOURCE VOLTAGE (V)
FIGURE 17. MAXIMUM RATED FORWARD BIASED SAFE OPERATING
AREA
FIGURE 16. CAPACITANCE
1.00
r(t) - TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
0.50
0.20
0.10
0.10
0.05
0.02
SING LE PULSE
0.01
1.0E-0 4 1.0E-0 3 1.0E-0 2 1.0E-0 1 1.0 E+00 1.0E+01 1.0E+02 1.0E+03
T - TIME (s)
FIGURE 18. TRANSIENT THERMAL RESPONSE, JUNCTION-TO-AMBIENT
Submit Document Feedback
6
FN8783.1
December 18, 2015
GWS2350S
Mechanical Considerations
This product is very small and thin. External stress may cause a
breakdown of the package and/or chip. Customers must insure
to handle this product with a distortion factor ε ≤2000µ. This is
represented on the Support Width Vs. Bend graph shown below
as the area above the lines. Each line shown represents a typical
printed circuit board thicknesses for which the product can be
mounted to.
Force
t
b
The distortion factor ε is defined by the following expression:
e
w
2
 = 6  t  b  w 
FIGURE 19.
Where:
t = board thickness (mm),
b = bend (mm),
w = support width (mm)
FIGURE 20. SUPPORT WIDTH vs BEND
Submit Document Feedback
7
FN8783.1
December 18, 2015
GWS2350S
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
December 18, 2015
FN8783.1
Added “Note 1. TJ = +25°C unless otherwise noted.” to Abs Max on page 3.
October 30, 2015
FN8783.0
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
8
FN8783.1
December 18, 2015
GWS2350S
Dimensional Outline and Pad Layout
0.29mm ± 0.02mm
SILICON
0.130mm ± 0.02mm
1.37mm ± 0.02mm
1.37mm ± 0.02mm
Bump Ø 0.365mm
0.65mm ±.05 mm
0.65mm ± 0.05 mm
Bumps are Lead Free solder
96.8 Sn / 2.6 Ag / 0.6 Cu
S1
S2
G1
G2
0.65mm
0.65mm
PCB LAND PATTERN
RECOMMENDATION
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
9
FN8783.1