SiHG20N50E Datasheet

SiHG20N50E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Low figure-of-merit (FOM) Ron x Qg
550
RDS(on) max. at 25 °C (Ω)
VGS = 10 V
Qg max. (nC)
•
•
•
•
•
0.184
92
Qgs (nC)
10
Qgd (nC)
19
Configuration
Single
APPLICATIONS
D
• Computing
- PC silver box / ATX power supplies
• Lighting
- Two stage LED lighting
• Consumer electronics
TO-247AC
G
• Applications using hard switched topologies
- Power factor correction (PFC)
- Two switch forward converter
- Flyback converter
• Switch mode power supplies (SMPS)
S
D
G
Low input capacitance (Ciss)
Reduced switching and conduction losses
Low gate charge (Qg)
Avalanche energy rated (UIS)
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247AC
Lead (Pb)-free and Halogen-free
SiHG20N50E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
UNIT
V
19
ID
A
12
IDM
42
1.4
W/°C
Single Pulse Avalanche Energy b
EAS
204
mJ
Maximum Power Dissipation
PD
179
W
TJ, Tstg
-55 to +150
°C
Linear Derating Factor
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
VDS = 0 V to 80 % VDS
Reverse Diode dV/dt d
Soldering Recommendations (Peak Temperature) c
70
dV/dt
V/ns
32
for 10 s
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 3.8 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
0.7
S15-0278-Rev. B, 23-Feb-15
MAX.
UNIT
°C/W
Document Number: 91635
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiHG20N50E
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Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.59
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
-
-
± 100
nA
μA
IGSS
IDSS
VGS = ± 30 V
-
-
±1
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
10
μA
-
0.160
0.184
Ω
gfs
VDS = 30 V, ID = 10 A
-
4.4
-
S
Input Capacitance
Ciss
1640
-
Coss
-
87
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
6
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
73
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
222
-
-
46
92
-
10
-
-
19
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = 10 V
ID = 10 A
Dynamic
pF
VDS = 0 V to 400 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
-
17
34
tr
-
27
54
-
48
96
-
25
50
-
0.83
-
-
-
19
-
-
42
-
-
1.2
-
293
-
ns
-
4.0
-
μC
-
26
-
A
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 10 A, VDS = 400 V
VDD = 400 V, ID = 10 A,
VGS = 10 V, Rg = 9.1 Ω
f = 1 MHz, open drain
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 10 A, VGS = 0 V
TJ = 25 °C, IF = IS = 10 A,
dI/dt = 100 A/μs, VR = 25 V
V
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
S15-0278-Rev. B, 23-Feb-15
Document Number: 91635
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50E
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
40
3.0
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
ID = 10 A
TJ = 25 °C
RDS(on), Drain-to-Source On-Resistance
(Normalized)
30
20
10
2.5
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
- 60 - 40 - 20
30
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
40
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
30
TJ = 150 °C
Ciss
1000
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
20
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
100
Crss
10
10
1
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
0
30
Fig. 2 - Typical Output Characteristics
100
200
300
400
VDS, Drain-to-Source Voltage (V)
500
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
9
50
7
6
30
Coss (pF)
ID, Drain-to-Source Current (A)
8
5000
TJ = 25 °C
40
TJ = 150 °C
20
5
Eoss
Coss
4
500
Eoss (μJ)
ID, Drain-to-Source Current (A)
50
3
2
10
1
VDS = 29.4 V
50
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S15-0278-Rev. B, 23-Feb-15
25
0
0
100
200
300
400
500
VDS
Fig. 6 - Coss and Eoss vs. VDS
Document Number: 91635
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50E
www.vishay.com
Vishay Siliconix
20
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
15
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
5
4
0
0
0
20
40
60
80
Qg, Total Gate Charge (nC)
100
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
25
75
100
125
TC, Case Temperature (°C)
150
650
VDS, Drain-to-Source Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
50
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD, Source-Drain Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this Area
Limited by RDS(on)
100
ID, Drain Current (A)
10
625
600
575
550
525
500
ID = 250 μA
475
- 60 - 40 - 20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
IDM Limited
10
100 μs
Limited by RDS(on)*
1
1 ms
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S15-0278-Rev. B, 23-Feb-15
Document Number: 91635
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50E
www.vishay.com
Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.05
0.1
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
L
Vary tp to obtain
required IAS
Current regulator
Same type as D.U.T.
VDS
50 kΩ
D.U.T
RG
+
-
IAS
12 V
0.2 µF
0.3 µF
V DD
+
D.U.T.
10 V
tp
0.01 Ω
-
VDS
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S15-0278-Rev. B, 23-Feb-15
Document Number: 91635
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHG20N50E
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91635.
S15-0278-Rev. B, 23-Feb-15
Document Number: 91635
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-247AC (High Voltage)
A
A
4
E
B
3 R/2
E/2
7 ØP
Ø k M DBM
A2
S
(Datum B)
ØP1
A
D2
Q
4
4
2xR
(2)
D1
D
1
2
4
D
3
Thermal pad
5 L1
C
L
A
See view B
2 x b2
3xb
0.10 M C A M
4
E1
0.01 M D B M
View A - A
C
2x e
A1
b4
Planting
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
D DE
(b1, b3, b5)
Base metal
E
C
(c)
C
c1
(b, b2, b4)
(4)
Section C - C, D - D, E - E
View B
MILLIMETERS
DIM.
MIN.
MAX.
A
4.58
5.31
A1
2.21
2.59
A2
1.17
2.49
b
0.99
1.40
b1
0.99
1.35
b2
1.53
2.39
b3
1.65
2.37
b4
2.42
3.43
b5
2.59
3.38
c
0.38
0.86
c1
0.38
0.76
D
19.71
20.82
D1
13.08
ECN: X13-0103-Rev. D, 01-Jul-13
DWG: 5971
INCHES
MIN.
MAX.
0.180
0.209
0.087
0.102
0.046
0.098
0.039
0.055
0.039
0.053
0.060
0.094
0.065
0.093
0.095
0.135
0.102
0.133
0.015
0.034
0.015
0.030
0.776
0.820
0.515
-
DIM.
D2
E
E1
e
Øk
L
L1
N
ØP
Ø P1
Q
R
S
MILLIMETERS
MIN.
MAX.
0.51
1.30
15.29
15.87
13.72
5.46 BSC
0.254
14.20
16.25
3.71
4.29
7.62 BSC
3.51
3.66
7.39
5.31
5.69
4.52
5.49
5.51 BSC
INCHES
MIN.
MAX.
0.020
0.051
0.602
0.625
0.540
0.215 BSC
0.010
0.559
0.640
0.146
0.169
0.300 BSC
0.138
0.144
0.291
0.209
0.224
0.178
0.216
0.217 BSC
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Contour of slot optional.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions D1 and E1.
5. Lead finish uncontrolled in L1.
6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154").
7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.
8. Xian and Mingxin actually photo.
Revision: 01-Jul-13
Document Number: 91360
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000