SiHG73N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Low figure-of-merit (FOM) Ron x Qg 650 RDS(on) max. at 25 °C (Ω) VGS = 10 V Qg max. (nC) • Low input capacitance (Ciss) 0.039 • Reduced switching and conduction losses 362 Qgs (nC) 48 • Ultra low gate charge (Qg) Qgd (nC) 98 • Avalanche energy rated (UIS) Configuration • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Single TO-247AC APPLICATIONS D S D Available • Switch mode power supplies (SMPS) • Power factor correction power supplies (PFC) • Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) G G S N-Channel MOSFET ORDERING INFORMATION Package TO-247AC Lead (Pb)-free SiHG73N60E-E3 Lead (Pb)-free and Halogen-free SiHG73N60E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID UNIT V 73 46 A IDM 236 4.2 W/°C Single Pulse Avalanche Energy b EAS 2030 mJ Maximum Power Dissipation PD 520 W TJ, Tstg -55 to +150 °C Linear Derating Factor Operating Junction and Storage Temperature Range Drain-Source Voltage Slope VDS = 0 V to 80 % VDS Reverse Diode dV/dt d Soldering Recommendations (Peak Temperature) c for 10 s dV/dt 60 8.4 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 12 A. c. 1.6 mm from case. d. ISD ≤ ID, dI/dt = 30 A/μs, starting TJ = 25 °C. S15-0399-Rev. E, 16-Mar-15 Document Number: 91482 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG73N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 0.24 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 250 μA - 0.65 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 10 Gate-Source Leakage IGSS Zero Gate Voltage Drain Current IDSS μA - 0.032 0.039 Ω gfs VDS = 40 V, ID = 10 A - 12 - S Input Capacitance Ciss 7700 - Coss - 320 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output Capacitance - 5 - Effective Output Capacitance, Energy Related a Co(er) - 259 - Effective Output Capacitance, Time Related b Co(tr) - 907 - - 241 362 - 48 - Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 10 V ID = 36 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V ID = 24 A, VDS = 480 V Gate-Drain Charge Qgd - 98 - Turn-On Delay Time td(on) - 63 95 - 105 158 - 290 435 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VDD = 480 V, ID = 24 A, VGS = 10 V, Rg = 10 Ω f = 1 MHz, open drain - 120 180 - 1.52 - - - 73 - - 200 nC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 36 A, VGS = 0 V TJ = 25 °C, IF = IS = 24 A, dI/dt = 100 A/μs, VR = 25 V - 0.9 1.2 V - 657 1314 ns - 14.6 29.2 μC - 34.7 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S15-0399-Rev. E, 16-Mar-15 Document Number: 91482 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG73N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) TOP 15 V 14 V 13 V 12 V 200 11 V 10 V 3 TJ = 25 °C ID = 36 A RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 250 9V 150 8V 100 7V 50 6V 2.5 2 1.5 VGS = 10 V 1 0.5 5V 0 - 60 - 40 - 20 0 10 90 20 25 30 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 120 15 100 000 TJ = 150 °C Ciss 10 000 7V 60 6V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 1000 Coss 100 Crss 30 10 5V 1 0 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 100 200 300 400 500 600 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 45 40 200 35 2000 30 150 Coss (pF) ID, Drain-to-Source Current (A) 250 100 TJ = 150 °C Coss 25 Eoss 20 200 Eoss (μJ) ID, Drain-to-Source Current (A) 150 5 Capacitance (pF) 0 15 TJ = 25 °C 10 50 5 0 0 5 10 15 20 25 20 0 VGS, Gate-to-Source Voltage (V) 300 VDS Fig. 3 - Typical Transfer Characteristics Fig. 6 - Coss and Eoss vs. VDS S15-0399-Rev. E, 16-Mar-15 0 100 200 400 500 600 Document Number: 91482 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG73N60E www.vishay.com Vishay Siliconix 80 VDS = 480 V VDS = 300 V VDS = 120 V 20 70 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 60 50 40 30 20 4 10 0 0 0 60 120 180 240 300 360 420 480 25 Qg, Total Gate Charge (nC) 50 75 100 125 150 TJ, Case Temperature (°C) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature 750 1000 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 725 100 TJ = 150 °C 10 TJ = 25 °C 1 700 675 650 625 600 575 VGS = 0 V 550 0.1 - 60 - 40 - 20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VSD, Source-Drain Voltage (V) Fig. 8 - Typical Source-Drain Diode Forward Voltage 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Temperature vs. Drain-to-Source Voltage 1000 Limited by RDS(on)* IDM Limited ID, Drain Current (A) 100 10 Operation in this Area Limited by RDS(on) 100 μs 1 ms 1 10 ms 0.1 TC = 25 °C TJ = 150 °C Single Pulse 0.01 BVDSS Limited 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S15-0399-Rev. E, 16-Mar-15 Document Number: 91482 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG73N60E www.vishay.com Vishay Siliconix Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS VDD D.U.T. RG + - VDD VDS 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS QG 10 V 90 % QGS 10 % VGS QGD VG td(on) td(off) tf tr Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L Vary tp to obtain required IAS VDS 50 kΩ D.U.T RG 12 V + - IAS 0.2 µF 0.3 µF V DD + D.U.T. - VDS 10 V tp 0.01 Ω VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S15-0399-Rev. E, 16-Mar-15 Document Number: 91482 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG73N60E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91482. S15-0399-Rev. E, 16-Mar-15 Document Number: 91482 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L A See view B 2 x b2 3xb 0.10 M C A M 4 E1 0.01 M D B M View A - A C 2x e A1 b4 Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE (b1, b3, b5) Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 A1 2.21 2.59 A2 1.17 2.49 b 0.99 1.40 b1 0.99 1.35 b2 1.53 2.39 b3 1.65 2.37 b4 2.42 3.43 b5 2.59 3.38 c 0.38 0.86 c1 0.38 0.76 D 19.71 20.82 D1 13.08 ECN: X13-0103-Rev. D, 01-Jul-13 DWG: 5971 INCHES MIN. MAX. 0.180 0.209 0.087 0.102 0.046 0.098 0.039 0.055 0.039 0.053 0.060 0.094 0.065 0.093 0.095 0.135 0.102 0.133 0.015 0.034 0.015 0.030 0.776 0.820 0.515 - DIM. D2 E E1 e Øk L L1 N ØP Ø P1 Q R S MILLIMETERS MIN. MAX. 0.51 1.30 15.29 15.87 13.72 5.46 BSC 0.254 14.20 16.25 3.71 4.29 7.62 BSC 3.51 3.66 7.39 5.31 5.69 4.52 5.49 5.51 BSC INCHES MIN. MAX. 0.020 0.051 0.602 0.625 0.540 0.215 BSC 0.010 0.559 0.640 0.146 0.169 0.300 BSC 0.138 0.144 0.291 0.209 0.224 0.178 0.216 0.217 BSC Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions D1 and E1. 5. Lead finish uncontrolled in L1. 6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. Outline conforms to JEDEC outline TO-247 with exception of dimension c. 8. Xian and Mingxin actually photo. Revision: 01-Jul-13 Document Number: 91360 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000