Critical Conduction Mode PFC Control IC SSC2005SC General Description Package SSC2005SC is a Critical Conduction Mode (CRM) control IC for power factor correction (PFC). Since no input voltage sensing and no auxiliary winding for inductor current detection are required, the IC allows the realization of low standby power and the low number of external components. The product achieves high cost-performance and high efficiency PFC converter system. SOIC8 Inductor Current Detection (No auxiliary winding required) Low Standby Power (No input voltage sensing required) Minimum Off-time Limitation Function to restrict the Rise of Operation Frequency High Accuracy Overcurrent detection: −0.60 V ± 5 % Protections Overcurrent Protection (OCP): Pulse-by-pulse Overvoltage Protection (OVP): Auto restart FB Pin Undervoltage Protection (FB_UVP): Auto restart Thermal Shutdown Protection with hysteresis (TSD): Auto restart Typical Application Circuit DBYP L1 1 8 VCC COMP 2 7 OUT RT 3 6 GND RDLY 4 5 CS Not to scale Features and Benefits BR1 FB Electrical Characteristics VCC Pin Absolute Maximum Ratings, VCC = 28 V OUT Pin Source Current, IOUT(SRC) = −500 mA OUT Pin Sink Current, IOUT(SNK) = 1000 mA Applications PFC circuit up to 200 W of output power such as: AC/DC power supply Digital appliances (large size LCD television and so forth). OA equipment (Computer, Server, Monitor, and so forth). Communication facilities D1 VOUT VAC D2 R2 C1 C2 Q1 R1 R3 RCS C5 Cｆ RDLY GND RT OUT COMP VCC FB 5 6 External power supply CS NC U1 R4 DZCS LINE GND 7 4 RDLY 3 C4 2 C3 RVS1 8 RRT RS 1 RVS2 SSC2005SC C6 CP CS TC_SSC2005SC_1_R2 SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. http://www.sanken-ele.co.jp/en/ 1 SSC2005SC CONTENTS General Description ------------------------------------------------------------------------ 1 1. Absolute Maximum Ratings --------------------------------------------------------- 3 2. Electrical Characteristics ------------------------------------------------------------ 3 3. Functional Block Diagram ----------------------------------------------------------- 5 4. Pin Configuration Definitions ------------------------------------------------------- 5 5. Typical Application Circuit --------------------------------------------------------- 6 6. Package Outline ------------------------------------------------------------------------ 7 7. Marking Diagram --------------------------------------------------------------------- 7 8. Operational Description -------------------------------------------------------------- 8 8.1 Critical Conduction Mode: CRM ----------------------------------------- 8 8.2 Startup Operation ------------------------------------------------------------ 9 8.3 Restart Circuit ---------------------------------------------------------------- 9 8.4 Maximum On-time Setting ------------------------------------------------- 9 8.5 Zero Current Detection and Bottom-on Timing (Delay Time) Setting ------------------------ 10 8.6 Minimum Off-time Limit Function -------------------------------------- 11 8.7 Overvoltage Protection (OVP) -------------------------------------------- 11 8.8 FB pin Under Voltage Protection (FB_UVP) -------------------------- 11 8.9 Overcurrent Protection (OCP) ------------------------------------------- 12 9. Design Notes --------------------------------------------------------------------------- 12 9.1 Inductor Setup --------------------------------------------------------------- 12 9.2 External Components------------------------------------------------------- 13 9.3 PCB Trace Layout and Component Placement ----------------------- 15 10. Reference Design of Power Supply ----------------------------------------------- 17 OPERATING PRECAUTIONS -------------------------------------------------------- 18 IMPORTANT NOTES ------------------------------------------------------------------- 19 SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 2 SSC2005SC 1. Absolute Maximum Ratings For additional details, refer to the datasheet. The polarity value for current specifies a sink as “+”, and a source as “−”, referencing the IC. Unless specifically noted TA = 25 °C Parameter Pins Rating Unit VCC 8–6 28 V OUT Pin Source Current IOUT(SRC) 7–6 − 500 mA OUT Pin Sink Current IOUT(SNK) 7–6 1000 mA VFB 1–6 − 0.3 to 5 V ICOMP 2–6 − 200 to 200 µA IRT 3–6 − 500 to 0 µA IRDLY 4–6 − 500 to 0 µA CS Pin Voltage VCS 5–6 − 5 to 0.3 V Allowable Power Dissipation PD − 0.5 W Operating Ambient Temperature TOP − − 40 to 110 °C Storage Temperature Tstg − − 40 to 150 °C Junction Temperature Tj − 150 °C VCC Pin Voltage FB Pin Voltage COMP Pin Current RT Pin Current RDLY Pin Current 2. Symbol Conditions Notes Electrical Characteristics For additional details, refer to the datasheet. The polarity value for current specifies a sink as “+”, and a source as “−”, referencing the IC. Unless specifically noted, TA = 25 °C, VCC = 14 V, VCS = 0.1 V Parameter Symbol Conditions Pins Min. Typ. Max. Unit Power Supply Operation Operation Start Voltage VCC(ON) 8–6 10.5 12.0 13.5 V Operation Stop Voltage VCC(OFF) 8–6 8.2 9.5 11.0 V Operation Voltage Hysteresis VCC(HYS) 8–6 1.4 2.5 3.1 V Circuit Current in Operation ICC(ON) 8–6 2.0 3.1 4.4 mA Circuit Current in Non-Operation ICC(OFF) VCC = 9.5 V 8–6 40 80 160 µA Maximum On-Time tON(MAX) V FB = 1.5 V RRT = 22 kΩ 7–6 15 23 33 µs Minimum Off-Time tOFF(MIN) RDRY = 22 kΩ 7–6 1.35 1.95 2.80 µs RDLY Pin Voltage VRDLY 4–6 1.3 1.5 1.7 V RT Pin Voltage VRT 3–6 1.3 1.5 1.7 V Feedback Control Voltage VFB 1–6 2.46 2.50 2.54 V Feedback Line Regulation VFB(LR) 1–6 −8 1 12 mV IFB 1–6 1–6 2–6 − 3.2 − 2.0 − 1.0 µA 60 103 150 µS Oscillation Operation FB Pin Bias Current Error Amplifier Transconductance Gain SSC2005SC-DS Rev.1.1 Feb. 06, 2015 gm SANKEN ELECTRIC CO.,LTD. 3 SSC2005SC Parameter Symbol Conditions Pins Min. Typ. Max. Unit COMP Pin Sink Current ICOMP(SNK) 2–6 18 40 72 µA COMP Pin Source Current ICOMP(SRC) 2–6 − 72 − 40 − 18 µA Zero Duty COMP Voltage VCOMP(ZD) 2–6 0.50 0.65 0.90 V tRS − 30 50 80 µs Restart Time Drive Output Output Voltage (High) VOH IOUT = –100 mA 7–6 10.0 12.0 13.5 V Output Voltage (low) VOL IOUT = 200 mA 7–6 0.40 0.75 1.25 V tr COUT = 1000 pF 7–6 − 60 120 ns tf COUT = 1000 pF 7–6 − 20 70 ns 5–6 − 20 − 10 0 mV 5–6 0.55 0.95 1.17 µs 5–6 − 0.63 − 0.60 − 0.57 V 5–6 100 250 400 ns 5–6 − 110 − 75 − 40 µA 1–6 1–6 1.075 ×VFB 55 1.090 ×VFB 90 1.105 ×VFB 125 mV 1–6 200 300 400 mV 1–6 80 120 160 mV Tj(TSD) – 135 150 – °C Tj(TSDHYS) – – 10 – °C θj-A – – – 180 °C/W Output Rise Time(1) Output Fall Time (1) Zero Current Detection and Overcurrent Protection Zero Current Detection Threshold VCS(ZCD) Voltage Zero Current Detection Delay tDLY(ZCD) RDLY = 22 kΩ Time(2) Overcurrent Protection Threshold VCS(OCP) Voltage Overcurrent Protection Delay tDLY(OCP) Time(2) CS Pin Source Current ICS FB Pin Protection Overvoltage Protection Threshold VOVP Voltage Overvoltage Protection Hysteresis VOVP(HYS) Undervoltage Protection VUVP Threshold Voltage Undervoltage Protection VUVP(HYS) Hysteresis V Thermal Shutdown Thermal Shutdown Threshold(2) Thermal Shutdown Hysteresis (2) Thermal Resistance Junction to Ambient Resistance(2) (1) (2) Shown in Figure 3-1 Design assurance item 90% VOUT 10% tr tf Figure 3-1 Switching time SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 4 SSC2005SC 3. Functional Block Diagram ＋ OVP REG － 8 VCC 7 OUT 6 GND 5 CS UVLO ＋ 1.090V×VFB － 12.0V /9.5V UVP － ＋ － 300mV /420mV R ＋ Q S Error AMP － 1 OCP － FB ＋ ＋ -0.60V VFB=2.50V OSC ZCD COMP 2 ＋ － -10mV 4. 3 4 RT RDLY Pin Configuration Definitions Number Name 1 FB Function Feedback signal input, overvoltage protection signal input and FB pin undervoltage protection signal input Phase compensation FB 1 8 VCC COMP 2 7 OUT RT 3 6 GND 2 COMP RDLY 4 5 CS 3 RT 4 RDLY 5 CS 6 GND Turn-on delay time adjustment Overcurrent protection signal input and zero current detection signal input Ground 7 OUT Gate drive output 8 VCC Power supply input for control circuit SSC2005SC-DS Rev.1.1 Feb. 06, 2015 Maximum on-time adjustment SANKEN ELECTRIC CO.,LTD. 5 SSC2005SC 5. Typical Application Circuit DBYP BR1 L1 D1 VAC D2 VOUT R2 Q1 C2 C1 R1 R3 LINE GND RCS R4 C5 DZCS External Power supply RDLY GND RT OUT COMP VCC FB 5 6 Cｆ CS NC U1 7 8 4 RDLY 3 C4 2 C3 RVS1 SSC2005SC CP 1 C6 RVS2 RS RRT CS TC_SSC2005SC_2_R2 SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 6 SSC2005SC 6. Package Outline SOIC8 1.6 (0.063) 3.8 (0.15) 1.27 (0.0500) NOTES: 1) All liner dimensions are in millimeters 2) Pb-free. Device composition compliant with the RoHS directive. 7. 0.61 (0.024) Land Pattern Example (not to scale) Marking Diagram 8 SC2005 SKYMDC 1 Part Number Lot Number Y is the last digit of the year (0 to 9) M is the month (1 to 9,O,N or D) D is a period of days 1 : 1st to 10th 2 : 11th to 20th 3 : 21st to 31st Sanken Control Number SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 7 SSC2005SC 8. Operational Description All of the parameter values used in these descriptions are typical values, unless they are specified as minimum or maximum. With regard to current direction, "+" indicates sink current (toward the IC) and "–" indicates source current (from the IC). 8.1 Critical Conduction Mode: CRM Figure 8-1 and Figure 8-2 show the PFC circuit and CRM operation waveform. The IC performs the on/off operation of switching device Q1 in critical mode (the inductor current is zero) as shown in Figure 8-1. Thus, the low drain current variation di/dt of power MOSFET is accomplished. Also, adjusting the turn-on timing at the bottom point of VDS free oscillation waveform (quasi-resonant operation), low noise and high efficiency PFC circuit is realized. voltage RVS2 is compared with the reference voltage VFB = 2.50 V by using error amplifier (Error AMP) connected to FB pin. The output of the Error AMP is averaged and phase compensated. This signal VCOMP is compared with the ramp signal VOSC to achieve on-time control. The ON time becomes almost constant in commercial cycle by setting VCOMP respond to below 20 Hz (Figure 8-4). This is achieved by tuning the capacitor connected to the COMP pin. The off-time and the bottom on timing of VDS are set by both zero current detection of drain current and the delay time configured by RDLY pin resistance. Thus, simple PFC circuit with inductor having no auxiliary winding is realized. L1 D1 U1 Q1 PWM COMP VCOMP 7 OUT VSET FB 1 VFB = 2.5V VOSC ZCD COMP VCS(ZCD)= -10mV D1 RVS1 Error AMP Q R S L1 VOUT RVS2 C6 OSC Q1 C1 VAC IOFF S CS 5 C2 D COMP 2 GND 6 RDLY 4 ION RS RCS C5 RCS DZCS RRT C3 RDLY C4 CS CP R4 Figure 8-3 CRM control circuit Figure 8-1 PFC circuit IL=ION+IOFF RT 3 √2×VACRMS ILPEAK 1 I L ( AVG ) ILPEAK 2 VAC(t) ILPEAK IL(t) √2×IACRMS IAC(t) ION IOFF tON tOFF Bottom on Free oscillation VCOMP VOSC Q1 VDS OFF ON OFF ON Turn on delay time Figure 8-2 CRM operation and bottom on operation Figure 8-3 shows the internal CRM control circuit. The power MOSFET Q1 starts switching operation by self-oscillation. The control of on-time is as follows: the detection SSC2005SC-DS Rev.1.1 Feb. 06, 2015 VSET OUT pin voltage VAC(t) ILPEAK(t) IL(AVG.)(t) Figure 8-4 CRM operation waveforms SANKEN ELECTRIC CO.,LTD. 8 SSC2005SC The off duty DOFF of boost converter in CRM mode have the relation of DOFF(t) = VAC(t)/VOUT and is proportional to input voltage, where V AC(t) is the input voltage of AC line as a function of time. As a result of aforementioned control shown in Figure 8-4, the peak current, ILPEAK, of the inductance current, IL, becomes sinusoidal. Since the averaged input current become similar to AC input voltage waveform by a low pass filter at input stage, high power factor is achieved. 8.2 Startup Operation Figure 8-5 shows the VCC pin peripheral circuit. The VCC pin is a control circuit power supply input. The voltage is supplied by using external power supply. As shown in Figure 8-6, when VCC pin voltage rises to the Operation Start Voltage VCC(ON) = 12.0 V, the control circuit starts operation. When the VCC pin voltage decreases to VCC(OFF) = 9.5 V, the control circuit stops operation by Undervoltage Lockout (UVLO) circuit, and reverts to the state before startup. Since COMP pin voltage rises from zero during startup period, the VCOMP signal shown in Figure 8-3 gradually rises from low voltage. The on-width gradually increased to restrict the rise of output power by the Softstart Function. Thus, the stress of the peripheral component is reduced. 8 External Power Supply 3 Cf U1 VCC 8.3 Restart Circuit The IC is self-oscillation type. The off-time of OUT pin is set by the zero current detection circuit (refer to Section 8.5). When the off-time of OUT pin is maintained for tRS = 50 μs or more, the restart circuit is activated and OUT pin turns on. At intermittent oscillation period in startup and light load, the restart circuit is activated and the switching operation is stabilized. Since tRS = 50 μs corresponds to the operational frequency of 20 kHz, the minimum frequency should be set to higher than 20 kHz (above audible frequency) at the inductance value design. 8.4 Maximum On-time Setting In order to reduce audible noise of transformer at transient state, the IC has the Maximum on-time, tON(MAX). This tON(MAX) is adjusted by the resistance RRT which is connected to the RT pin. Figure 8-7 shows the relation between RRT value and tON(MAX) in IC design. . The RRT value is set by using the result of tON(MAX)_OP and Figure 8-7, where tON(MAX)_OP is the maximum on-time of the peak voltage of the minimum AC input voltage ● tON(SET)MAX Setting ILP is calculated by Equation (1). ILP is peak current of the peak voltage of the minimum AC input voltage. COMP RS CP GND 6 CS Figure 8-5 VCC pin peripheral circuit ICC ILP 2 2 POUT VACRMS ( MIN ) (A) (1) where, POUT : Output power (W) VACRMS(MIN) : Minimum AC input voltage rms value (V) η : Efficiency of PFC (About 0.90 to 0.97) VCC（OFF） tON(MAX)_OP is calculated by Equation (2) with results of Equation (1) and Equation (5). tON(MAX)_OP is the maximum on time of the peak voltage of the minimum AC input voltage. Startup Stop ICC（ON） VCC（ON） Figure 8-6 Relationship between VCC pin voltage and ICC VCC pin voltage t ON ( MAX ) _ OP L P I LP 2 VACRMS ( MIN ) (s) (2) where, LP : Inductance value of the result of Equation (5) VACRMS(MIN) : Minimum AC input voltage rms value (V) ● RRT Setting SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 9 SSC2005SC The value of RRT should set larger than RRT(SET). RRT(SET) is given by tON(MAX)_OP in Figure 8-7. The range of RRT is 15 kΩ to 47 kΩ. When tON(MAX)_OP is 16.3 μs or less, RRT is set 15 kΩ. If tON(MAX)_OP is 45 μs or more, RRT is over 47 kΩ. Thus, the setting value of fSW(SET) in Equation (5) is increased and the value of LP should be calculated again. If the setting value of RRT is too large for RRT(SET), it is necessary to be careful about the audible noise of transformer in the transient operation including startup. 45 tON(MAX) (μs) 40 35 25 t ONDLY ≒ L P C V (s) (3) where, LP : Inductance value of the result of Equation (5). CV : Sum of the following capacitance: the output capacitance of power MOSFET, the parasitic capacitance of inductor, and the junction capacitance of boost diode. 50 30 point of VDS free oscillation waveform on actual operation in the application. Adjusting the output timing of the on signal to the bottom point of VDS free oscillation waveform (quasi-resonant operation), low noise, low switching loss and high efficiency PFC circuit is realized. The range of RDLY is 15 kΩ to 56 kΩ. The ideal delay time shown in figure 8-11 is given by Equation (3), and it depends on LP and CV. tON(MAX)_OP IL D1 20 VOUT L1 15 ex. Range of RRT Setting 10 Q1 7 ID 5 15 20 ZCD COMP VCS(ZCD)= －10mV C1 RRT(SET) 0 25 30 35 40 45 U1 OUT 50 OSC RRT (kΩ) CS 5 Figure 8-7 tON(MAX) as a function of RRT (IC design) Zero Current Detection and Bottom-on Timing (Delay Time) Setting Figure 8-8 shows the peripheral circuit of the RDLY pin and the CS pin. Figure 8-9 shows the waveform of each pin. The off-time and the bottom on timing of VDS are set by both zero current detection of inductor current, IL and the delay time. The off-time of a power MOSFET is set by the zero current detection signal of the CS pin and the delay time of the RDLY pin. Thus, simple PFC circuit with inductor having no auxiliary winding is realized. The zero current detection signal of inductor current, IL, is detected by RCS and it is inputted to the CS pin as shown in Figure 8-8. While the power MOSFET is in OFF state, the CS pin voltage decrease to the absolute value of Zero Current Detection Threshold Voltage, VCS(ZCD) = − 10 V, or less, the OUT pin outputs ON signal after the turn-on delay time, tDLY. The value of tDLY is determined by the value of the resistor, RDLY, connected to the RDLY pin. Figure 8-10 shows relationship between RDLY value and .tDLY value (IC design). As shown in Figure 8-11, the value of RDLY adjusts the turn-on timing to the bottom SSC2005SC-DS Rev.1.1 Feb. 06, 2015 GND RDLY 4 6 RCS R4 8.5 RT 3 C5 DZCS RRT C3 RDLY C4 Figure 8-8 The peripheral circuit of the RDLY pin and the CS pin VDS 0 ID 0 OUT pin voltage 0 IL 0 CS pin voltage 0 VZCD Turn on delay time, tDLY Figure 8-9 Zero current detection waveform SANKEN ELECTRIC CO.,LTD. 10 tDLY (μs) SSC2005SC When the FB pin voltage increase to Overvoltage Protection Threshold Voltage, VOVP, OUT pin voltage become Low immediately and the switching operation stops. As a result, the rise of output voltage is prevented. VOVP is 1.090 times the Feedback Control Voltage, VFB = 2.50 V. When the cause of the overvoltage is removed and FB pin voltage decreases to VOVP − VOVP(HYS), the switching operation restarts. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 8.8 15 20 25 30 35 40 45 50 55 60 RDLY (kΩ) Figure 8-10 tDLY as a function of and RDLY (IC design) tDLY Bottom on Free oscillation Ideal delay time Delay time is short. Make RDLY value larger. FB pin Under Voltage Protection (FB_UVP) Delay time is Long. Make RDLY value smaller. Figure 8-11 Turn-on timing of VDS FB pin Under Voltage Protection (FB_UVP) is activated when the FB pin voltage is decreased by the malfunctions in feedback loop such as the open of RVS1 or the short of RVS2. Figure 8-13 shows the FB pin peripheral circuit and internal circuit. When the FB pin voltage is decreased to VUVP = 300 mV or less, the OUT pin output is turned-off immediately and switching operation stops. This prevents the rise of output voltage. When the cause of malfunction is removed and the FB pin voltage rises to VUVP + VUVP(HYS), the switching operation restarts. In case the FB pin is open, the FB pin voltage is increase and Overvoltage Protection (OVP) is activated as described in Section 8.7. When the cause of malfunction is removed and the IC becomes nomal control, the switching operation rstarts. VOUT U1 Error AMP PWM COMP IFB RVS1 FB 1 8.6 Minimum Off-time Limit Function VFB = 2.50V In order to prevent the rise of operation frequency at light load, the IC have the Minimum Off-Time tOFF(MIN) = 1.95 μs. If this Minimum Off-Time is shorter than the freewheeling time of inductor, the IC operates in discontinuous condition mode (DCM). VOSC OVP UVP 8.7 Overvoltage Protection (OVP) Figure 8-12 shows the waveforms of Overvoltage Protection (OVP) operation. GND RVS2 C6 VOVP = 1.090×VFB VOVP(HYS) = 90mV VUVP = 300mV VUVP(HYS) = 120mV 6 Figure 8-13 The FB pin peripheral circuit and internal circuit. FB pin voltage VOVP VOVPHYS OUT pin voltage Figure 8-12 Overvoltage protection waveforms SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 11 SSC2005SC 8.9 Overcurrent Protection (OCP) Figure 8-14 shows the CS pin peripheral circuit and internal circuit. The inductor current, IL is detected by the detection resistor, RCS. The detection voltage, VRCS, is fed into the CS pin. The OCP COMP compares the detection voltage, VRCS with Overcurrent Protection Threshold Voltage, VCS(OCP) = − 0.60 V. When VRCS increases to absolute value of VCS(OCP) or more, the OUT pin output is turned-off by pulse-by-pulse. As shown in Figure 8-14, the CS pin is connected to capacitor-resistor filter (R4 and C5) and zener diode, DZCS, for the CS pin overvoltage protection. L1 D1 Q1 7 (4) where, VACRMS(MAX) : Maximum AC input voltage rms value (V) VDIF : Boost voltage (About 10V) (V) 2) Operational Frequency, fSW(SET) Determine fSW(SET) that is minimum operational frequency at the peak of the AC line waveform. The frequency becomes higher with lowering the input voltage. The frequency at the peak of the AC line waveform, fSW(SET) should be set more than the audible frequency (20 kHz). VOUT U1 ZCD COMP OUT C2 VCS(ZCD) = －10mV OCP COMP VCS(OCP) = －0.60V 3) Inductance, LP Substituting both minimum and maximum of AC input voltage to VACRMS, choose a smaller one as LP value. LP is calculated as follows: LP CS 5 VACRMS VOUT 2 VACRMS 2 POUT f SW (SET ) VOUT 2 GND 6 VOUT 2 VACRMS ( MAX ) VDIF (V) (H) (5) DZCS VRCS C5 RCS R4 LINE GND Figure 8-14 The CS pin peripheral circuit and internal circuit. 9. 9.1 Design Notes where, η : Efficiency of PFC (In general, the range of η is 0.90 to 0.97, depending on on-resistance of power MOSFET RDS(ON) and forward voltage drop of rectifier diode VF.) VACRMS : Maximum/Minimum of AC input voltage rms value (V) VOUT : Output voltage (V) POUT : Output power (W) fSW(SET) : Minimum operational frequency at the peak of the AC line waveform (kHz) Inductor Setup Apply proper design margin to temperature rise by core loss and copper loss. The calculation methods of inductance ,LP, is as shown below. Since the following calculating formulas are approximated, the peak current and the frequency of operational waveforms may be different from the setting value at calculating. Eventually, the inductance value should be adjusted in actual operation. Apply proper design margin to temperature rise by core loss and copper loss. 1) Output Voltage, VOUT The output voltage VOUT of boost-converter should be set to a higher value than peak value of input voltage, shown in the following equation: SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 12 SSC2005SC 9.2 External Components Take care to use properly rated, including derating as necessary and proper type of components. Figure 9-1 shows the IC peripheral circuit. L1 D1 VOUT U1 Q1 7 PWM COMP VCOMP OUT RVS1 Error AMP FB 1 Q R S VSET VFB = 2.5V VOSC ZCD COMP VCS(ZCD)= -10mV RVS2 CS 5 RT 3 GND 6 RDLY 4 COMP 2 RS RCS C5 DZCS RRT C3 RDLY C4 CP CS R4 Figure 9-1 The IC peripheral circuit. FB Pin Peripheral Circuit (Output VoltageDetection) The output voltage VOUT is set using RVS1 and RVS2. It is expressed by the following equation: V VOUT FB I FB R VS1 VFB (V) R VS 2 where, VFB IFB RVS, RVS2 (6) : Feedback reference voltage = 2.50 V : Bias current = − 2.0 µA : Combined resistance to set VOUT (Ω) Since RVS1 have applied high voltage and have high resistance value, RVS1 should be selected from resistors designed against electromigration or use a combination of resistors for that. The value of capacitor C6 between the FB pin and the GND pin is set approximately 100 pF to 3300 pF, in order to reduce the switching noise. COMP Pin Peripheral Circuit: RS, CS and CP Figure 9-1 shows the IC peripheral circuit. The FB pin voltage is induced into internal Error AMP. The output voltage of the Error AMP is averaged by the COMP pin. The on-time control is achieved by comparing the signal VCOMP and the ramp signal VOSC. CS and RS adjust the response speed of changing on-time according to output power. The typical value of CS and RS are 1 μF and 10 kΩ, respectively. When CS value is too large, the response becomes slow at dynamic variation of output and the output voltage decreases. Since CS and RS affect on the soft-start period at startup, adjustment is necessary in actual operation. SSC2005SC-DS Rev.1.1 Feb. 06, 2015 RT Pin Peripheral Circuit: RRT and C3 The value of capacitor C3 in parallel with RRT is approximately 0.01 μF, in order to reduce the switching noise. RRT is 15 kΩ to 47 kΩ for the adjustment of maximum on-time, tON(MAX). Refer to Section 8.4 for RRT setting. RDLY Pin Peripheral Circuit: RDLY and C4 RDLY shown in Figure 9-1 is for the adjustment of the turn-on delay time, tDLY, of the Power MOSFET. As shown in Section 8.5 Zero Current Detection, adjust the value of RDLY and turn-on timing to the bottom point of VDS free oscillation waveform on actual operation in the application. The range of RDLY is 15 kΩ to 56 kΩ. The value of capacitor C4 is approximately 0.01 μF, in order to reduce the switching noise. C6 OSC The ripple of output detection signal is averaged by CP. When the CP value is too small, the IC operation may become unstable due to the output ripple. The value of capacitor CP is approximately 0.47 μF. CS Pin Peripheral Circuit: RCS, R4, C5 and DZCS RCS shown in Figure 9-1 is current sensing resistor. RCS is calculated by the following Equation (7), where Overcurrent Protection Threshold Voltage VCS(OCP) is − 0.60 V and ILP is calculated by Equation (1). R CS VCS( OCP ) I LP (Ω) (7) The CR filter (R4 and C5) prevents IC from responding to the drain current surge at power MOSFET turn-on and avoids the unstable operation of the IC. R4 value of approximately 47 Ω is recommended, since the CS Pin Source Current affects the accuracy of OCP detection (see Section 8.5). C5 value is recommended to be calculated by using following equation in which the cut-off frequency of the CR filter (C5 and R4) is approximately 1 MHz. C5 1 (F) 2 π110 6 R 4 (8) If R4 value is 47 Ω, C5 value is approximately 3300 pF. The absolute voltage of the CS pin is −5 V. The CS pin voltage may exceed the absolute value when the startup current to a charge output capacitor, C2, flows RCS. Thus, DZCS is used for the overvoltage protection of the CS pin. DZCS value of approximately 3.9 V is recommended. The value should be higher than VCS(OCP) and be lower than the CS pin absolute maximum rating of −5 V. SANKEN ELECTRIC CO.,LTD. 13 SSC2005SC OUT Pin Peripheral Circuit (Gate Drive Circuit) Figure 9-2 shows the OUT pin peripheral circuit. The OUT pin is the gate drive output which can drive an external power MOSFET directly. The maximum output voltage of the OUT pin is the VCC pin voltage. The maximum current is −500 mA for source and 1 A for sink, respectively. R1 is for source current limiting. Both R2 and D2 are for sink current limiting. The values of these components are adjusted to decrease the ringing of Gate pin voltage and the EMI noise. The reference value is several ohms to several dozen ohms. R3 is used to prevent malfunctions due to steep dv/dt at turn-off of the power MOSFET, and the resistor is connected near the power MOSFET, between the gate and source. The reference value of R3 is from 10 kΩ to 100 kΩ. R1, R2, D2 and R3 are affected by the printed circuit board trace layout and the power MOSFET capacitance. Thus, the optimal values should be adjusted under actual operation of the application. L1 U1 OUT Q1 R1 7 R2 GND 6 D2 R3 RCS Figure 9-2 The OUT pin peripheral circuit. VCC Pin Peripheral Circuit Figure 9-3 shows the VCC pin peripheral circuit. The VCC pin is power supply input. The VCC pin is supplied from an external power. When the VCC pin and the external power supply are distant from each other, placing a film capacitor Cf between the VCC pin and the GND pin is recommended. The value of capacitor Cf is set approximately 0.47 μF, in order to reduce the switching noise. External Power Supply 8 Cf VCC U1 Power MOSFET : Q1 Choose a power MOSFET having proper margin of VDSS against output voltage, VOUT. The size of heat sink is chosen taking into account some loss by switching and ON resistance of the power MOSFET. The RMS value of drain current, IDRMS is expressed as follows: I DRMS＝ 2 2 POUT VACRMS ( MIN ) 1 4 2 VACRMS(MIN) － 6 9 π VOUT (A) (9) The loss, PRDS(ON), by on-resistance of the power MOSFET is calculated as follows: PRDS (ON ) I DRSM R DS(ON )125 C (W) 2 where, VACRMS(MIN) POUT η RDS(ON)125°C (10) : Minimum AC input voltage rms value (V) : Output power (W) : Efficiency of PFC : ON resistance of the power MOSFET at Tch = 125 °C (Ω) Boost Diode: DFW Choose a boost diode having proper margin of a peak reverse voltage VRSM against output voltage, VOUT. A fast recovery diode is recommended to reduce the switching noise and loss. Please ask our staff about our lineup. The size of heat sink is chosen taking into account some loss by VF and recovery current of the boost diode. The loss of VF, PDFW, is expressed as follows: P DFW VF I OUT (W) (11) Where, VF : Forward voltage of boost diode (V) IOUT : Out put current (A) Bypass Diode: DBYP A Bypass diode protects a boost diode from a large current such as an inrush current. A high surge current tolerance diode is recommended. Please ask our staff about our lineup. GND 6 Figure 9-3 The VCC pin peripheral circuit SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 14 SSC2005SC Output Capacitor: C2 Apply proper design margin to accommodate the ripple current, the ripple voltage and the temperature rise. Use of high ripple current and low impedance types, designed for switch-mode power supplies, is recommended, depending on their purposes. C2 is calculated by both Equation (12) and (14), and is selected the large value of them. 9.3 1) Given the C2 ripple voltage VOUTRIPPLE (VPP) (10 VPP for example), C2 is expressed as follows: Figure 9-4 shows the circuit design example. Figure 9-5 shows the PCB pattern layout example around the IC. C2 I OUT (F) 2 f LINE VOUT ( RI ) (1) Main Circuit Trace This is the main trace containing switching currents, and thus it should be as wide trace and small loop as possible. The C2 voltage is expressed by Equation (13). When the output ripple is high, the VC2 voltage may reach to Overvoltage Protection voltage, VOVP, in near the maximum value of VC2, or input current waveform may be distorted due to the stop of the boost operation in near the minmum value of VC2. It is necessary to select large C2 value or change the setting of output voltage (boost voltage). VOUT ( RI ) 2 (V) (13) 2) Given the output hold time as tHOLD (s), C2 is expressed as follows: C2 V 2 POUT t HOLD OUT 2 VOUT ( MIN ) 2 Since the PCB circuit trace design and the component layout significantly affects operation, EMI noise, and power dissipation, the high frequency PCB trace should be low impedance with small loop and wide trace. In addition, the ground traces affect radiated EMI noise, and wide, short traces should be taken into account. (12) where, fLINE :Line frequency (Hz) IOUT :Output current (A) VC 2 VOUT PCB Trace Layout and Component Placement (F) (14) (2) Control Ground Trace Layout Since the operation of the IC may be affected from the large current of the main trace that flows in control ground trace, the control ground trace should be separated from main trace and connected at a single point grounding of point A in Figure 9-4 as close to the RCS as possible. (3) RCS Trace Layout RCS should be placed as close as possible to the Source pin and the CS pin. The peripheral components of the CS pin should be connected by dedicated pattern from root of RCS. The connection between the power ground of the main trace and the IC ground should be at a single point ground which is close to the base of RCS. (4) Peripheral Component of the IC The components for control connected to the IC should be placed as close as possible to the IC, and should be connected as short as possible to the each pin. where, tHOLD : Output hold time (s) VOUT(MIN) : Minmum output voltage of C2 during output hold (V) η : Efficiency SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 15 SSC2005SC (1) Main trace should be wide trace and small loop BR1 L1 DBYP D1 VAC D2 VOUT R2 C2 Q1 C1 R1 R3 (3)RCS Should be as close to Source pin as possible. LINE GND RCS (3) Connected by dedicated pattern from root of RCS A R4 (2) Control GND trace should be connected at a single point as close to the RCS as possible U1 RDLY GND NC RT OUT COMP VCC FB 5 DZCS RDLYC4 CS 4 C5 6 RRT C3 3 CP 7 Cｆ External Power Supply 8 SSC2005SC 2 RS CS RVS1 1 C6 RVS2 (4)The components connected to the IC should be as close to the IC as possible, and should be connected as short as possible TC_SSC2005SC_3_R2 Figure 9-4 Example of connection of peripheral component Q1 C1 C2 RCS Close to C1 Close to C2 and source of Q1 R4 DZCS Q1 gate drive C5 VOUT 6 5 CS 7 OUT VCC Cf 8 GND External power supply U1 Main trace RDLY CP C3 4 RDLY 3 RS CS Control GND trace C4 2 RRT 1 RVS1 RT COMP FB C6 RVS2 SSC2005SC TC_SSC2005SC_4_R2 Figure 9-5 Example of connection of peripheral component SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 16 SSC2005SC 10. Reference Design of Power Supply As an example, the following show the power supply specification, the circuit schematic, the bill of materials. Circuit schematic IC Input voltage Output power Output voltage Minimum operational frequency at the peak of the AC line waveform Efficiency SSC2005SC AC 85 to AC 265 V 200 W 390 V 40 kHz (AC 265 V) 0.95 Circuit schematic F1 D3 BR1 L1 D1 VAC C1 D2 C2 VOUT R2 Q1 C4 C3 R1 R3 R5 LINE GND R4 R6 DZ1 C10 CS RDLY NC U1 RT 5 GND 6 C11 External power supply 7 8 OUT COMP VCC FB R14 R13 R10 R15 R12 R11 4 R9 3 C9 2 C8 SSC2005SC C6 1 C5 R17 R16 R8 R7 C7 TC_SSC2005SC_5_R1 Bill of materials Symbol BR1 F1 L1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 R1 R2 R3 R4 Part type General Fuse Inductor (2) (2) (2) (2) (2) Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic Ceramic General General General General Ratings(1) 600 V AC 250 V 170 μH (EI30) 450 V, 0.68 μF 450 V, 0.68 μF 450 V, 180 μF 1kV, 100pF 1000 pF 0.47 μF 1 μF 0.01 μF 0.01 μF 3300 pF 0.47 μF 100 Ω 10 Ω 100 kΩ 47 Ω Recommended Symbol Sanken Parts R5 R6 R7 R8 R9 (2) R10 (3) R11 (3) R12 (3) R13 (3) R14 (3) R15 (3) R16 (2) R17 D1 D2 D3 U1 Part type General General General General General General General General General General General General General Fast recovery Schottky General IC Ratings(1) 0.15 Ω, 2W 0.15 Ω, 2W 10 kΩ 15kΩ 15kΩ 180 kΩ, 1% 820 kΩ, 1% 560 kΩ, 1% 560 kΩ, 1% 680 kΩ, 1% 680 kΩ, 1% Open 22 kΩ, 1% 600V, 10 A 60 V, 0.7 A 600V, 1.2A Recommended Sanken Parts FMNS-1106S AK06 RM10A SSC2005SC (1) Unless otherwise specified, the voltage rating of capacitor is 50 V or less and the power rating of resistor is 1/8 W or less. It is necessary to be adjusted based on actual operation in the application. (3) Resistors applied high DC voltage and of high resistance are recommended to select resistors designed against electromigration or use combinations of resistors in series for that to reduce each applied voltage, according to the requirement of the application. (2) SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 17 SSC2005SC OPERATING PRECAUTIONS In the case that you use Sanken products or design your products by using Sanken products, the reliability largely depends on the degree of derating to be made to the rated values. Derating may be interpreted as a case that an operation range is set by derating the load from each rated value or surge voltage or noise is considered for derating in order to assure or improve the reliability. In general, derating factors include electric stresses such as electric voltage, electric current, electric power etc., environmental stresses such as ambient temperature, humidity etc. and thermal stress caused due to self-heating of semiconductor products. For these stresses, instantaneous values, maximum values and minimum values must be taken into consideration. In addition, it should be noted that since power devices or IC’s including power devices have large self-heating value, the degree of derating of junction temperature affects the reliability significantly. Because reliability can be affected adversely by improper storage environments and handling methods, please observe the following cautions. Cautions for Storage Ensure that storage conditions comply with the standard temperature (5 to 35°C) and the standard relative humidity (around 40 to 75%); avoid storage locations that experience extreme changes in temperature or humidity. Avoid locations where dust or harmful gases are present and avoid direct sunlight. Reinspect for rust on leads and solderability of the products that have been stored for a long time. Cautions for Testing and Handling When tests are carried out during inspection testing and other standard test periods, protect the products from power surges from the testing device, shorts between the product pins, and wrong connections. Ensure all test parameters are within the ratings specified by Sanken for the products. Soldering When soldering the products, please be sure to minimize the working time, within the following limits: • 260 ± 5 °C 10 ± 1 s (Flow, 2 times) • 380 ± 10 °C 3.5 ± 0.5 s (Soldering iron, 1 time) Electrostatic Discharge When handling the products, the operator must be grounded. Grounded wrist straps worn should have at least 1MΩ of resistance from the operator to ground to prevent shock hazard, and it should be placed near the operator. Workbenches where the products are handled should be grounded and be provided with conductive table and floor mats. When using measuring equipment such as a curve tracer, the equipment should be grounded. When soldering the products, the head of soldering irons or the solder bath must be grounded in order to prevent leak voltages generated by them from being applied to the products. The products should always be stored and transported in Sanken shipping containers or conductive containers, or be wrapped in aluminum foil. SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 18 SSC2005SC IMPORTANT NOTES The contents in this document are subject to changes, for improvement and other purposes, without notice. Make sure that this is the latest revision of the document before use. Application examples, operation examples and recommended examples described in this document are quoted for the sole purpose of reference for the use of the products herein and Sanken can assume no responsibility for any infringement of industrial property rights, intellectual property rights, life, body, property or any other rights of Sanken or any third party which may result from its use. Unless otherwise agreed in writing by Sanken, Sanken makes no warranties of any kind, whether express or implied, as to the products, including product merchantability, and fitness for a particular purpose and special environment, and the information, including its accuracy, usefulness, and reliability, included in this document. Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to the society due to device failure or malfunction. Sanken products listed in this document are designed and intended for the use as components in general purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). When considering the use of Sanken products in the applications where higher reliability is required (transportation equipment and its control systems, traffic signal control systems or equipment, fire/crime alarm systems, various safety devices, etc.), and whenever long life expectancy is required even in general purpose electronic equipment or apparatus, please contact your nearest Sanken sales representative to discuss, prior to the use of the products herein. The use of Sanken products without the written consent of Sanken in the applications where extremely high reliability is required (aerospace equipment, nuclear power control systems, life support systems, etc.) is strictly prohibited. When using the products specified herein by either (i) combining other products or materials therewith or (ii) physically, chemically or otherwise processing or treating the products, please duly consider all possible risks that may result from all such uses in advance and proceed therewith at your own responsibility. Anti radioactive ray design is not considered for the products listed herein. Sanken assumes no responsibility for any troubles, such as dropping products caused during transportation out of Sanken’s distribution network. The contents in this document must not be transcribed or copied without Sanken’s written consent. SSC2005SC-DS Rev.1.1 Feb. 06, 2015 SANKEN ELECTRIC CO.,LTD. 19