CXB1549Q Laser Diode Driver Description The CXB1549Q is a high-speed monolithic Laser Diode Driver/Current Switch with ECL/PECL input level. Open collector outputs are provided at the output pins (Q, QBX) and have the capacity of driving modulation current of 50mAp-p at a max. data rate of 1.25Gbps (Min.). Along with the modulation current generator there is the laser diode bias generator which has capacity of sourcing up to 60mA (Bias). The laser diode current can be controlled by either a voltage or current into the bias adjust pin (BiasAdj) and the bias set pin (SBias), depending on how these pins are configured. Control of the diode bias current is achieved through the APC (Automatic Power Control) circuitry. In order to avoid having a large current go through the laser diode, this IC also provides an Activity detector and Power on Reset functions for Laser Safety. The Activity detector circuit detects data edge transitions and if no data transition occur after a certain time period, then both the modulation and bias current are shutdown. The Power on Reset circuit holds the modulation and bias current off for a set period of time while the system power is applied. Additionally, this IC has an internal Duty Cycle correction circuit that can control the falling edge of the input pulse up to a maximum of 0.2ns (Min.). Features • Maximum data rate (NRZ): 1.25Gbps • Power on Reset function • Alarm and Shutdown function • Signal Duty cycle correction • Automatic Power Control (APC) for bias current • Activity detector function for laser safety • Power indicate function • Differential PECL inputs or AC coupled inputs 40 pin QFP (Plastic) Application • Gbit-ethernet: 1.25Gb/s • SONET/SDH: 622Mb/s • Fibre channel: 532Mb/s, 1.062Gb/s Absolute Maximum Ratings • Supply voltage Vcc – VEE –0.3 to +6.0 VEE to Vcc • Input voltage VIN • Differential input voltage | VD – VDB | 0 to 2.5 • Bias output current 0 to 80 • Modulation output current 0 to 70 • SBias input/output current 0 to 5 • Input bias control current Iset (Ibiasadj) 0 to 5 • Input bias control voltage Vset (Vbiasadj) 0 to 3 • Storage temperature Tstg –65 to +150 Recommended Operating Conditions • DC power supply voltage 3.14 to 3.46 Vcc – VEE • Operating ambient temperature Ta –40 to +85 V V V mA mA mA mA V °C V °C Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98313B92-PS CXB1549Q LDAlmB RS RSB Tset Indicate VBB VCC2 D DB VEE2 Block Diagram and Pin Assignment 30 29 28 27 26 25 24 23 22 21 LDAlm 31 Reference Generator VBB Generator 20 ADCDis 19 TM 18 NC SDN 32 Duty Cycle Cont In_ALM 17 Timer SDNB 33 VREF 34 VREF 16 CompB TEST_PIN 35 VCC3 36 Power on Reset 15 CompA DRV Cont CapZ 37 14 DrvAdj VEE3 38 13 DrvMon APCOut 39 12 VEE1 RsetPD 40 Bias Circuit VEE4 BiasAdj SBias Bias –2– 6 7 8 9 10 VEE1 5 VEE1 4 QBX 3 Q 2 VEE5 1 VCC4 11 VCC1 CXB1549Q Pin Description Pad No. Symbol Typical voltage [V] DC Equivalent circuit AC Description 1 VCC4 3.3 Positive power supply pin for APC circuit. 2 VEE4 0 Negative power supply pin for APC circuit. 3 BiasAdj 1.5 to 0 VCC 4 SBias 0mA to 2.5mA 3 5 Bias 0mA to 60mA 6 VEE5 0 7 8 Q QBX 1.3 to 3.3 1.3 to 3.3 4 Sets Laser bias current pin. 5 Sets Laser bias current or monitor pin. 30 10pF 8 240 Laser bias current output pin. Open collector output. VEE Negative power supply pin for Bias circuit. 6mA to 30mA∗1 7 Laser modulation current output pin. Open collector output. 8 6mA to 50mA∗2 6mA to 30mA∗1 Complementary current output pin. Q and QBX are not symmetrical output. Use Q output for Laser modulation. Current Source 6mA to 50mA∗2 VEE 9, 10 VEE1 0 Negative power supply pin for Driver circuit. 11 VCC1 3.3 Positive power supply pin for Driver circuit. 12 VEE1 0 Negative power supply pin for Driver circuit. 13 DrvMon 0µA to 600µA Rdrv VCC Rmon 14 13 14 DrvAdj ∗1 Ta = –40 to 0°C ∗2 Ta = 0 to +85°C 0µA to 600µA 150 150 1.3k VEE –3– Sets Laser modulation current (IQ) monitor pin. IQ is monitored by connecting a resistor (Rmon) to this pin. Sets Laser modulation current pin (IQ). IQ is controlled by connecting a resistor (Rdrv) to this pin. Refer to Fig.2. CXB1549Q Pad No. 15 Symbol Typical voltage [V] DC Equivalent circuit CompA VCC Modulation current driver compensation pin. Normally, connects 180pF Capacitor across CompA and CompB pins. 15 180pF 30pF 16 16 Description AC 10k CompB VEE VCC 2.1k Ctimer 2.4k 17 2.4k 17 Timer 10pF 200µA 25µA VEE 18 NC 19 TM Capacitor port pin for activity detector (IN_ALM) operation. This pin set the period of inactive time for activity detector. Inactive time is controlled by connecting a capacitor to this pin. Refer to Fig.6. No Connect pin. 1.5 VEE 19 21 Chip temperature monitor pin. VCC 3.8k 20 ADCDis VEE to VCC (open) 3.8k 35k 35k 35k 35k 20 15µA This pin control the activity detector Circuit. High (connected to Vcc or open): an activity detector is disable. Low (connected to VEE): an activity detector is enable. VEE 21 VEE2 Negative power supply pin for Data input circuit. 0 –4– CXB1549Q Pad No. 22 Symbol Typical voltage [V] DC DB Equivalent circuit 1.6 to 2.4 24 300 300 22 23 D 400 200 1.6 to 2.4 23 24 VCC2 25 VBB Description AC 25 200 10k Positive power supply pin for Data input circuit. 10k 3.3 21 Reference bias voltage. (Option) 600µA 600µA 2 VCC 50µA 26 Indicate 0.7 to 1.7 35µA 35µA 100k 26 14k VEE VCC 2.4k 2.4k Rset 20pF 27 27 Tset 70µA 220 VEE 140 VCC 28 RSB 100µA 0.5 2.5k 29 20k 28 29 RS Differential PECL data inputs pins. These two inputs are internally biased by 10kΩ to VBB. 5k 2.5 VEE –5– The analog voltage high impedance output pin which indicate of whether the optical power of Laser diode is operated normal or not. The power output range has following relationship. High Light Indication; Vo ≥ 1.7V Nominal Operation; Vo = 1.2V Low Light Indication; Vo ≤ 0.7V Selector for output duty cycle control pin. This pin controls the trailing edge of the input high pulse. Variable delay limit of that is from 0 to 0.2ns. Duty cycle is controlled by connected a resistor value between Vcc and this pin. Refer to Fig.1. Window comparator top/bottom threshold voltage pin for LD_ALARM. The alarm (fail) threshold assert voltage can be set by the external resistor. Default voltages are RS equal to 2.5V and RSB equal to 0.5V. CXB1549Q Pad No. Symbol 30 LDAlmB Typical voltage [V] DC Equivalent circuit AC Description VCC 0.2 to 3 4.7k 4.7k 30 31 31 LDAlm Complementary open collector TTL outputs. Asserted when the fault is detected in the Laser monitor diode circuit. 0.2 to 3 VEE VCC 32 SDN 0 to 3.3 5k 5k 5k 5k Complementary TTL inputs pin to disable output current. (shutdown input) When left open = "High" 300 32 300 33 33 SDNB 60µA 0 to 3.3 60µA VEE VCC 300 300 Temperature compensated reference voltage pin for APC. 1.7V (Constant for VEE reference) 200 34 34 VREF 1.7 2.4k 9.1k 1.9mA VEE 35 TEST_ PIN OPEN Do not connect. 36 VCC3 3.3 Positive power supply pin for Signal Detect circuit. –6– CXB1549Q Pad No. Symbol Typical voltage [V] DC Equivalent circuit AC Description VCC 3k Rseries 200 37 37 CapZ Cap_Z 145µA 145µA VEE 38 VEE3 Capacitor and resistor port pins for slow start up. This pin controls the initial turn-on time of this IC (release time of bias and modulation current). The time for this function is set by an external RC network. Refer to Fig.7. Negative power supply pin for Signal Detect circuit. 0 VCC 39 APCOut Output pin of APC OPAmp. This signal control to bias adjust pins. (BiasAdj and SBias) 39 500 VEE VCC 300 300 200 40 40 Monitor PD connect pin. RsetPD 1.8mA VEE –7– CXB1549Q Electrical Characteristics DC Electrical Characteristics (VCC = 3.14 to 3.46V, VEE = 0V, Ta = –40 to +85°C) Symbol Item Condition Min. Typ. Max. Unit V DC Power supply voltage Vdc VCC – VEE 3.14 3.3 3.46 Power supply current IEE IQ = 0mA, IBIAS = 0mA –76 –59 — IQ1 Ta = –40 to 0°C 6 — 30 IQ2 Ta = 0 to +85°C 6 — 50 Modulation output current range mA Modulation output voltage range VQ VCC – 2 — VCC V Bias output current range IB 0 — 60 mA Bias output voltage range VB VCC – 2 — VCC V Ratio of IB vs. Iset IBvslset 14 22 27 — ECL input High voltage VEIH VCC – 1.17 — VCC – 0.81 ECL input Low voltage VEIL VCC – 1.84 — VCC – 1.48 SDN, SDNB, Reset input High voltage VTIH 2 — VCC SDN,SDNB, Reset input Low voltage VTIL 0 — 0.8 LDA, LDAB output High voltage VTOH IOH = –10µA, RL = 4.7kΩ VCC – 0.1 — VCC + 0.2 LDA, LDAB output Low voltage VTOL IOL = 1mA, RL = 4.7kΩ 0 — 0.4 Reference bias voltage for OP Amp VREF 1.5 1.7 1.9 Operating current range of VREF VREFdrv –500 — +500 AC Electrical Characteristics Item V µA (VCC = 3.14 to 3.46V, VEE = 0V, Ta = –40 to +85°C) Symbol Condition Min. Typ. Max. Unit 1.25 — — Gbps Maximum Data Rate fdmax Rise time (20 to 80%) tr IQ = 20mA, RL = 25Ω — 100 — Fall time (20 to 80%) tf IQ = 20mA, RL = 25Ω — 200 — Max. variable High pulse width by duty cycle control tdelay Data rate = 1.25Gbps 0.2 — — Max. setting time range of IN_Alarm ts_alm 20 — — Max. setting time range of POR ts_por 150 — — Shut down time tsut_off — — 10 Shut down recovery time tsut_on — — 100 –8– ps ns µs CXB1549Q DC and AC Electrical Characteristics for OpAmp of APC Circuitry (VCC = 3.14 to 3.46V, VEE = 0V, Ta = –40 to +85°C) Item Symbol Condition Min. Typ. Max. Unit Input voltage range VIN 1.2 — 2.8 V Output voltage range VO 0.6 — 2 V Input bias current IB — 7 — µA Input offset voltage VOFF — 2.5 — mV Input offset Input current IOFF — 0.7 — µA Input impedance ZIN — 12 — kΩ Output drive current IO –5.0 — 1.0 mA Through rate SR — 1.9 — V/µs Open loop gain Av — 55 — dB Unity gain band-width funit — 20 — MHz –9– CXB1549Q Description of each function block 1. Data Buffer Data Buffer is comprised of the data buffer and delay generator. ECL/PECL data is input to the data buffer at a maximum data rate of 1.25Gbps. This data is buffered and input to the delay circuitry. The delay circuitry adds a delay to the falling edge of the pulse up to a maximum of 0.2ns (Min.). The delay is set by a single external resistor between the delay set pin (Tset-Pin 27) and Vcc. A plot of the high pulse width vs. set resistance (Rset) is shown in Fig. 1. 2. VBB Generator This circuit provides a reference bias voltage to the data buffer for AC coupling inputs. 3. Modulation Current Generator This circuit can sink up to 50mA of current to modulate the laser diode. The modulation current is set by an external resistor to Vcc at modulation current set pin (DrvAdj-Pin 14). There is also a modulation current monitor pin (DrvMon-Pin 13) that allows the IC user to monitor the modulation current. By putting an external fixed resistor between Vcc and DrvMon pin, you can monitor the modulation current by measuring the voltage of DrvMon pin. The modulation current and monitor current are in the rate of approximately 50:1 (Refer to Figs. 8 and 9). A plot of the modulation current vs. setting resistance (Rdrv) is shown in Fig. 2. 4. Laser Diode Bias Current Generator This circuit is a very large current source capable of sourcing up to 60mA of current to bias the laser diode on. The circuit is a 22 to 1 (for current – current setting) current mirror that can be controlled externally two ways. The first of these is to tie the BiasAdj (Pin 3) and SBias (Pin 4) terminals together and inject a current into the two terminals. The Bias (Pin 5) terminal is connected to the laser diode. Laser diode bias current vs. control current (Iset) characteristics is shown in Fig. 3. The second method of controlling the laser diode current is to ties the SBias (Pin 4) terminal to Vcc and tune the BiasAdj (Pin 3) terminal with a voltage source. Varying the voltage at the BiasAdj terminal will vary the current through the laser diode. Laser diode bias current vs. control voltage characteristics is shown in Fig. 4. 5. APC (Automatic Power Control) Circuitry The APC Circuitry is comprised of the window comparator, APC OpAmp, laser diode alarm circuit and the diode power indicator. The APC OpAmp is normally configured as an inverting integrator. The inverting input is connected to the photo diode that monitors the light intensity from the laser diode. The photo diode converts the received light from the laser diode to a current. The output of the OpAmp then drives the laser diode current bias adjust pin, and the laser diode bias set pin is held at Vcc via a resistor. With the OpAmp configured as an inverting integrator, the OpAmp can tune the diode current inversely to the current in the photo diode. That is to say that if a low current is detected by the photo diode the integrator output goes up causing more bias current to go through the diode. If the photo diode current is high, then the output of the OpAmp will go low causing less bias current to flow through the laser diode. The output of the APC OpAmp drives a window comparator. The function of the window comparator is to detect when the output of the APC OpAmp goes above or below a preset reference voltage for each comparator (RS, RSB). When this happens the comparators outputs cause the laser diode alarm circuit (LDAlm) to go high alerting the system that the laser diode current is either to high or to low. The window comparator also drives the laser diode power indicator circuit (Indicate). This circuit is comprised of two switches and one fixed current sources. When the APC OpAmp output is such that the laser diode bias current is at its nominal set point, the output of the power indicator is at approximately 1.2Vdc. If the APC OpAmp output goes low, the output of the power indicator increases to approximately 1.7Vdc, indicating a high laser diode power condition. If the output of the APC OpAmp goes high, the output of the power indicator drops to approximately 0.7Vdc. Also connected to the output of the window comparator is laser alarm circuitry. This circuit alerts the user of the device when the laser diode power level has risen either twice the normal set power or half the normal set power. A high voltage at the laser diode alarm output indicates an alarm event. The laser diode alarm output is disabled whenever a shutdown event is encountered. – 10 – CXB1549Q 6. Shutdown and Input Alarm Circuitry This portion of the circuit disables both the modulation current driver and the laser diode bias generator under various conditions. The function block diagram for all of the shutdown mechanisms for the circuit is shown in Fig. 5. Shown below is the signal priority primarily for the reset function. 1) Power on Reset 2) Shutdown, Input Alarm The Shutdown circuit has complementary TTL input to disable output current. Shown below is the desired truth table for the shutdown function. SDN SDNB output current Low Low Off Low High On High Low Off High High Off The Activity detector (In_ALM) circuit is designed to detect an input pulse transition. If there is no input pulse transition over a period time determined by the user, then the shutdown circuit is enabled causing the modulation current and laser bias current to be shutdown. Inactive time is set by external capacitor value between Timer pin (Pin 17) and VCC. Inactive time vs. Ctimer is shown in Fig.6. The Power on reset circuit is an inverting comparator that has an external RC network with CapZ pin (Pin 37) that is connected between Vcc and VEE. At power up, the RC begins to charge up towards the reference voltage of the comparator. Since this is an inverting comparator the output will stay high until the capacitor charges above the reference. As long as the comparator output is high, the laser diode is disabled. As soon as the capacitor charges up beyond the reference, the output of the circuit goes low and the laser diode is enabled and ready for normal operation. A plot of the power on reset time vs. capacitance for a 10kΩ resistor (Rseries) is shown in Fig. 7. SDN Shutdown SDNB Switch D In_ALM To Modulation and Bias Current shutdown circuits DB Timer ADCDis Power on Reset (CapZ) Power on Reset Fig.5. Shutdown and In_ALM Functional Block Diagram 7. Others Pay attention to handling this IC because its electrostatic discharge strength is weak. The Tset terminal (27pin) has to be connected through a resistor to Vcc. Do not leave this pin open or connect to Vcc directly. – 11 – CXB1549Q DC Electrical Characteristics Measurement Circuit 4.7k V V V 29 28 2k V V 26 25 –10µ or 1mA 30 27 24 23 22 21 4.7k 31 Reference Generator V VBB Generator 20 V 19 V 18 32 Duty Cycle Cont In_ALM 17 33 0.1µF V V 34 VREF 16 –500 to 35 500µA 36 10k 180pF Power on Reset 15 DRV Cont 37 14 38 13 1000pF V A 39 1k 12 40 Bias Circuit 1k 1 2 3 11 4 5 6 7 A 8 9 10 A 25 0 to 2V A A 3.14 to 3.46V – 12 – CXB1549Q AC Electrical Characteristics Measurement Circuit 51 4.7k 30 51 0.1µF 29 28 27 26 25 24 23 0.1µF 22 21 4.7k 31 Reference Generator VBB Generator 20 19 18 32 Duty Cycle Cont In_ALM 17 33 0.1µF 34 VREF 100k 16 35 36 10k 180pF Power on Reset 15 DRV Cont 37 14 38 13 1000pF 1k 39 12 40 Bias Circuit 1µF 1 2 3 4 11 5 6 7 8 9 10 25 Z0 = 50 Spectrum analizer 1µF Oscilloscope 50Ω input – 13 – 3.14 to 3.46V CXB1549Q Application Circuit (at VCC = 3.3V, VEE = 0V) VCC LDAlm LDAlmB Indicate PECL input 0.1µF VCC 4.7k 100pF Rset 4.7k 30 29 31 28 27 26 25 Reference Generator 24 23 22 21 VBB Generator 20 19 SDN 32 SDNB 33 34 18 Duty Cycle Cont In_ALM 17 Ctimer VREF 180pF VCC 16 35 10k 100pF 36 CapZ Rf Power on Reset 15 Rdry DRV Cont 37 14 38 13 510 39 Cpd 12 40 Bias Circuit 1 2 3 4 11 5 6 7 8 9 10 Rs 15 RI lset 5.1 20 Rpd 100pF 0.1µF 3.3V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – CXB1549Q Example of Representative Characteristics 60 0.4 50 0.2 40 0.1 IQ [mA] Falling edge delay [ns] 0.3 0 –0.1 30 20 –0.2 10 –0.3 –0.4 0 1 2 3 4 5 Rset [kΩ] 6 7 0 8 70 70 60 60 50 50 40 30 10 10 0.5 1 1.5 Iset [mA] 2 2.5 8 10 30 20 0 4 6 Rdrv [kΩ] 40 20 0 2 Fig. 2. Modulation Current (IQ) vs. Rdrv Characteristics IBIAS [mA] IBIAS [mA] Fig. 1. Delay vs. Rset Characteristic at 1ns input data pulse apply 0 0 3 Fig. 3. Bias Current (IBIAS) vs. Bias adjust current (Iset) Characteristics 0.4 0.6 0.8 1 Vset [V] 1.2 1.4 1.6 Fig. 4. Bias Current (IBIAS) vs. Bias adjust voltage (Vset) Characteristics 70 2.0 Power on time [100µs] Shutdown time [µs] 60 50 40 30 1.5 1.0 0.5 20 10 0.5 1 1.5 2 2.5 3 Ctimer [nF] 3.5 4 0.0 4.5 Fig. 6. Shutdown Time vs. Ctimer Characteristics – 15 – 0 2 4 6 Cap_Z [nF] 8 10 Fig. 7. Power on Reset Time vs. Cap_Z Characteristics (Rseries = 10kΩ) CXB1549Q 100 IQ/IDRVMON (A) 3.14V IQ/IDRVMON (A) 3.3V IQ/IDRVMON (A) 3.46V 80 IQ/IDRVMON 60 40 20 0 0 5 10 15 20 25 RADJ [kΩ] Fig. 8. Ratio of Modulation Current (IQ)/Modulation Monitor Current (IDRVMON) vs. Rdrv Characteristics (Electrical) 60 IQ/Imon –40°C 3.3V IQ/Imon 0°C 3.3V IQ/Imon 27°C 3.3V IQ/Imon 85°C 3.3V IQ/Imon 55 50 45 40 0 1 2 3 4 5 6 7 8 RADJ [kΩ] Fig. 9. Ratio of Modulation Current (IQ)/Modulation Monitor Current (IDRVMON) vs. Rdrv Characteristics (Temperature) – 16 – CXB1549Q VCC = 0V VEE = –3.3V RL = 25Ω Ta = 27°C IQ = 30mA Single input Pattern = PRBS223 – 1 Data Rate 1.25Gbps Ch.1 :150mV/div, Offset: –300mV Bandwidth: 20.0GHz Time Base : 200ps/div Fig. 10. Electrical Output Waveform 2 VCC = 0V VEE = –3.3V FP – LD (λ = 1330nm) Ta = 27°C Single Input Pattern = PRBS223 – 1 Data Rate 1.06Gbps Filter (Cut Off 700Mbps) Mask: FC1063 1 3 Ch.2 :5.0mV/div, Offset: 12.8mV Bandwidth: 12.4GHz Time Base:200ps/div Fig. 11. Optical Output Waveform – 17 – CXB1549Q CXB1549Q PIN# PIN NAME PIN# PIN NAME 1 VCC4 21 VEE2 2 VEE4 22 DB 3 BiasAdj 23 D 4 SBias 24 VCC2 5 Bias 25 VBB 6 VEE5 26 Indicate 7 Q 27 Tset 8 QBX 28 RSB 9 VEE1 29 RS 10 VEE1 30 LDAlmB 11 VCC1 31 LDAlm 12 VEE1 32 SDN 13 DrvMon 33 SDNB 14 DrvAdj 34 VREF 15 CompA 35 TEST_PIN 16 CompB 36 VCC3 17 Timer 37 CapZ 18 NC 38 VEE3 19 TM 39 APCOut 20 ADCDis 40 RsetPD – 18 – CXB1549Q Package Outline Unit: mm 40PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 9.0 ± 0.4 + 0.4 7.0 – 0.1 0.1 21 30 20 31 A 11 40 1 + 0.15 0.3 – 0.1 0.65 10 0.24 M 0° to 10° 0.5 ± 0.2 (8.0) + 0.15 0.1 – 0.1 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-40P-L01 LEAD TREATMENT SOLDER / PALLADIUM PLATING EIAJ CODE QFP040-P-0707 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 19 –