CD4029BMS CMOS Presettable Up/Down Counter December 1992 Features Description • High-Voltage Type (20V Rating) CD4029BMS consists of a four-stage binary or BCD-decade up/ down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. • Medium Speed Operation: 8MHz (Typ.) at CL = 50pF and VDD - VSS = 10V • Multi-Package Parallel Clocking for Synchronous High Speed Output Response or Ripple Clocking for Slow Clock Input Rise and Fall Times • “Preset Enable” and Individual “Jam” Inputs Provided • Binary or Decade Up/Down Counting • BCD Outputs in Decade Mode • 100% Tested for Maximum Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device’s Applications • Programmable Binary and Decade Counting/Frequency Synthesizers-BCD Output • Analog to Digital and Digital to Analog Conversion • Up/Down Binary Counting • Difference Counting • Magnitude and Sign Generation A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRE-SET ENABLE signals are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRY-OUT signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS when not in use. Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallelclocking or a ripple-clocking arrangement as shown in Figure 17. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times. The CD4029BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W • Up/Down Decade Counting Functional Diagram Pinout CD4029BMS TOP VIEW PRESET ENABLE 1 Q4 2 15 CLOCK 14 Q3 JAM 1 4 13 JAM 3 CARRY IN 5 12 JAM 2 CARRY OUT 7 VSS 8 1 CARRY IN 1 (CLOCK ENABLE) 5 16 VDD JAM 4 3 Q1 6 JAM INPUTS PRESET ENABLE BINARY/ DECADE 9 2 3 4 12 13 3 4 VDD 16 6 Q1 11 Q2 14 11 Q2 Q3 UP/DOWN 10 10 UP/DOWN 2 9 BINARY/DECADE CLOCK 15 Q4 7 8 VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-798 BUFFERED OUTPUTS CARRY OUT File Number 3304 Specifications CD4029BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 - 10 µA +125oC - 1000 µA 3 -55oC - 10 µA 1 +25o C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 1 -55oC VDD = 18V MAX 2 oC 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-799 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4029BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock To Q Output SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Preset Enable To Q TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND 9 10, 11 9 10, 11 Propagation Delay Preset Enable To CarryOut TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND Propagation Delay Carry-In To Carry-Out TPHL5 TPLH5 VDD = 5V, VIN = VDD or GND TTHL TTLH VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency 9 10, 11 Propagation Delay Clock To Carry Out Transition Time Q Output GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC MIN MAX UNITS - 500 ns - 675 ns - 560 ns - 756 ns - 470 ns - 635 ns - 640 ns - 864 ns 9 +25oC - 340 ns 10, 11 +125oC, -55oC - 459 ns 9 +25oC - 200 ns - 270 ns 2 - MHz 1.48 - MHz MIN MAX UNITS µA 10, 11 FCL +25oC LIMITS 9 10, 11 +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) IOL10 IOL15 IOH5A VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 7-800 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA Specifications CD4029BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) SYMBOL IOH5B CONDITIONS VDD = 5V, VOUT = 2.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -1.15 mA -55 C - -2.0 mA +125oC - -0.9 mA - -2.6 mA o Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 -55 Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 oC +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V Propagation Delay Q Output TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 240 ns VDD = 15V 1, 2, 3 +25oC - 180 ns Propagation Delay Carry Output TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 260 ns 1, 2, 3 +25oC - 190 ns Propagation Delay Preset Enable To Q TPHL3 TPLH3 VDD = 15V o VDD = 10V 1, 2, 3 +25 C - 200 ns VDD = 15V 1, 2, 3 +25oC - 160 ns 1, 2, 3 +25oC - 290 ns oC - 210 ns Propagation Delay Preset Enable To CarryOut TPHL4 TPLH4 VDD = 10V VDD = 15V 1, 2, 3 +25 Propagation Delay Carry In To Carry Out TPHL5 TPLH5 VDD = 10V 1, 2, 3 +25oC - 140 ns VDD = 15V 1, 2, 3 +25oC - 100 ns ns Transition Time Maximum Clock Input Frequency Minimum Data Setup Time Note 4 TTHL TTLH VDD = 10V FCL TS 1, 2, 3 +25 C - 100 VDD = 15V 1, 2, 3 +25 oC - 80 ns VDD = 10V 1, 2, 3 +25oC 4 - MHz VDD = 15V 1, 2, 3 +25oC 5.5 - MHz VDD = 5V 1, 2, 3 +25oC - 340 ns VDD = 10V 1, 2, 3 +25oC - 140 ns 1, 2, 3 +25 oC - 100 ns VDD = 5V 1, 2, 3 +25oC - 15 µs VDD = 10V 1, 2, 3 +25oC - 15 µs 1, 2, 3 +25oC - 15 µs VDD = 5V 1, 2, 3 +25oC - 180 ns VDD = 10V 1, 2, 3 +25oC - 90 ns VDD = 15V Clock Rise And Fall Time Note 5 TRCL TFCL VDD = 15V Minimum Clock Pulse Width TW Minimum Carry In Setup Time Note 6 TS Minimum Carry Input Hold Time Note 6 TH Minimum Preset Enable Removal Time Note 4 VDD = 15V 1, 2, 3 +25oC - 60 ns VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 70 ns VDD = 15V 1, 2, 3 +25oC - 60 ns VDD = 5V 1, 2, 3 +25oC - 50 ns 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 25 ns VDD = 5V 1, 2, 3 +25oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 110 ns 1, 2, 3 +25oC - 80 ns VDD = 10V TREM o VDD = 15V 7-801 Specifications CD4029BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Preset Enable Pulse Width Input Capacitance SYMBOL TW CONDITIONS VDD = 5V CIN NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC - 130 ns o VDD = 10V 1, 2, 3 +25 C - 70 ns VDD = 15V 1, 2, 3 +25oC - 50 ns oC - 7.5 pF Any Input 1, 2 +25 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge. 5. If more than one unit is cascaded in the parallel clocked application, tr CL should be made ≤ the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load. This measurement was made with a decoupling capacitor (>1µF) between VDD and VSS. 6. From Carry In to Clock Edge. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VSS = 0V, IDD = 10µA 1, 4 VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND MAX UNITS - 25 µA -2.8 -0.2 V - ±1 V +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns 3. See Table 2 for +25oC limit. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-802 MIN Specifications CD4029BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 2, 6, 7, 11, 14 1, 3 - 5, 8 - 10, 12, 13, 15 16 Static Burn-In 2 Note 1 2, 6, 7, 11, 14 8 1, 3 - 5, 9, 10, 12, 13, 15, 16 Dynamic BurnIn Note 1 - 1, 3 - 5, 8, 12, 13 9, 10, 16 2, 6, 7, 11, 14 8 1, 3 - 5, 9, 10, 12, 13, 15, 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 2, 6, 7, 11, 14 15 - NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-803 BINARY/ DECADE * 12 J2 Logic Diagram * * 4 J1 * 13 J3 3 J4 9 * PRESET ENABLE 1 * CARRY IN * 5 PE J PE J PE J PE J TE1 Q1 TE2 Q2 TE3 Q3 TE4 Q4 F/F1 F/F2 F/F3 F/F4 CLOCK ENABLE Q1 Q2 CL Q3 CL 7 CARRY OUT Q4 CL CL UP/DOWN 7-804 CD4029BMS * 10 CLOCK * 15 6 Q2 11 Q2 14 Q3 2 Q4 TRUTH TABLE VDD FUNCTION TABLE CONTROL INPUT LOGIC LEVEL 1 BIN/DEC (B/D) 1 0 Binary Count Decade Count Q Q UP/DOWN (U/D) 1 0 Up Count Down Count 1 1 0 Preset Enable (PE) 1 0 Jam In No Jam X Q Q 1 No Counter Advance at POS Clock Transition Advance Counter at POS Clock Transition CLOCK TE PE J Q Q X X 0 0 0 0 1 X X 0 1 1 *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS PE J TE Q Q X NC CARRY IN (CI) (CLOCK ENABLE) X 1 X = Don’t Care FIGURE 1. X Q Q NC 0 ACTION CD4029BMS AMBIENT TEMPERATURE (TA) = +25oC 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 15 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10 10V 7.5 5 2.5 5V 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 -10 -15V -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) TRANSITION TIME (tTHL, tTLH) (ns) 200 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (Q OUTPUT) 7-805 CD4029BMS Typical Performance Characteristics (Continued) POWER DISSIPATION (PD) (µW) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 105 AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD) = 5V 300 200 10V 100 15V 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 104 10V 8 6 4 2 103 8 6 10V 5V 4 2 102 8 6 4 CL = 50pF CL = 15pF 2 AMBIENT TEMPERATURE (TA) = +25oC 10 0 20 40 60 80 2 100 4 68 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CARRY OUTPUT) 2 4 6 8 2 4 6 8 2 2 4 6 8 4 6 8 10 102 103 104 CLOCKFREQUENCY (fCL) (kHz) 1 FIGURE 9. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY Timing Diagrams CLOCK (CL) CARRY IN (CL ENABLE) UP/DOWN BINARY/ DECADE PRESET ENABLE J1 J2 J3 J4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 5 6 7 8 9 10 11 12 13 14 15 9 The CD4029BMS CLOCK and UP/DOWN inputs are used directly in most applications. In applications where CLOCK UP and CLOCK DOWN inputs are provided, conversion to the CD4029BMS CLOCK and UP/DOWN inputs can easily be realized by use of the circuit in Figure 11. CD4029BMS changes count on positive transitions of CLOCK UP or CLOCK DOWN inputs. For the gate configuration in Figure 12, when counting up the CLOCK DOWN input must be maintained high and conversely when counting down the CLOCK UP input must be maintained high. 8 7 6 5 4 3 2 1 0 0 15 “CLOCK UP” “UP/DOWN” VDD “CLOCK DOWN” “CLOCK” 1 CD4011 QUAD 2 INPUT NAND GATE FIGURE 11. CONVERSION OF CLOCK UP, CLOCK DOWN INPUT SIGNALS TO CLOCK AND UP/DOWN INPUT SIGNALS 7-806 CD4029BMS Timing Diagrams (Continued) CLOCK (CL) CARRY IN (CL ENABLE) UP/DOWN BINARY/ DECADE PRESET ENABLE J1 J2 J3 J4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 8 7 FIGURE 12. TIMING DIAGRAM-DECADE MODE “PARALLEL CLOCKING” UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 CI CI CI B/D CD4029 CO CL Q1 Q2 Q3 Q4 CD4029 B/D CO CL Q1 Q2 Q3 Q4 B/D CD4029 CO * CL Q1 Q2 Q3 Q4 CLOCK BINARY/ DECADE *CARRY OUT LINES AT THE 2ND, 3RD, ETC, STAGES MAY HAVE A NEGATIVE-GOING GLITCH PULSE RESULTING FROM DIFFERENTIAL DELAYS OF DIFFERENT CD4029BMS IC’S. THESE NEGATIVE GOING GLITCHES DO NOT AFFECT PROPER CD4029BMS OPERATION. HOWEVER, IF THE CARRY OUT SIGNALS ARE USED TO TRIGGER OTHER EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF’S OR COUNTERS, THE CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL USING A 2-INPUT OR GATE SUCH AS CD4071BMS. FIGURE 13. CASCADING COUNTER PACKAGES All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 807 CD4029BMS Timing Diagrams (Continued) “RIPPLE CLOCKING” UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 CI CI CI B/D CD4029 CO CL Q1 Q2 Q3 Q4 B/D CLOCK CD4029 CO CL Q1 Q2 Q3 Q4 CD4029 B/D 1/4 CD4071B RIPPLE CLOCKING MODE: THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH. FOR CASCADING COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE, THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CONNECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH CI GROUNDED. FIGURE 13. CASCADING COUNTER PACKAGES (Continued) Chip Dimensions and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-808 CL Q1 Q2 Q3 Q4 1/4 CD4071B BINARY/ DECADE CO