CD4510BMS, CD4516BMS Data Sheet December 1992 File Number CMOS Presettable Up/Down Counters Features CD4510BMS Presettable BCD Up/Down Counter and the CD4516BMS Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. The CD4510BMS will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. • High Voltage Types (20V Rating) If the CARRY IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY OUT of a less significant stage to the CARRY IN of a more significant stage. The CD4510BMS and CD4516BMS can be cascaded in the ripple mode by connecting the CARRY OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. (See Figures 13, 14.) These devices are similar to types MC14510 and MC14516. The CD4510BMS and CD4516BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD4510B Only *H4W †H45 *FBF †H1F H6W †CD4516B Only 3338 • CD4510BMS - BCD Type • CD4516BMS - Binary Type • Medium Speed Operation - fCL = 8MHz Typ. at 10V • Synchronous Internal Carry Propagation • Reset and Preset Capability • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized Symmetrical Output Characteristics • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Up/Down Difference Counting • Multistage Synchronous Counting • Multistage Ripple Counting • Synchronous Frequency Dividers Pinout Functional Diagram CD4510BMS, CD4516BMS TOP VIEW PRESET ENABLE PRESET ENABLE 1 P1 16 VDD 1 P2 Q4 2 15 CLOCK P4 3 14 Q3 P1 4 13 P3 CARRY IN 5 12 P2 Q1 6 11 Q2 CARRY OUT 7 10 UP/DOWN VSS 8 P3 P4 CLOCK 9 RESET UP/DOWN CARRY IN 4 6 12 11 13 14 3 2 1 Q2 Q3 Q4 15 10 5 7 9 RESET Q1 CARRY OUT VDD = 16 VSS = 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 CD4510BMS, CD4516BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance. . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current Input Leakage Current IIL IIH VIN = VDD or GND VIN = VDD or GND LIMITS GROUP A SUBGROUPS VDD = 20 VDD = 18V Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V 1 +25oC 0.53 - mA 1 +25oC 1.4 - mA Output Current (Sink) Output Current (Sink) IOL5 IOL10 VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA Output Current (Source) Output Current (Source) IOH5B IOH10 VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V 7 +25oC P Threshold Voltage Functional VPTH F VSS = 0V, IDD = 10µA VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 2 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. CD4510BMS, CD4516BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay Clock to Q Output TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay Preset or Reset to Q TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Clock to Carry Out TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Propagation Delay Carry In to Carry Out Propagation Delay Preset or Reset to Carry Out Transition Time Maximum Clock Input Frequency TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND TPHL5 TPLH5 VDD = 5V, VIN = VDD or GND (Note 3) TTHL TTLH VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9 +25oC - 400 ns 10, 11 +125oC, -55oC - 540 ns 9 +25oC - 420 ns 10, 11 +125oC, -55oC - 567 ns 9 +25oC - 480 ns 10, 11 +125oC, -55oC - 648 ns 9 +25oC - 250 ns 10, 11 +125oC, -55oC - 338 ns 9 +25oC - 640 ns 10, 11 +125oC, -55oC - 864 ns 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns 9 +25oC 2 - MHz 10, 11 +125oC, -55oC 1.48 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. Reset to Carry Out (TPLH) only. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 2 -55oC, +25oC µA 1, 2 1, 2 - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA -55oC, +25oC - 10 µA +125oC - 600 µA - 50 mV Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, 55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, 55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) IOL10 IOL15 IOH5A 3 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA CD4510BMS, CD4516BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) Output Current (Source) Output Current (Source) SYMBOL IOH5B IOH10 IOH15 CONDITIONS VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA - 3 V 1, 2 1, 2 Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 55oC Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, 55oC +7 - V Propagation Delay Clock to Q Output TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 150 ns Propagation Delay Preset or Reset to Q TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 210 ns VDD = 15V 1, 2, 3 +25oC - 160 ns Propagation Delay Clock to Carry Out TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC - 240 ns 1, 2, 3 +25oC - 180 ns VDD = 10V 1, 2, 3 +25oC - 120 ns VDD = 15V 1, 2, 3 +25oC - 100 ns 1, 2, 3, 4 +25oC - 320 ns - 250 ns - 100 ns Propagation Delay Carry In to Carry Out Propagation Delay Preset or Reset to Carry Out Transition Time Maximum Clock Input Frequency Minimum Hold Time Preset Enable to JN TPHL4 TPLH4 VDD = 15V TPHL5 TPLH5 VDD = 10V VDD = 15V 1, 2, 3, 4 +25oC TTLH TTHL VDD = 10V 1, 2, 3 +25oC VDD = 15V 1, 2, 3 +25oC - 80 ns FCL VDD = 10V 1, 2 +25oC 4 - MHz VDD = 15V 1, 2 +25oC 5.5 - MHz VDD = 5V 1, 2, 3 +25oC - 70 ns VDD = 10V 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 40 ns VDD = 5V 1, 2, 3 +25oC - 25 ns VDD = 10V 1, 2, 3 +25oC - 10 ns VDD = 15V 1, 2, 3 +25oC - 10 ns VDD = 5V 1, 2, 3 +25oC - 60 ns 1, 2, 3 +25oC - 30 ns VDD = 15V 1, 2, 3 +25oC - 30 ns VDD = 5V 1, 2, 3 +25oC - 30 ns 1, 2, 3 +25oC - 30 ns 1, 2, 3 +25oC - 30 ns 1, 2 +25oC - 7.5 pF TH VDD = 15V Minimum Data Setup Time Preset Enable to JN Minimum Data Hold Time Clock to Carry In Minimum Clock Hold Time Clock to Up/Down TS TH VDD = 10V TH VDD = 10V VDD = 15V Input Capacitance CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Reset to Carry Out (TPLH) only. 4 CD4510BMS, CD4516BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Supply Current IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 5 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 CD4510BMS, CD4516BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 2, 6, 7, 11, 14 1, 3-5, 8-10, 12, 13, 15 16 Static Burn-In 2 (Note 1) 2, 6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13, 15, 16 Dynamic BurnIn (Note 1) - 1, 3, 4, 8, 9, 12, 13 10, 16 2, 6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13, 15, 16 9V ± -0.5V 50kHz 25kHz 2, 6, 7, 11, 14 15 5 CD4510BMS Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagrams P1* 4 RESET* PRESET* ENABLE CLOCK* CARRY OUT P2* 12 Q1 6 Q4 2 1 P P P P PE Q PE Q PE Q PE Q C C C C 15 7 Q T Q1 UP/DOWN* P4* 3 Q3 14 9 T CARRY IN* P3* 13 Q2 11 Q Q2 T Q Q2 Q3 T Q3 Q Q4 5 10 U/D U/D Q1 U/D VDD * VSS U/D Q3 Q4 Q2 Q4 ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK FIGURE 1. CD4510BMS 6 U/D Q3 U/D U/D Q2 Q2 Q4 U/D Q3 Q2 Q3 Q2 U/D Q3 Q4 Q4 CD4510BMS, CD4516BMS Logic Diagrams (Continued) P1* 4 RESET* PRESET* ENABLE CLOCK* CARRY OUT P2* 12 Q1 6 Q4 2 1 P P P P PE Q PE Q PE Q PE Q C C C C 15 7 Q T Q1 UP/DOWN* P4* 3 Q3 14 9 T CARRY IN* P3* 13 Q2 11 Q Q2 T Q Q2 Q3 T Q3 5 10 U/D U/D Q1 U/D Q3 U/D Q3 Q2 Q4 Q2 Q4 VDD * VSS U/D U/D Q2 Q2 ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK FIGURE 2. CD4516BMS TRUTH TABLE CL CI U/D PE R X 1 X 0 0 NO COUNT 0 1 0 0 COUNT UP 0 0 0 0 COUNT DOWN X X X 1 0 PRESET X X X X 1 RESET X = DON’T CARE 7 ACTION U/D Q3 Q2 Q2 U/D Q3 Q Q4 Q4 CD4510BMS, CD4516BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS TRANSITION TIME (tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE 8 0 AMBIENT TEMPERATURE (TA) = +25oC 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V -15 FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPLH, tPHL) (ns) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics AMBIENT TEMPERATURE (TA) = +25oC 250 200 SUPPLY VOLTAGE (VDD) = 5V 150 10V 100 15V 50 0 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE FOR CLOCK-TO-Q OUTPUTS CD4510BMS, CD4516BMS (Continued) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50pF 15 POWER DISSIPATION PER GATE (PD) (µW) MAXIMUM CLOCK INPUT FREQUENCY (fCL MAX) (MHz) Typical Performance Characteristics 10 5 104 AMBIENT TEMPERATURE (TA) 8 = +25oC 6 4 tr, tf = 20ns 2 103 SUPPLY VOLTS (VDD) = 15V 10V 8 6 4 10V 5V 2 102 8 6 4 CL = 50pF 2 CL = 15pF 10 0 5 10 15 2 20 4 68 01 SUPPLY VOLTAGE (VDD) FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs SUPPLY VOLTAGE 2 1 4 68 2 4 68 2 4 68 2 4 68 10 102 103 INPUT FREQUENCY (fCL) (kHz) FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs FREQUENCY Test Circuit and Waveform 100µF ID 1 16 2 15 3 14 4 13 500µF PULSE GENERATOR 20ns 90% CL CL CL CL 5 12 6 11 7 10 8 9 20ns VDD 50% 10% VARIABLE WIDTH VSS CL FIGURE 11. POWER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM Acquisition System SAMPLE AND HOLD AMPLIFIER ANALOG DATA INPUTS 16 CHANNEL MULTIPLEXER CD4067 START CLOCK CONVERSION LOGIC SELECT INPUTS Q1 PRESET INPUTS Q4 CD4516BMS CLOCK 10 BIT A/D CONVERTER PARALLEL DATA OUTPUTS END NOTE: This acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the CD4516BMS. PRESET ENABLE FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM 9 104 CD4510BMS, CD4516BMS Timing Diagrams CLOCK CARRY IN UP/DOWN RESET PE P1 P2 P3 P4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0 FIGURE 13. CD4510BMS CLOCK CARRY IN UP/DOWN RESET PE P1 P2 P3 VDD VSS P4 Q1 Q2 Q3 Q4 CARRY OUT COUNT 5 6 7 8 9 10 11 12 13 14 15 9 8 7 FIGURE 14. CD4516BMS 10 6 5 4 3 2 1 0 0 15 0 CD4510BMS, CD4516BMS PARALLEL CLOCKING UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 CI CD4510/16BMS CO CI CD4510/16BMS CO CI CD4510/16BMS CO R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 * CLOCK RESET * CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edgesensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as CD4071BMS. RIPPLE CLOCKING UP/DOWN PRESET ENABLE UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 CI CD4510/16BMS CO CI CD4510/16BMS CO CI CD4510/16BMS CO R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 CLOCK 1/4 CD4071B RESET Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded. FIGURE 15. CASCADING COUNTER PACKAGES All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 11 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029