DATASHEET

Radiation Hardened Adjustable Positive Voltage
Regulator
HS-117RH, HS-117EH
Features
The radiation hardened HS-117RH and HS-117EH are
adjustable positive voltage linear regulators capable of
operating with input voltages up to 40VDC. The HS-117EH
encompasses all of the production testing of the HS-117RH
and additionally is tested in the Intersil Enhanced Low Dose
Rate Sensitivity (ELDRS) product manufacturing flow. The
output voltage is adjustable from 1.25V to 37V with two
external resistors. The device is capable of sourcing from 5mA
to 1.25A max (0.5A max for the TO-39 package). Current
protection is provided by the on-chip thermal shutdown and
output current limiting circuitry.
• Electrically screened to DLA SMD # 5962-99547
The Intersil HS-117 has advantages over other industry
standard types, in that circuitry is incorporated to minimize the
effects of radiation and temperature on device stability.
Constructed in Intersil’s dielectrically isolated Rad Hard Silicon
Gate (RSG) process, the HS-117RH and HS-117EH are immune
to single event latch-up and has been specifically designed to
provide highly reliable performance in harsh radiation
environments.
Applications
• Superior temperature stability
• Overcurrent and Over-temperature protection
• Wide input voltage range . . . . . . . . . . . . . . . . . . 4.25V to 40V
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• QML Qualified per MIL-PRF-38535 requirements
• Radiation environment
- SEL/SEB LETTH (VS = ±20V). . . . . . . . . .87.4 MeV•cm2/mg
- Total Dose, High Dose Rate . . . . . . . . . . . . . . . 300krad(Si)
- Total Dose, Low Dose Rate . . . . . . . . . . . . . . . 100krad(Si)*
* Product capability established by initial characterization. The
EH version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
Related Literature
• TID, “Total Dose Testing of the HS117 Linear Regulator”
• SEE, “SEE Testing of the HS117 Linear Regulator”
• ELDRS, “Low Dose Testing of HS117 to 100krad(Si)”
• Adjustable Voltage Regulators
• Adjustable Current Regulators
0.30
HS-117EH
VIN
IN
C1
VOUT
OUT
OUTPUT
ADJUST
R1
C2
VOUT SHIFT (%)
0.25
0.20
0.15
HIGH DOSE RATE
0.10 LOW DOSE RATE
0.05
R2
0.00
-0.05
0
VOUT = VREF (1+R2/R1) + IADJ R2
FIGURE 1. TYPICAL APPLICATION
March 25, 2014
FN4560.10
1
50
100
150
krad(Si)
200
250
300
FIGURE 2. VOUT SHIFT vs HIGH and LOW DOSE RATE RADIATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2001, 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-117RH, HS-117EH
Ordering Information
ORDERING SMD NUMBER
(Note 2)
INTERNAL MKTG. PART
NUMBER
TEMPERATURE RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
5962F9954702V9A
HS0-117EH-Q
-55 to +125
DIE
5962F9954701V9A
HS0-117RH-Q
-55 to +125
DIE
HS0-117RH/SAMPLE
HS0-117RH/SAMPLE
-55 to +125
DIE
5962F9954702VUC
HS2-117EH-Q (Note 1)
-55 to +125
3 Ld METAL CAN
T3.C
5962F9954701VUC
HS2-117RH-Q (Note 1)
-55 to +125
3 Ld METAL CAN
T3.C
5962F9954701QUC
HS2-117RH-8 (Note 1)
-55 to +125
3 Ld METAL CAN
T3.C
HS2-117RH/PROTO
HS2-117RH/PROTO (Note 1)
-55 to +125
3 Ld METAL CAN
T3.C
5962F9954702VYC
HSYE-117EH-Q (Note 1)
-55 to +125
3 PAD CLCC
J3.A
5962F9954701VYC
HSYE-117RH-Q (Note 1)
-55 to +125
3 PAD CLCC
J3.A
5962F9954701QYC
HSYE-117RH-8 (Note 1)
-55 to +125
3 PAD CLCC
J3.A
HSYE-117RH/PROTO
HSYE-117RH/PROTO (Note 1)
-55 to +125
3 PAD CLCC
J3.A
5962F9954701VXC
HS9S-117RH-Q (Note 1)
-55 to +125
3 Ld TO-257
T3.D
5962F9954701QXC
HS9S-117RH-8 (Note 1)
-55 to +125
3 Ld TO-257
T3.D
5962F9954702VXC
HS9S-117EH-Q (Note 1)
-55 to +125
3 Ld TO-257
T3.D
HS9S-117RH/PROTO
HS9S-117RH/PROTO (Note 1)
-55 to +125
3 Ld TO-257
T3.D
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table on page 2 must be used when ordering.
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FN4560.10
HS-117RH, HS-117EH
Pin Configurations
HSYE-117RH
(SMD.5 CLCC)
BOTTOM VIEW
HS2-117RH
(TO-39 CAN)
BOTTOM VIEW
ADJUST
2
2
3 OUT
IN 1
1 - ADJUST
2 - IN
3 - OUT
3
1
HS9S-117RH
(TO-257AA FLANGE MOUNT)
TOP VIEW
NOTE: No current JEDEC outline for the SMD.5 package. Refer to SMD
for package dimensions. The TO-257 is a totally isolated metal
package.
3
IN
2
OUT
1
ADJUST
Pin Descriptions
HS2-117RH
(TO-39)
HS9S-117RH
(TO-257AA)
HSYE-117RH
(SMD.5 CLCC)
PIN NAME
1
3
2
IN
2
1
1
ADJUST
3
2
3
OUT
DESCRIPTION
Regulator Input
Voltage Adjust Feedback Input
Regulator Output
IN
ADJ
OUT
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March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Functional Block Diagram
IN
ADJUST
1.25V
OUT
Typical Applications
HS-117EH
VIN
HS-117EH
VOUT
OUT
OUTPUT
IN
30µF
R1
ADJUST
VIN
OUT
OUTPUT
IN
30µF
30µF
R1
ADJUST
CONSTANT IOUT
R2
30µF
VOUT = VREF (1+ R2/R1) + IADJ*R2
IOUT = VREF / R1
FIGURE 3. RESISTOR ADJUSTED OUTPUT VOLTAGE
FIGURE 4. CONSTANT CURRENT REGULATOR
HS-117EH
VIN
IN
30µF
HS-117EH
VOUT
OUT
OUTPUT
R1
ADJUST
Q1
HIGH = SHUTDOWN
0V
30µF
VIN
R2
R3
In shutdown VOUT = VREF
VOUT
OUT
OUTPUT
IN
30µF
R2
30µF
R1
ADJUST
R4
R3
Q2
a
Q1
b
R5
R6
FIGURE 5. REGULATOR SHUTDOWN
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FIGURE 6. FOUR DIGITALLY PROGRAMMED OUTPUT VOLTAGES
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Absolute Maximum Ratings
Thermal Information
Input to Output Voltage Differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Input to Output Voltage Differential (Note 5) . . . . . . . . . . . . . . . . . . . . . 40V
Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5A
Thermal Resistance (Typical)
JA (°C/W)
TO-39 (Notes 3, 4, 6) . . . . . . . . . . . . . . . . . . . .
125
TO-257AA (Notes 3, 4, 6) . . . . . . . . . . . . . . . . .
26
SMD.5 (Notes 3, 4, 6). . . . . . . . . . . . . . . . . . . .
42
Maximum Power Dissipation TC = +25°C
HS2-117 (TO-39 Can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8W
HS9S-117 (TO-257AA Flange Mount) . . . . . . . . . . . . . . . . . . . . . . . . . . 50W
HSYE-117 (SMD.5 CLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.5W
Maximum Power Dissipation TC = +100°C (Note 6)
HS2-117 (TO-39 Can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3W
HS9S-117 (TO-257AA Flange Mount) . . . . . . . . . . . . . . . . . . . . . . . . . . 20W
HSYE-117 (SMD.5 CLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11W
JC (°C/W)
15
2.5
4.5
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX) . . . . . . . . . . . . . . . . . . . . .+175°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-55°C to +125°C
Input Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25V to 40V
Output Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25V to 37V
Minimum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (HBM) (Tested per MIL-PRF-883 3015.7) . . . 1500V
Machine Model (MM) (Tested per EIA/JESD22-A115-A) . . . . . . . . . 350V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. The maximum supply limit specified is for operation in a heavy ion environment at an LET = 87.4MeV*cm2/mg.
6. The linear derating factor for TO-39 package is 0.067 W/°C, for TO-257AA package is 0.4 W/°C, for the SMD.5 package is 0.22 W/°C
Electrical Specifications
-55°C to +125°C.
PARAMETER
VDIFF = 3V, TA = 25°C, unless otherwise noted. Boldface limits apply across the operating temperature range,
DESCRIPTION
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
VREF
Reference Voltage
VDIFF = 3V, VDIFF = 40V,
5.0mA ≤ IOUT ≤ 5.5mA
1.20
1.255
1.30
V
RLINE
Line Regulation
VREF = VOUT - VADJ, 3V ≤ VDIFF ≤ 40V,
5.0mA ≤ IOUT ≤ 5.5mA
-0.02
0.005
0.02
%
RLOAD
Load Regulation
VDIFF = 3V, 5mA ≤ IOUT ≤ 1.25A
TO-257AA and SMD.5 packages only
-1.5
-0.1
1.5
%
VDIFF = 3V, 5mA ≤ IOUT ≤ 500mA
TO-39 package
-1.5
-0.8
1.5
%
64
100
µA
2.36
6
µA
IADJ
Adjust Pin Current
VDIFF = 3V, VDIFF = 40V,
5.0mA ≤ IOUT ≤ 5.5mA
dIADJ
Adjust Pin Current Change
3V IADJ - 40V IADJ
5.0mA ≤ IOUT ≤ 5.5mA
IOUT
Maximum Output Current
TO-257AA and SMD.5 packages only
TO-39 package
TON
VIN Applied to VOUT Turn-on
Isc
Max. Output Short Circuit Current Limit
-6
1.25
A
0.5
A
0.2
VOUT = 0V
3
A
°C
OT
Over-temperature Shutdown
150
OT_HYS
Over-temperature Hysteresis
20
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5
ms
175
°C
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Post Radiation Electrical Specifications VDIFF = 3V, TA = +25°C, unless otherwise noted. Boldface limits apply over a total
ionizing dose of 300krad(Si) with exposure at a high dose rate of 50 to 300krad(Si)/s; or over a total ionizing dose of 50krad(Si) with exposure a low
dose rate of <10mrad(Si)/s.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 7)
MAX
(Note 7)
UNITS
VREF
Reference Voltage
VDIFF = 3V, VDIFF = 40V,
5.0mA ≤ IOUT ≤ 5.5mA
1.20
1.30
V
RLINE
Line Regulation
VREF = VOUT-VADJ, 3V ≤ VDIFF ≤ 40V,
5.0mA ≤ IOUT ≤ 5.5mA
-0.02
0.02
%
RLOAD
Load Regulation
VDIFF = 3V, 5mA ≤ IOUT ≤ 1.25A
TO-257AA and SMD.5 packages only
-1.5
1.5
%
VDIFF = 3V, 5mA ≤ IOUT ≤ 500mA
TO-39 package
-1.5
1.5
%
100
µA
6
µA
IADJ
Adjust Pin Current
VDIFF = 3V, VDIFF = 40V,
5.0mA ≤ IOUT ≤ 5.5mA
dIADJ
Adjust Pin Current Change
3V IADJ - 40V IADJ
5.0mA ≤ IOUT ≤ 5.5mA
IOUT
Output Current
TO-257AA and SMD.5 packages only
TO-39 package
-6
1.25
A
0.5
A
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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FN4560.10
HS-117RH, HS-117EH
Post Radiation Characteristics This data is a typical mean test data post total dose radiation exposure at both a low dose rate (LDR)
of <10mrad(Si)/s to 100krad(Si) and at a high dose rate (HDR) of 50 to 300rad(Si)/s to 300krad(Si). This data is intended to show typical parameter
shifts due to low dose rate radiation. These are not limits nor are they guaranteed.
0.009
1.259
0.008
VIN = 3V
VIN = 40
1.257
LINE REGULATION (%)
REFERENCE VOLTAGE (V)
1.258 LOW DOSE RATE
VIN = 3V
1.256
HIGH DOSE RATE
1.255
VIN = 40
1.254
1.253
0.004
0.003
1.252
0.001
50
100
150
krad(Si)
200
250
0
300
FIGURE 7. REFERENCE VOLTAGE vs RADIATION
0.32
68
ADJUST PIN CURRENT (µA)
69
HIGH DOSE RATE
0.24
0.20
0.16
LOW DOSE RATE
0.12
0.08
0.04
0
0
50
100
150
krad(Si)
200
250
300
FIGURE 8. LINE REGULATION (3V ≤ VDIFF ≤ 40V) vs RADIATION
0.36
0.28
HIGH DOSE RATE
0.005
0.002
0
LOW DOSE RATE
0.006
1.252
1.251
LOAD REGULATION (%)
0.007
67
LOW DOSE RATE
66
VIN = 3V
VIN = 40
65
VIN = 40V
64
63
VIN = 3V
HIGH DOSE RATE
62
61
0
50
100
150
krad(Si)
200
250
300
FIGURE 9. LOAD REGULATION (IOUT 5mA to 1.25A) vs RADIATION
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60
0
50
100
150
krad(Si)
200
250
300
FIGURE 10. ADJUST PIN CURRENT vs RADIATION
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Typical Performance Curves
1.270
1.253
1.265
1.252
1.251
VIN = 40V
1.250
1.255
VREF (V)
VREF at 5mA (V)
1.260
VIN = 3V
1.250
1.245
1.249
1.248
1.247
1.240
1.246
1.235
1.245
1.244
1.230
-55
25
125
0.05 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
TEMPERATURE (°C)
1.3
IOUT (A)
FIGURE 12. VREF vs OUTPUT CURRENT at TA = +25°C
FIGURE 11. VREF vs TEMPERATURE
75
0.010
70
IADJ (µA)
LINE REGULATION (%)
0.008
VIN = 40V
65
60
VIN = 3V
55
50
0.006
0.004
0.002
45
40
0.000
-55
25
125
-55
25
125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. IADJ vs TEMPERATURE
FIGURE 14. LINE REGULATION vs TEMPERATURE
0.0
4.50
4.00
IOUT = 5mA - 500mA
DROPOUT VOLTAGE (V)
LOAD REGULATION (%)
-0.2
-0.4
-0.6
-0.8
IOUT = 5mA - 1.25A
TA = +125°C
3.50
3.00
2.50
TA = +25°C
2.00
1.50
1.00
-1.0
0.50
-1.2
-55
25
125
TEMPERATURE (°C)
FIGURE 15. LOAD REGULATION vs TEMPERATURE
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0.20
0.40
0.60
0.80
1.00
1.20
1.40
IOUT (A)
FIGURE 16. DROPOUT VOLTAGE vs OUTPUT CURRENT, VIN = 12V
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FN4560.10
HS-117RH, HS-117EH
Typical Performance Curves (Continued)
VIN
VOUT
VIN
VOUT
FIGURE 17. POWER-ON VIN = 12V, VOUT = 5V, Rl = 10Ω
FIGURE 18. VIN = 30V, VOUT = 15V, IOUT 0 -1A STEP
VOUT
VOUT
IADJ
IADJ
IIN
IIN
FIGURE 19. SHORT CIRCUIT INTO OVER-TEMP PROTECTION
FIGURE 20. SHORT CIRCUIT RECOVERY
VOUT
VOUT
IADJ
IADJ
IIN
IIN
FIGURE 21. SHORT CIRCUIT CURRENT LIMIT DETAIL
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FIGURE 22. SHORT CIRCUIT OVER-TEMP PROTECTION DETAIL
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Functional Description
Performance and PCB Layout Considerations
Functional Overview
The radiation hardened HS-117RH, HS-117EH are adjustable
positive voltage linear regulators capable of operating with input
voltages up to 40 VDC. The output voltage is adjustable from
1.25V (VREF) to 37V with two external resistors. The device is
capable of sourcing from 5mA to 1.25APEAK (0.5APEAK for the
TO-39 can package). Dual mode protection is provided by the
on-chip +175oC thermal shutdown at output current limiting
circuitry.
The Intersil HS-117RH, HS-117EH has advantages over other
industry standard types, in that circuitry is incorporated to
minimize the effects of radiation and temperature on device
stability providing < 0.2% shifts in output voltage over
300krad(Si) of high dose rate (HDR) and 100krad(Si) of low dose
rate (LDR) gamma radiation.
Constructed with the Intersil dielectrically isolated Radiation
Hardened Silicon Gate (RSG) process, the HS-117RH and
HS-117EH are both immune to single event latch-up and have
been specifically designed to provide highly reliable performance
providing power in harsh radiation environments.
Output Voltage Adjustment
The HS-117 is an adjustable output voltage regulator operating
with a 1.25V reference voltage developed between the OUT and
ADJUST pins. The ADJ current (IADJ) is typically 64μA at +25°C
and 100μA maximum over temperature.
Linear regulators typically need a minimum current load for the
regulation amplifier feedback to maintain stability, and for the
HS-117 this minimum is 5mA. In order to ensure stability in all
situations, the minimum resistor between the VOUT and ADJ is
suggested to be 120 Ω.
Referring to Figure 1, the reference voltage is programmed to a
constant current source by resistor R1, and this current flows
through R2 to ground to set the output voltage, see Equation 1.
V OUT = 1.25  1 + R2  R1  + I ADJ R2
(EQ. 1)
In practical applications the R2 value is in the range of a few kΩ,
so that the IADJ x R2 contribution can be ignored in the VOUT
calculation; simplifying the VOUT calculation to the following:
V OUT = 1.25  1 + R2  R1 
(EQ. 2)
CURRENT LIMITING
The HS-117 has internal current limiting that will be activated
whenever the output current exceeds the lower limit of the
Maximum Output Current parameter shown in the “Electrical
Specifications” on page 5, (typically limiting to ~1.5A) to a
maximum limit of typically 3A in an output short circuit
condition.
In order to optimize load regulation performance, it is important
to implement Kelvin connections for the R1 and R2 resistors. In
practice, the R1 connection must be close to the OUT and
ADJUST pins. This is done to eliminate PCB trace resistance being
included in the constant current determination. In contrast, the
R2 to ground connection must be placed as near as possible to
the negative load pin to ensure that the voltage being delivered
to the load is as designed for by the choice of R1 and R2 values.
Ripple rejection can be improved by placing a 10μF capacitor
across the R2 resistor. At low output voltage, increasing this
capacitor value will further decrease output ripple.
External Bypass Capacitors
Input bypass capacitance is recommended to enhance regulator
stability if the device is located more than a few inches from its
power source. The input bypass capacitor (C1) should be
mounted with the shortest possible track length directly across
the regulator’s input and ground terminals. A 30μF tantalum
capacitor should be adequate for most applications. Frequency
compensation for the regulator is provided by the output
capacitor (C2) and is required to ensure output stability. A
minimum (C2) capacitance value of 30μF is recommended.
Higher values of output capacitance can be used to enhance loop
stability, transient response and output noise.
Thermal Considerations
The HS-117 has a thermal limiting circuit that is designed to
protect the regulator when the junction temperature is typically
> +150°C. The regulator output turns off and then on again as
the die cools. If the device is continuously operated in an
over-temperature condition, this feature provides protection from
catastrophic device damage due to accidental or prolonged
overheating.
The HS-117 is available in a TO-39 3 pin can, a TO-257AA flange
mount and a SMD.5 CLCC surface mount packages. These
packages represent a wide range of thermal resistance to the die
and thus a wide range of power dissipation (PD) capabilities.
Consult the “Thermal Information” on page 5 for the relevant
package thermal impedances. Also the “Absolute Maximum
Ratings” on page 5 lists the power dissipation limitations by
package.
When developing circuits using the HS-117, its thermal
performance and limitations should be tested in order to insure
acceptable performance. As with all tabbed packaged devices,
flange mounting to a thermal heat-sink is recommended for the
TO-257AA following best practices.
During a short circuit condition if the regulator's differential
voltage exceeds the Absolute Maximum Rating of 40V (e.g. VIN ≥
40V, VOUT = 0V), the device may be likely damaged.
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FN4560.10
HS-117RH, HS-117EH
T0-257AA Package
Characteristics
Die Characteristics
Die Dimensions
Weight of Packaged Device
2616µm x 2794µm (103mils x 110mils)
Thickness: 483µm ± 25µm (19mils ± 1mil)
4.50 Grams (Typical)
Interface Materials
Case Characteristics
Finish: Gold
Potential: Unbiased
GLASSIVATION
T0-39 Package Characteristics
Weight of Packaged Device
Type: PSG
Thickness: 8kÅ ± 1kÅ
TOP METALLIZATION
Type: Al/Cu/Si (98.75%/0.5%/0.75%)
Thickness: 16kÅ
0. 91 Grams (Typical)
Case Characteristics
BACKSIDE FINISH
Gold
Finish: Steel, Gold
Potential: Unbiased
Assembly Related Information
SMD.5 CLCC Package
Characteristics
SUBSTRATE POTENTIAL
Unbiased (DI)
Weight of Packaged Device
Additional Information
0.91 Grams (Typical)
WORST CASE CURRENT DENSITY
Case Characteristics
< 2 x 105 A/cm2
Finish: Gold, Ceramic
Potential: Unbiased
PROCESS
Dielectrically Isolated RH - Si-GATE
TRANSISTOR COUNT:
96
Metallization Mask Layout
VIN_2
OUT_1
ADJ
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VIN_1
OUT_2
VOUTK
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
TABLE 1. DIE LAYOUT X-Y COORDINATES (Notes: 8, 9)
PAD NAME
X
(µm)
Y
(µm)
dX
(µm)
dY
(µm)
VIN_1
1214
2191
514
257
VIN_2
14
2191
514
257
VOUT_1
14
934
514
257
ADJ
0
0
514
257
VOUTK
1361
14
514
257
VOUT_2
1214
934
514
257
NOTES:
8. Origin of coordinates is the centroid of pad ADJ.
9. Bond Pads sized for is 5mil diameter wire
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
March 25, 2014
FN4560.10
Updated “Ordering Information on page 2. Expanded content in datasheet from 3 to 15 pages.
Sept 4, 2012
FN4560.9
Added HS-117EH as Device # to datasheet (EH FGs already added to the Ordering Information table), making
this a 2-part datasheet: HS-117RH, HS-117EH.
Global search/change HS-117RH to HS-117RH, HS-117EH.
Dec 15, 2011
FN4560.8
Added parts to datasheet: HS2-117EH-Q, HS0-117EH-Q, HS9S-117EH-Q and HSYE-117EH-Q
Oct 10, 2003
FN4560.7
Revised datasheet includes a new date and file number.
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12
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Ceramic Leadless Chip Carrier Packages (CLCC)
J3.A
B
D
3 PAD HERMETIC SMD.5 PACKAGE
CERAMIC BOTTOM TERMINAL CHIP CARRIER
INCHES
E
A
TOP VIEW
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.110
0.124
2.79
3.15
3
A1
0.010
0.020
0.25
0.51
-
b
0.281
0.291
7.13
7.39
-
b1
0.220
0.230
5.58
5.84
-
b2
0.090
0.100
2.28
2.54
-
b3
0.115
0.125
2.92
3.18
-
D
0.395
0.405
10.03
10.28
-
D1
0.030
-
0.76
-
-
E
0.291
0.301
7.39
7.64
-
e
A1
A
C
1.91 BSC
-
NOTES:
1. Controlling dimensions are in inches (mm for reference only).
2. Dimensioning and tollorance per ANSI Y14.5M - 1982
SIDE VIEW
C
0.075 BSC
Rev. 2 1/14
(3 PLCS)
0.004
MILLIMETERS
3. The maximum “A” dimension is package height before being
solder dipped.
4. Patterned after MIL-STD-1835 CBCC1-N3 (C-B1) Note: Not
meeting the Mil-Std “A” min. dimension of 0.112
D1
b1
b3
(2 PLCS)
2
3
e (2 PLCS)
b
1
b2
0.014
M
(2 PLCS)
C A
BOTTOM VIEW
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13
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Metal Can Package
T3.C
REFERENCE
PLANE
3 LEAD TO-39 (TO-205) METAL CAN PACKAGE
A
Øb1
L1
e
ØD
ØD1
F
3
2
A
k
1
A
Øb
INCHES
e1


L2
L
BASE METAL
CL
k1
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.160
0.180
4.07
4.58
-
Øb
0.016
0.019
0.41
0.48
1
Øb1
0.016
0.021
0.41
0.53
1
Øb2
0.016
0.024
0.41
0.61
-
ØD
0.350
0.370
8.89
9.40
-
ØD1
0.315
0.335
8.00
8.51
-
e
LEAD FINISH
e1
F
Øb1
Øb2
SECTION A-A
MILLIMETERS
0.200 BSC
5.08 BSC
0.100 BSC
0.009
0.050
-
2.54 BSC
0.23
-
1.27
-
k
0.027
0.034
0.69
0.086
-
k1
0.027
0.045
0.69
1.14
2
12.70
19.05
1
1.27
1
-
1
L
0.500
0.750
L1
-
0.050
-
L2
0.250
-
6.35

45° BSC
45° BSC
3

90° BSC
90° BSC
-
N
3
3
4
Rev. 0 6/01
NOTES:
1. (All leads) Øb applies between L1 and L2. Øb1 applies between
L2 and 0.500 from the reference plane. Diameter is uncontrolled
in L1 and beyond 0.500 from the reference plane.
2. Measured from maximum diameter of the product.
3.  is the basic spacing from the centerline of the tab to terminal 1
looking at the bottom of the package.
4. N is the maximum number of terminal positions.
5. Controlling dimension: Millimeter.
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14
March 25, 2014
FN4560.10
HS-117RH, HS-117EH
Hermetic Metal Package
ØP
E
T3.D
A
A1
3 LEAD JEDEC TO-257AA HERMETIC METAL PACKAGE
INCHES
D
L1
D1
D2
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.188
0.200
4.78
5.08
7
A1
0.035
0.045
0.89
1.14
-
LEAD #1 A
A
A2
e
e1
Øb
-
D
0.645
0.665
16.39
16.89
-
0.410
0.430
10.41
10.92
-
D2
-
0.038
0.97
-
0.100 BSC
0.200 BSC
-
2.54 BSC
-
5.08 BSC
E
0.410
0.420
10.41
10.67
-
Øb
0.025
0.040
0.64
1.02
1, 2
Øb1
0.025
0.035
0.64
0.89
1, 2
L
0.500
0.750
12.70
19.05
-
L1
0.527
0.537
13.39
13.64
-
P
0.140
0.150
3.56
N
Øb
3.05 BSC
D1
e1
LEAD #3
0.120 BSC
A2
e
L
MILLIMETERS
3
3.81
-
3
Øb1
5
Rev. 2 3/09
NOTES:
3 PLC
1. Dimension Øb1 applies to base metal only.
Dimension Øb applies to plated part.
2. Section A-A dimension apply between 0.100 inch (2.54mm) to
0.150 inch (3.81mm) from lead tip.
3. Die to base BeO isolated, terminals to case is plated.
4. Controlling dimensions are in inches (mm for reference only).
5. N is the maximum number of terminal positions.
6. Patterned after MIL-STD-1835 MSFM1-P3AA.
7. “A” minimum dimension not meeting the MIL-STD 0.190 minimum dimension.
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15
March 25, 2014
FN4560.10