LT3090 –36V, 600mA Negative Linear Regulator with Programmable Current Limit Description Features n n n n n n n n n n n n n n n n n Output Current: 600mA Single Resistor Sets Output Voltage 50µA SET Pin Current: ±1% Initial Accuracy Programmable Current Limit Positive or Negative Output Current Monitor Parallelable for Higher Current and Heat Spreading Low Dropout Voltage: 300mV Low Output Noise: 18µVRMS (10Hz to 100kHz) Configurable as 3-Terminal Floating Regulator Wide Input Voltage Range: –1.5V to –36V Rail-to-Rail Output Voltage Range: 0V to –32V Positive/Negative Shutdown Logic or UVLO Programmable Cable Drop Compensation Load Regulation: 1.2mV (1mA to 600mA) Stable with 4.7µF Minimum Output Capacitor Stable with Ceramic or Tantalum Capacitors Thermally Enhanced 12-Lead MSOP and 10-Lead 0.75mm × 3mm × 3mm DFN Packages Applications n n n n Post Regulator for Switching Supplies Low Noise Instrumentation and RF Supplies Rugged Industrial Supplies Precision Power Supplies The LT®3090 is a 600mA, low dropout negative linear regulator that is easily parallelable to increase output current or spread heat on surface mounted boards. Designed with a precision current reference followed by a high performance rail-to-rail voltage buffer, this regulator finds use in applications requiring precision output, high current with no heat sink, output adjustability to zero and low dropout voltage. The device can also be configured as a 3-terminal floating regulator. The LT3090 features fast transient response, high PSRR and output noise as low as 18µVRMS. The LT3090 generates a wide output voltage range (0V to –32V) while maintaining unity gain operation. This yields virtually constant bandwidth, load regulation, PSRR and noise, regardless of the programmed output voltage. The LT3090 supplies 600mA at a typical dropout voltage of 300mV. Operating quiescent current is nominally 1mA and drops to << 1µA in shutdown. A single resistor adjusts the LT3090’s precision programmable current limit. The LT3090’s positive or negative current monitor either sources a current (0.5mA/A) or sinks a current (1mA/A) proportional to output current. Built-in protection includes reverse output protection, internal current limit with foldback and thermal shutdown with hysteresis. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent Pending. Typical Application 0.1µF LT3090 TO ADC (IMON) 49.9k 3.32k SET GND IMONP 4.7µF VOUT –2.5V MAX IOUT 600mA OUT + Output Noise: 10Hz to 100kHz VOUT 100µV/DIV – 4.7µF VIN –3V TO –10V 50µA IMONN IN 3.3V SHDN ILIM 0.1µF 10k 1ms/DIV VIN: –3.5V VOUT: –2V COUT: 4.7µF, CSET: 0.1µF IL: 600mA 3090 TA01b 3090 TA01a 3090fa For more information www.linear.com/LT3090 1 LT3090 Absolute Maximum Ratings (Note 1) IN Pin Voltage (Note 3) with Respect to GND Pin............................0.3V, –40V ILIM Pin Voltage with Respect to IN Pin (Note 3).................–0.3V, 0.7V IMONP Pin Voltage with Respect to IN Pin (Note 3)..................–0.3V, 40V with Respect to GND Pin.............................–40V, 20V with Respect to IMONN Pin.........................–40V, 20V IMONN Pin Voltage with Respect to IN Pin (Note 3)..................–0.3V, 40V with Respect to GND Pin.............................–40V, 20V SHDN Pin Voltage with Respect to IN Pin (Note 3)..................–0.3V, 55V with Respect to GND Pin.............................–40V, 20V SET Pin Voltage with Respect to IN Pin (Note 3)..................–0.3V, 36V with Respect to GND Pin.....................................±36V SET Pin Current (Note 9)........................................±5mA OUT Pin Voltage with Respect to IN Pin (Note 3)..................–0.3V, 36V with Respect to GND Pin.....................................±36V Output Short-Circuit Duration........................... Indefinite Operating Junction Temperature Range (Note 2) E-, I-Grade......................................... –40°C to 125°C MP-Grade.......................................... –55°C to 150°C H-Grade............................................. –40°C to 150°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 Sec) MSE Package .................................................... 300°C Pin Configuration TOP VIEW TOP VIEW IN 1 10 OUT IN 2 9 OUT ILIM 3 IMONP 4 IMONN 5 11 IN IN IN IN ILIM IMONP IMONN 8 GND 7 SET 6 SHDN 1 2 3 4 5 6 13 IN 12 11 10 9 8 7 OUT OUT OUT GND SET SHDN MSE PACKAGE 12-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 34°C/W, θJC = 5.5°C/W EXPOSED PAD (PIN 11) IS IN, MUST BE SOLDERED TO PCB TJMAX = 150°C, θJA = 33°C/W, θJC = 8°C/W EXPOSED PAD (PIN 13) IS IN, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3090EDD#PBF LT3090EDD#TRPBF LGHJ 10-Lead (3mm x 3mm) Plastic DFN –40°C to 125°C LT3090IDD#PBF LT3090IDD#TRPBF LGHJ 10-Lead (3mm x 3mm) Plastic DFN –40°C to 125°C LT3090HDD#PBF LT3090HDD#TRPBF LGHJ 10-Lead (3mm x 3mm) Plastic DFN –40°C to 150°C LT3090MPDD#PBF LT3090MPDD#TRPBF LGHJ 10-Lead (3mm x 3mm) Plastic DFN –55°C to 150°C LT3090EMSE#PBF LT3090EMSE#TRPBF 3090 12-Lead Plastic MSOP –40°C to 125°C LT3090IMSE#PBF LT3090IMSE#TRPBF 3090 12-Lead Plastic MSOP –40°C to 125°C LT3090HMSE#PBF LT3090HMSE#TRPBF 3090 12-Lead Plastic MSOP –40°C to 150°C LT3090MPMSE#PBF LT3090MPMSE#TRPBF 3090 12-Lead Plastic MSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2 For more information www.linear.com/LT3090 3090fa LT3090 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS Minimum IN Voltage (Note 11) ILOAD = 100mA ILOAD = 600mA SET Pin Current (ISET) Output Offset Voltage VOS (VOUT – VSET) MIN TYP l –1.9 –1.5 –1.5 VIN = –1.9V, ILOAD = 1mA, –36V < VIN < –1.9V, 1mA < ILOAD < 600mA (Note 5) l 49.5 49 50 50 VIN = –1.9V, ILOAD = 1mA, –36V < VIN < –1.9V, 1mA < ILOAD < 600mA (Note 5) l –1 –2 Line Regulation: ΔISET/ΔVIN VIN = –1.9V to –36V, ILOAD = 1mA Line Regulation: ΔVOS/ΔVIN VIN = –1.9V to –36V, ILOAD = 1mA MAX UNITS V V 50.5 51 µA µA 1 2 mV mV 1.5 2.5 nA/V µV/V ILOAD = 1mA to 600mA ILOAD = 1mA to 600mA, VIN = –1.9V (Note 6) l 0.5 1.2 2.5 nA mV Output Regulation with SET Pin Voltage Change: VSET = 0V to –32V, VIN = –36V, ILOAD = 1mA ΔISET/ΔVSET ΔVOS/ΔVSET VSET = 0V to –32V, VIN = –36V, ILOAD = 1mA l l 0.2 2.5 1 30 nA/V µV/V 185 230 270 240 300 360 450 mV mV mV mV mV mV 1.4 1.4 5 22.5 mA mA mA mA Load Regulation: ΔISET Load Regulation: ΔVOS Dropout Voltage VIN = VOUT(NOMINAL) (Note 7) GND Pin Current VIN = VOUT(NOMINAL) (Note 8) ILOAD = 1mA ILOAD = 1mA ILOAD = 100mA ILOAD = 100mA ILOAD = 600mA ILOAD = 600mA l 195 l 300 l ILOAD = 10µA ILOAD = 1mA ILOAD = 100mA ILOAD = 600mA 1 1.05 2.6 11.5 l l l l Error Amplifier RMS Output ILOAD = 600mA, BW = 10Hz to 100kHz, COUT = 4.7µF, CSET = 0.1µF Noise (Note 12) 18 µVRMS Reference Current RMS Output Noise (Note 12) BW = 10Hz to 100kHz 10 nARMS Ripple Rejection VIN – VOUT = –1.5V (Avg) VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 100mA, COUT = 4.7µF, CSET = 0.47µF VRIPPLE = 50mVP-P, fRIPPLE = 10kHz, ILOAD = 600mA, COUT = 4.7µF, CSET = 0.47µF VRIPPLE = 50mVP-P, fRIPPLE = 1MHz, ILOAD = 600mA, COUT = 4.7µF, CSET = 0.47µF 70 85 50 20 dB dB dB SHDN Pin Turn-ON Threshold Positive SHDN Rising Negative SHDN Rising (in Magnitude) 1.14 –1.36 1.23 –1.27 SHDN Pin Hysteresis Positive SHDN Hysteresis Negative SHDN Hysteresis 180 190 SHDN Pin Current (Note 10) VSHDN = 0V VSHDN = 15V VSHDN = –15V 21 –4.5 Quiescent Current in Shutdown VIN = –6V, VSHDN = 0V VIN = –6V, VSHDN = 0V Internal Current Limit (Note 13) VIN = –1.9V, VOUT = 0V VIN = –13V, VOUT = 0V VIN = –36V, VOUT = 0V VIN = –1.9V, ∆VOUT < 10mV Programmable Current Limit l l –7 V V mV mV ±1 30 µA µA µA 0.1 1 10 µA µA 850 60 830 mA mA mA mA 540 115 A•kΩ mA mA l Programming Scale Factor: –36V < VIN < –1.9V, IOUT > 50mA (Note 14) Max IOUT: VIN = –1.9V, RILIM = 20k Max IOUT: VIN = –1.9V, RILIM = 100k 1.32 –1.18 l 650 l l 20 630 750 350 35 730 l l 460 85 10 500 100 3090fa For more information www.linear.com/LT3090 3 LT3090 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS Positive Current Monitor (Note 15) Positive Current Monitoring (IMONP) Scale Factor IOUT = 600mA, VIN = –2.5V, VIMONN = 2V, VIMONP = 0V IOUT = 100mA, VIN = –2.5V, VIMONN = 2V, VIMONP = 0V l l 280 42.5 0.5 300 50 320 57.5 mA/A µA µA Negative Current Monitor Negative Current Monitoring (IMONN) Scale Factor IOUT = 600mA, VIN = –2.5V, VIMONN = 0V, VIMONP = –2.5V IOUT = 100mA, VIN = –2.5V, VIMONN = 0V, VIMONP = –2.5V l l 560 85 1 600 100 640 115 mA/A µA µA Minimum Required Load Current (Note 4) –36V < VIN < –1.9V l 10 Thermal Regulation ISET 10ms Pulse 0.04 Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. The LT3090 is tested and specified under pulsed load conditions such that TJ ≅ TA. The LT3090E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization, and correlation with statistical process controls. The LT3090I is guaranteed over the full –40°C to 125°C operating junction temperature range. The LT3090MP is 100% tested and guaranteed over the full –55°C to 150°C operating junction temperature range. The LT3090H is 100% tested at the 150°C operating junction temperature. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3. Parasitic diodes exist internally between the OUT, SET, ILIM, SHDN, IMONP, IMONN, and GND pins and the IN pin. Do not drive OUT, SET, ILIM, SHDN, IMONP, IMONN, and GND pins more than 0.3V below the IN pin during fault conditions. These pins must remain at a voltage more positive than IN during normal operation. Note 4. The LT3090 may go out of regulation if the minimum output current requirement is not satisfied. Note 5. Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current, primarily due to the internal current limit foldback which decreases current limit at VOUT – VIN ≥ 7V. If operating at maximum output current, limit the input voltage range. If operating at maximum input voltage, limit the output current range. 4 µA %/W Note 6. Load regulation is Kelvin sensed at the package. Note 7. Dropout voltage is the minimum output-to-input voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage is: VIN + VDROPOUT. Note 8. GND pin current is tested with VIN = VOUT(NOMINAL) and a current source load. Therefore, the device is tested while operating in dropout. This is the worst-case GND pin current. GND pin current decreases at higher input voltages. Note 9. The SET pin is clamped to OUT with diodes through 12k resistors. These resistors and diodes only carry current under transient overloads or fault conditions. Note 10. Positive SHDN pin current flows into the SHDN pin. Note 11. The SHDN threshold must be met to ensure device operation. Note 12. Output noise decreases by adding a capacitor across the voltage setting resistor. Adding this capacitor bypasses the voltage setting resistor’s thermal noise as well as the reference current’s noise. Output noise then equals the error amplifier noise (see Applications Information section). Note 13. The internal back-up current limit circuitry incorporates foldback protection that decreases current limit for VOUT – VIN ≥ 7V. Some level of output current is provided at all VOUT – VIN differential voltages. Please consult the Typical Performance Characteristic graph for current limit vs VOUT – VIN. Note 14. The current limit programming scale factor is specified while the internal backup current limit is not active. Please note that the internal current limit has foldback protection for VOUT-to-VIN differentials greater than 7V. Note 15. For positive current monitoring, bias IMONN to ≥ 2V above IMONP. 3090fa For more information www.linear.com/LT3090 LT3090 Typical Performance Characteristics SET Pin Current 50.5 2.0 N = 3122 50.2 50.1 50.0 49.9 49.8 49.7 49.5 –75 –50 –25 49 0 25 50 75 100 125 150 TEMPERATURE (°C) 49.5 50 50.5 DISTRIBUTION (µA) 1.0 0.5 0 –0.5 –1.0 –2.0 –75 –50 –25 51 3090 G02 3090 G01 Offset Voltage N = 3122 2.0 IL = 1mA VOUT = –1.25V 50.4 50.1 50.0 49.9 49.8 –55°C 25°C 125°C 150°C 49.6 –1 0 1 VOS DISTRIBUTION (mV) 49.5 2 49.9 49.8 –55°C 25°C 125°C 150°C –8 –12 –16 –20 –24 –28 –32 OUTPUT VOLTAGE (V) 3090 G07 OFFSET VOLTAGE (mV) 50.0 –4 –1.0 –55°C 25°C 125°C 150°C –1.5 –2.0 0 –5 –10 –15 –20 –25 –30 –35 –40 INPUT VOLTAGE (V) 3090 G06 Load Regulation 1.0 0.5 0 –0.5 –1.0 –55°C 25°C 125°C 150°C –1.5 –2.0 0 –4 –8 –12 –16 –20 –24 –28 –32 OUTPUT VOLTAGE (V) 3090 G08 20 2.5 ∆IL = 1mA to 600mA VIN = –1.9V VOUT = –1.25V 2.0 10 1.5 0 1.0 –10 0.5 –20 –75 –50 –25 OFFSET VOLTAGE LOAD REGULATION (mV) 50.1 0 –0.5 30 IL = 1mA VIN = –36V 1.5 50.2 49.6 0 Offset Voltage (VOUT – VSET) 2.0 50.3 49.7 –10 –15 –20 –25 –30 –35 –40 INPUT VOLTAGE (V) 0.5 3090 G05 IL = 1mA VIN = –36V 50.4 –5 3090 G04 Set Pin Current 50.5 0 IL = 1mA VOUT = –1.25V 1.0 SET PIN CURRENT LOAD REGULATION (nA) –2 OFFSET VOLTAGE (mV) SET PIN CURRENT (µA) 50.3 49.7 Offset Voltage (VOUT – VSET) 1.5 50.2 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G03 Set Pin Current 50.5 SET PIN CURRENT (µA) IL = 1mA VOUT = –1.25V VIN = –1.9V –1.5 49.6 49.5 Offset Voltage (VOUT – VSET) 1.5 OFFSET VOLTAGE (mV) 50.3 SET PIN CURRENT (µA) SET Pin Current IL = 1mA VOUT = –1.25V VIN = –1.9V 50.4 TJ = 25°C, unless otherwise noted. 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G09 3090fa For more information www.linear.com/LT3090 5 LT3090 Typical Performance Characteristics Quiescent Current 450 VSHDN = VIN DROPOUT VOLTAGE (mV) 0.8 0.4 0.2 0 –75 –50 –25 400 450 350 400 300 250 200 150 –55°C 25°C 125°C 150°C 100 50 VSHDN = 0V 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 100 400 500 200 300 OUTPUT CURRENT (mA) Dropout Voltage 300 IL = 300mA IL = 1mA 150 IL = 100mA 100 50 8 6 4 –55°C 25°C 125°C 150°C 0 100 POSITIVE SHDN TURN-ON THERSHOLD (V) MINIMUM INPUT VOLTAGE (V) –1.2 –1.0 –0.8 –0.6 –0.4 RSET = 25kΩ IL = 1mA 0 25 50 75 100 125 150 TEMPERATURE (°C) 300 400 500 200 OUTPUT CURRENT (mA) 3090 G16 VOUT(NOMINAL) = –3V IL = 600mA 6 IL = 300mA 4 IL = 100mA IL = 1mA 0 –2.5 –2.6 –2.7 –2.8 –2.9 –3 –3.1 –3.2 –3.3 –3.4 –3.5 INPUT VOLTAGE (V) 600 3090 G15 SHDN Pin Hysteresis –1.300 VIN = –1.9V 1.275 –1.275 1.250 –1.250 1.225 –1.225 1.200 –1.200 1.175 –1.175 1.150 –75 –50 –25 600 8 2 –1.150 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G17 0.30 NEGATIVE SHDN TURN-ON THRESHOLD (V) –1.4 200 300 400 500 OUTPUT CURRENT (mA) 10 SHDN Turn-On Threshold –1.6 100 3090 G14 1.300 –1.8 0 GND Pin Current Entering Dropout 10 Minimum Input Voltage 6 100 3090 G12 12 0 0 25 50 75 100 125 150 TEMPERATURE (°C) –2.0 0 –75 –50 –25 150 12 3090 G13 –0.2 200 14 2 0 –75 –50 –25 TJ ≤ 25°C 250 0 600 VIN = –3.5V VOUT = –3V 14 IL = 600mA GND PIN CURRENT (mA) DROPOUT VOLTAGE (mV) 400 200 300 GND Pin Current 16 450 250 350 3090 G11 3090 G10 350 TJ ≤ 150°C 50 GND PIN CURRENT (mA) 0.6 RL = 125kΩ (10µA) VOUT = –1.25V VIN = –1.9V 500 VIN = –1.9V 0.25 SHDN PIN HYSTERESIS (V) QUIESCENT CURRENT (mA) 1.0 Guaranteed Dropout Voltage Typical Dropout Voltage DROPOUT VOLTAGE (mV) 1.2 TJ = 25°C, unless otherwise noted. 0.20 0.15 0.10 0.05 0 –75 –50 –25 POSITIVE SHDN HYSTERESIS NEGATIVE SHDN HYSTERESIS 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G18 3090fa For more information www.linear.com/LT3090 LT3090 Typical Performance Characteristics SHDN Pin Current VIN = –36V IMONN Pin Current 700 VIN = –15V 10 5 0 –55°C 25°C 125°C 150°C –10 –15 –36 –28 –20 –12 –4 4 SHDN PIN VOLTAGE (V) 12 15 10 5 0 –5 –75 –50 –25 20 510 500 490 480 VOUT = –1.2V VIMONN = –0.5V VIMONP = VIN ILOAD = 500mA 470 460 –75 –50 –25 110 105 100 95 90 VOUT = –1.2V VIMONN = –0.5V VIMONP = VIN ILOAD = 100mA 85 80 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) IMONP CURRENT (µA) IMONP CURRENT (µA) 58 56 245 240 200 300 400 500 OUTPUT CURRENT (mA) VOUT = –1.2V VIMONN = 3V VIMONP = 0.5 ILOAD = 100mA 600 IMONP Pin Current 250 200 150 100 VOUT = –1.2V VIN = –3V VIMONN = 3V VIMONP = 0.5V 50 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 100 200 300 400 ILOAD (mA) 500 600 700 3090 G24 Programmable Current Limit 600 VIN = –3V VIN = –7V 54 52 50 48 46 44 235 230 –75 –50 –25 60 VIN = –3V VIN = –7V 250 100 300 IMONP Pin Current at 100mA 255 0 3090 G23 IMONP Pin Current at 500mA VOUT = –1.2V 265 VIMONN = 3V VIMONP = 0.5 260 ILOAD = 500mA 350 VIN = –3V VIN = –7V 3090 G22 270 200 3090 G21 IMONN Pin Current at 100mA 115 IMONN CURRENT (µA) IMONN CURRENT (µA) 120 VIN = –3V VIN = –7V 520 300 3090 G20 IMONN Pin Current at 500mA 530 400 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G19 540 500 100 VSHDN = –15V IMONP CURRENT (µA) –5 VSHDN = 15V IMONN CURRENT (µA) 15 VIN = –3V VOUT = –1.2V VIMONN = –0.5V VIMONP = VIN 600 20 20 SHDN PIN CURRENT (µA) SHDN PIN CURRENT (µA) 25 SHDN Pin Current 25 500 CURRENT LIMIT (mA) 30 TJ = 25°C, unless otherwise noted. 400 VIN = –2V VOUT = 0V 300 200 RILIM = 20k RILIM = 100k 100 42 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G25 40 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G26 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G27 3090fa For more information www.linear.com/LT3090 7 LT3090 Typical Performance Characteristics Programmable Brick-Wall Current Limit RILIM = 20k RILIM = 40k RILIM = 100k –0.75 –0.50 0 100 500 400 300 200 100 RSET = 25K VIN = –3V 0 50 600 CURRENT LIMIT (mA) –1.00 –0.25 Internal Current Limit 60 700 CURRENT LIMIT (mA) OUTPUT VOLTAGE (V) –1.25 Internal Current Limit 800 200 300 400 500 OUTPUT CURRENT (mA) 0 –75 –50 –25 600 400 300 200 60 50 40 30 20 VOUT = –2.5V ILOAD = 600mA CSET = 0.1µF INPUT RIPPLE = 50mVRMS 10 VOUT = 0V 0 –6 –18 –12 –24 –30 INPUT-TO-OUTPUT DIFFERENTIAL (V) 0 –36 10 100 1k 10k 100k FREQUENCY (Hz) 40 0 VOUT = –2.5V ILOAD = 600mA CSET = 0.1µF INPUT RIPPLE = 50mVRMS 10 100 1k 10k 100k FREQUENCY (Hz) 20 1M 10M VOUT = –2.5V VIN = –3.5V CSET = 0.1µF INPUT RIPPLE = 50mVRMS 10 100 1k 10k 100k FREQUENCY (Hz) 85 80 70 –75 –50 –25 1M 10M 3090 G33 Noise Spectral Density 90 75 3090 G34 8 30 0 10M 95 RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) 50 10 40 VIN = –4V VOUT = –2.5V ILOAD = 600mA CSET = 0.47µF 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G35 1k 100 100 10 10 10 100 1k 10k FREQUENCY (Hz) REFERENCE CURRENT NOISE SPECTRAL DENSITY (pA/√Hz) 60 20 50 Ripple Rejection (120Hz) 70 30 1M 100 COUT = 4.7µF, CSET = 0.1µF COUT = 22µF, CSET = 0.1µF COUT = 4.7µF, CSET = 0.47µF 80 60 3090 G32 Input Ripple Rejection 90 IL = 600mA IL = 300mA IL = 100mA 70 10 3090 G31 100 Input Ripple Rejection –3VIN –3.5VIN –4.5VIN 70 100 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 80 RIPPLE REJECTION (dB) 500 80 RIPPLE REJECTION (dB) CURRENT LIMIT (mA) 600 VIN = –36V VOUT = 0V 3090 G30 Input Ripple Rejection –55°C 25°C 125°C 150°C 700 20 3090 G29 Internal Current Limit 800 30 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3090 G28 40 10 VIN = –1.9V VOUT = 0V ERROR AMPLIFIER NOISE SPECTRAL DENSITY (nV/√Hz) –1.50 TJ = 25°C, unless otherwise noted. 1 100k 3090 G36 3090fa For more information www.linear.com/LT3090 LT3090 Typical Performance Characteristics Output Noise: 10Hz to 100kHz TJ = 25°C, unless otherwise noted. Load Transient Response, –3VOUT Output Noise: 10Hz to 100kHz ILOAD 300mA/DIV VOUT 1mV/DIV VOUT 100µV/DIV ∆VOUT 100mV/DIV 1ms/DIV VIN: –3.5V COUT: 4.7µF, CSET: 20pF VOUT: –2V IL: 600mA 1ms/DIV VIN: –3.5V COUT: 4.7µF, CSET: 0.1µF VOUT: –2V IL: 600mA 3090 G37 3090 G38 20µs/DIV ILOAD: 20mA TO 600mA COUT: 4.7µF, CSET: 0.1µF VOUT: –3V VIN = –4V, SHDN = IN 3090 G39 Slow Input Supply Ramp-Up and Ramp-Down Line Transient Response 0V VOUT 1V/DIV VIN 500mV/DIV ∆VOUT 50mV/DIV VIN 1V/DIV VIN: –5V TO –4V COUT: 4.7µF, CSET: 0.1µF VOUT: –3V IL: 600mA, SHDN = IN 50ms/DIV VIN: –5V TO 0V COUT: 4.7µF, CSET: 0.1µF VOUT: –3V TO 0V IL: 600mA, SHDN = IN Fast Input Supply Start-Up Fast Input Supply Start-Up 5µs/DIV 3090 G40 0V 0V VIN 2V/DIV VIN 2V/DIV 0V 0V VOUT 1V/DIV VOUT 1V/DIV 20µs/DIV VIN: 0V TO –5V COUT: 4.7µF, CSET: 100pF VOUT: 0V TO –3V IL: 600mA, SHDN = IN 3090 G42 5ms/DIV VIN: 0V TO –5V COUT: 4.7µF, CSET: 0.1µF VOUT: 0V TO –3V IL: 600mA, SHDN = IN 3090 G41 3090 G43 3090fa For more information www.linear.com/LT3090 9 LT3090 Pin Functions (DFN/MSOP) IN (Pins 1, 2, Exposed Pad 11/1, 2, 3, Exposed Pad 13): Input. These pins supply power to the regulator. The exposed backside pad of the DFN and MSOP packages is an electrical connection to IN and the device’s substrate. For proper electrical and thermal performance, tie all IN pins together and tie IN to the exposed backside of the package on the PCB. See the Applications Information section for thermal considerations and calculating junction temperature. The LT3090 requires a bypass capacitor at IN. In general, a battery’s output impedance rises with frequency, so include a bypass capacitor in battery powered applications. An input bypass capacitor in the range of 2.2µF to 4.7µF generally suffices, but applications with large load transients or longer input lines may require higher input capacitance to prevent input supply droop or input ringing. ILIM (Pin 3/4): Current Limit Programming Pin. Connecting an external resistor between the ILIM and IN pins programs the current limit set point. For best accuracy, Kelvin connect this resistor to the IN pins. The programming scale factor is nominally 10A • kΩ. Current limit is accurate to ±8% over temperature. If unused, tie ILIM to IN and the internal current limit protects the part. A parasitic substrate diode exists between the LT3090’s ILIM and IN pins. Therefore, do not drive ILIM more than 0.3V below IN during normal operation or during a fault condition. IMONP (Pin 4/5): Positive Current Monitoring Pin. For positive current monitoring, connect a resistor between IMONP and GND. IMONP sources current equal to 1/2000 of output current. For negative current monitoring, tie this pin to IN. For proper operation, IN and IMONP must be at least 2V below IMONN. If unused, tie IMONP to IN. A parasitic substrate diode exists between the LT3090’s IMONP and IN pins. Therefore, do not drive IMONP more than 0.3V below IN during normal operation or during a fault condition. IMONN (Pin 5/6): Negative Current Monitoring Pin. For negative current monitoring, connect a resistor between IMONN and GND. IMONN sinks current equal to 1/1000 of output current. For positive current monitoring, bias IMONN 10 to a positive supply voltage (at least 2V above IMONP). If unused, tie IMONN to the GND pin. A parasitic substrate diode exists between the LT3090’s IMONN and IN pins. Therefore, do not drive IMONN more than 0.3V below IN during normal operation or during a fault condition. SHDN (Pin 6/7): Shutdown. Use the SHDN pin to put the LT3090 into a micropower shutdown state and to turn off the output voltage. The SHDN function is bidirectional, allowing either positive or negative logic to turn the regulator ON/OFF. The SHDN pin threshold voltages are referenced to GND. The output of the LT3090 is OFF if the SHDN pin is pulled within ±0.45V of GND. Driving the SHDN pin more than ±1.4V turns the LT3090 ON. Drive the SHDN pin with either a logic gate or with open collector/drain logic using a pull-up resistor. The resistor supplies the pull-up current of the open collector/drain gate. The maximum SHDN pin current is 7µA out of the pin (for negative logic) or 30µA into the pin (for positive logic). If the SHDN function is unused, connect the SHDN pin to VIN or a positive bias voltage to turn the device ON. Do not float the SHDN pin. As detailed in the Applications Information section, the SHDN pin can also be used to set a programmable undervoltage lockout (UVLO) threshold. A parasitic diode exists between the LT3090’s SHDN and IN pins. Therefore, do not drive SHDN more than 0.3V below IN during normal operation or during a fault condition. SET (Pin 7/8): SET. This pin is the inverting input to the error amplifier and the regulation setpoint for the device. A precision fixed current of 50µA flows into this pin. Connecting a resistor from SET to GND programs the LT3090’s output voltage. Output voltage range is from zero to the –36V absolute maximum rating. Adding a bypass capacitor from SET to GND improves transient response, PSRR, noise performance and soft starts the output. Kelvin connect the GND side of the SET pin resistor to the load for optimum load regulation performance. A parasitic substrate diode exists between the LT3090’s SET and IN pins. Therefore, do not drive SET more than 0.3V below IN during normal operation or during a fault condition. 3090fa For more information www.linear.com/LT3090 LT3090 Pin Functions (DFN/MSOP) GND (Pin 8/9): Ground. This pin supplies the LT3090's quiescent current and the drive current to the NPN pass transistor. The LT3090's GND pin is highly versatile. Depending on application’s requirements, it can be tied to the system ground, a positive voltage, or the OUT pin. A parasitic substrate diode exists between the LT3090’s GND and IN pins. Therefore, do not drive GND more than 0.3V below IN during normal operation or during a fault condition. OUT (Pins 9, 10/10, 11, 12): Output. These pins supply power to the load. Tie all OUT pins together for best performance. Use a minimum output capacitor of 4.7µF with an ESR less than 0.5Ω to prevent oscillations. As mentioned in the Electrical Characteristics table, a minimum load current of 10µA is required to prevent instability. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitance. A parasitic substrate diode exists between OUT and IN pins of the LT3090. Therefore, do not drive OUT more than 0.3V below IN during normal operation or during a fault condition. Block Diagram COUT RSET SET RLOAD OUT SHDN GND 1.23V IMONN – + BIAS – –1.27V + BIDIRECTIONAL SHUTDOWN 20.25µA – – + 0.135Ω 5k + RAIL-TO-RAIL ERROR AMP 50µA 2x INTERNAL CURRENT LIMIT 1x + + V 225mV + DRIVER – – + – – 3k 270Ω PROGRAMMABLE CURRENT LIMIT IN ILIM POSITIVE OR NEGATIVE CURRENT MONITOR IMONP RILIM CIN IN 3090 BD 3090fa For more information www.linear.com/LT3090 11 LT3090 Applications Information The LT3090 is a 600mA, rail-to-rail output, negative low dropout linear regulator featuring very low output noise, high bandwidth, precision programmable current limit, precision positive or negative current monitor, and bidirectional shutdown. The LT3090 supplies 600mA at a typical dropout voltage of 300mV. Unlike other devices, the LT3090 does not require a separate supply to achieve low dropout performance. The 1mA quiescent current drops to well below 1µA in shutdown. The LT3090 is easy to use and incorporates all of the protection features expected in high performance regulators. Included are short circuit protection, safe operating area protection, as well as thermal shutdown with hysteresis. In bipolar supply applications where the regulator’s load is returned to a positive supply, OUT can be pulled above GND up to 36V and still allow the LT3090 to safely startup. Output Voltage The LT3090 incorporates a zero TC 50µA reference current source that flows into the SET pin. The SET pin is the inverting input of the error amp. Connecting a resistor from SET to ground generates a voltage that becomes the reference point for the error amplifier (see Figure 1). The reference voltage is a straight multiplication of the SET pin current and the resistor value (Ohm’s Law, V = I • R). The rail-to-rail error amp’s unity gain configuration produces a low impedance voltage on its noninverting input, i.e. the OUT pin. Output voltage is programmable from 0V (using zero Ω resistor) to VIN plus dropout. Table 1 lists many common output voltages and its corresponding 1% RSET resistance. The benefits of using a current reference, as opposed to a voltage reference as in conventional regulators such as the LT1185, LT1175, LT1964 and LT3015, is that the device always operates in unity gain configuration – regardless of the programmed output voltage. This allows the LT3090 to have loop gain, frequency response, and bandwidth independent of the output voltage. Moreover, none of the error amp gain is needed to amplify the set pin voltage to a higher output voltage (in magnitude). As a result, output load regulation is specified in terms of millivolts and not a fixed percentage of the output voltage. Since the zero TC current source is very accurate, the SET pin resistor is the limiting factor in achieving high accuracy; hence, it must be a precision resistor. Moreover, any leakage paths to and from the SET pin create errors in the output voltage. If necessary, use high quality insulation (e.g. Teflon, Kel-F); moreover, cleaning of all insulating surfaces to remove fluxes and other residues may be required. High humidity environments may require a surface coating at the SET pin to provide a moisture barrier. Minimize board leakage by encircling the SET pin with a guard ring operated at a potential close to itself – ideally the guard ring should be tied to the OUT pin. Guarding both sides of the circuit board is required. Bulk leakage 0.1µF RSET 49.9k SET 12 RSET (kΩ) –2.5 49.9 –3 60.4 –3.3 66.5 –5 100 –12 243 –15 301 GND IMONN OUT + Table 1. 1% Resistor for Common Output Voltages VOUT (V) COUT 4.7µF – CIN 4.7µF VOUT –2.5V MAX IOUT 600mA LT3090 50µA IN VIN –3V TO –10V SHDN IMONP ILIM RILIM 10k 3090 F01 Figure 1. Basic Adjustable Regulator 3090fa For more information www.linear.com/LT3090 LT3090 Applications Information reduction depends on the guard ring width. Leakages as small as 50nA into or out of the SET pin creates a 0.1% error in the reference voltage. Leakages of this magnitude, coupled with other sources of leakage, can cause significant errors in the output voltage, especially over wide operating temperature range. Figure 2 illustrates a typical guard ring layout technique. If guard ring techniques are used, then SET pin stray capacitance is practically eliminated. Since the SET pin is a high impedance node, unwanted signals may couple into the SET pin and cause erratic behavior. This is most noticeable when operating with a minimum output capacitor at light load currents. The simplest remedy is to bypass the SET pin with a small capacitance to ground – 100pF is generally sufficient. 10 1 9 2 3 11 OUT 8 4 7 5 6 SET 3090 F02 Figure 2. Guard Ring Layout for DFN Stability and Input Capacitance The LT3090 is stable with a minimum of 4.7µF capacitor placed at the IN pin. Low ESR ceramic capacitors can be used. However, in cases where long wires connect the power supply to the LT3090’s input and ground, the use of low value input capacitors combined with a large output load current may result in instability. The resonant LC tank circuit formed by the wire inductance and the input capacitor is the cause and not because of LT3090 instability. The self inductance, or isolated inductance, of a wire is directly proportional to its length. However, the wire diameter has less influence on its self inductance. For example, the self inductance of a 2-AWG isolated wire with a diameter of 0.26" is about half the inductance of a 30-AWG wire with a diameter of 0.01". One foot of 30-AWG wire has 465nH of self inductance. Several methods exist to reduce a wire’s self inductance. One method divides the current flowing towards the LT3090 between two parallel conductors. In this case, placing the wires further apart reduces the inductance; up to a 50% reduction when placed only a few inches apart. Splitting the wires connects two equal inductors in parallel. However, when placed in close proximity to each other, mutual inductance adds to the overall self inductance of the wires. The second and most effective technique to reduce overall inductance is to place the forward and return current conductors (the input wire and the ground wire) in close proximity. Two 30-AWG wires separated by 0.02" reduce the overall self inductance to about one-fifth of a single wire. If a battery, mounted in close proximity, powers the LT3090, a 4.7µF input capacitor suffices for stability. However, if a distantly located supply powers the LT3090, use a larger value input capacitor. Use a rough guideline of 1µF (in addition to the 4.7µF minimum) per 8" of wire length. The minimum input capacitance needed to stabilize the application also varies with power supply output impedance variations. Placing additional capacitance on the LT3090’s output also helps. However, this requires an order of magnitude more capacitance in comparison with additional LT3090 input bypassing. Series resistance between the supply and the LT3090 input also helps stabilize the application; as little as 0.1Ω to 0.5Ω suffices. This impedance dampens the LC tank circuit at the expense of dropout voltage. A better alternative is to use higher ESR tantalum or electrolytic capacitors at the LT3090 input in place of ceramic capacitors. Stability and Output Capacitance The LT3090 requires an output capacitor for stability. It is stable with low ESR capacitors (such as ceramic, tantalum or low ESR electrolytic). A minimum output capacitor of 4.7µF with an ESR of 0.5Ω or less is recommended to prevent oscillations. Larger values of output capacitance 3090fa For more information www.linear.com/LT3090 13 LT3090 Applications Information decrease peak output deviations during a load transient. The LT3090 requires a minimum 10µA load current to maintain stability under all operating conditions. Give extra consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitance in small packages, but they have strong voltage and temperature coefficients as shown in Figures 3 and 4. When used with a 5V regulator, a 16V 10µF Y5V capacitor can exhibit an effective value as low as 1µF to 2µF for the DC bias voltage applied over the operating temperature range. 20 BOTH CAPACITORS ARE 16V 1210 CASE SIZE, 10µF CHANGE IN VALUE (%) 0 X5R –20 –40 –60 Y5V 0 2 4 8 6 10 12 DC BIAS VOLTAGE (V) 14 16 3090 F03 Figure 3. Ceramic Capacitor DC Bias Characteristics 40 BOTH CAPACITORS ARE 16V 1210 CASE SIZE, 10µF CHANGE IN VALUE (%) 20 X5R 0 –20 –40 Y5V –60 –80 –100 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3090 F04 Figure 4. Ceramic Capacitor Temperature Characteristics 14 Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates a voltage across its terminals due to mechanical stress upon it, similar to how a piezoelectric microphone works. For a ceramic capacitor the stress can be induced by mechanical vibrations within the system or due to thermal transients. Output Noise Analysis –80 –100 The X5R and X7R dielectrics result in more stable characteristics, and are thus more suitable for use as the regulator’s output capacitor. The X7R dielectric has better stability across temperature, while X5R is less expensive and is available in higher values. Nonetheless, care must still be exercised when using X5R and X7R capacitors. The X5R and X7R codes only specify operating temperature range and the maximum capacitance change over temperature. While capacitance change due to DC bias for X5R and X7R is better than Y5V and Z5U dielectrics, it can still be significant enough to drop capacitance below sufficient levels. Capacitor DC bias characteristics tend to improve as component case size increases, but verification of expected capacitance at the operating voltage is highly recommended. The LT3090 offers many advantages with respect to noise performance. Traditional linear regulators have several sources of noise. The most critical noise sources for an LDO are its voltage reference, the error amplifier, the noise of the resistors in the divider network setting output voltage and the noise gain created by this resistor divider. Many low noise regulators pin out the voltage reference to allow for bypassing and noise reduction of the reference. Unlike other linear regulators, the LT3090 does not use a traditional voltage reference, but instead it uses a 50µA current source reference. That current operates with typical noise current levels of 31.6pA/√Hz (10nARMS over a 10Hz to 100kHz bandwidth). The voltage noise equals the noise current multiplied by the resistor value. The resistor itself generates spot noise equal to √4KTR (whereby K = Boltzmann’s constant, 1.38 • 10–23 J/K and T is the absolute temperature) which is RMS summed with the reference current noise. 3090fa For more information www.linear.com/LT3090 LT3090 Applications Information One problem that conventional linear regulators face is that the resistor divider setting VOUT gains up the reference noise. In contrast, the LT3090’s unity gain follower architecture presents no gain from the SET pin to the output. Therefore, output noise is virtually independent of the output voltage setting if a capacitor bypasses the SET pin. Resultant output noise is then set by the error amplifier’s noise, typically 57nV/√Hz (18µVRMS in a 10Hz to 100kHz bandwidth). Curves in the Typical Performance Characteristics section show noise spectral density and peak-to-peak noise characteristics for both the reference current and the error amplifier over a 10Hz to 100kHz bandwidth. Set Pin (Bypass) Capacitance: Output Noise, PSRR, Transient Response and Soft-Start Bypassing the SET pin’s voltage setting resistor with a capacitor lowers output noise. The Typical Performance Characteristics section illustrates that connecting a 0.1µF from SET to GND yields output noise as low as 18µVRMS. Paralleling multiple LT3090s further reduces noise by √N, for N parallel regulators. Curves in the Typical Performance Characteristics section show noise spectral density and peak-to-peak noise characteristics for the error amplifier for different values of bypass capacitance. Use of a SET pin bypass capacitor also improves PSRR and transient response performance. It is important to note that any bypass capacitor leakage deteriorates the LT3090’s DC regulation. Capacitor leakage of even 50nA is a 0.1% DC error. Therefore, LTC recommends the use of a good quality low leakage capacitor. voltage reference to the SET pin removes any errors in output voltage due to the reference current and resistor tolerances. Shutdown/UVLO The SHDN pin is used to put the LT3090 into a micropower shutdown state. The LT3090 has an accurate –1.27V turn-ON threshold on the SHDN pin. This threshold can be used in conjunction with a resistor divider from the input supply to define an accurate undervoltage lockout (UVLO) threshold for the regulator. The SHDN pin current (at the threshold) needs to be considered when determining the resistor divider network. See the Typical Performance curves for SHDN pin current vs SHDN pin voltage. Moreover, since the SHDN pin is bidirectional, it can be taken beyond ±1.4V to turn-ON the LT3090. In bipolar supply applications, the positive SHDN threshold can be used to sequence the turn-ON of LT3090 after the positive regulator has turned on. Current Monitoring (IMONN and IMONP) The LT3090 incorporates precision positive or negative current monitor. As illustrated in the Block Diagram, the negative current monitor pin (IMONN) sinks current proportional (1:1000) to the output current while the positive current monitor pin (IMONP) sources current proportional (1:2000) to the output current. For proper operation, ensure IMONN is at least 2V above IN and IMONP. As highlighted in Figure 5, for a negative current monitor application, tie IMONP to IN and tie IMONN through a The final benefit of using a SET pin bypass capacitor is that it soft starts the output and limits inrush current. The R-C time constant, formed by the SET pin resistor and capacitor, controls soft-start time. Ramp-up rate from 0 to 90% of nominal VOUT is: 0.1µF 49.9k 4.7µF 1mV PER mA SET GND IMONN OUT LT3090 tSS ≈ 2.3 • RSET • CSET 4.7µF For applications requiring higher accuracy or an adjustable output voltage, the SET pin may be actively driven by an external voltage source capable of sourcing 50µA – the application limitations are the creativity and ingenuity of the circuit designer. For instance, connecting a precision 1k IOUT 2000 IN VIN –3V TO –10V VOUT: –2.5 MAX IOUT: 600mA SHDN IMONP ILIM 10k 3090 F05 Figure 5: Negative Output Current Monitor 3090fa For more information www.linear.com/LT3090 15 LT3090 Applications Information resistor to GND – this generates a negative voltage (proportional to output current) on IMONN. Furthermore, as illustrated in Figure 6, the negative current monitor pin can also be used for cable drop compensation. Cable drop compensation corrects for load dependent voltage drop caused by a resistive connection between the LT3090’s OUT pin and its load. RCBL2 4.7µF RCDC = RCBL • 1K LOAD 0.1µF 100k IMONN GND SET OUT RCBL = RCBL1 + RCBL2 + – 4.7µF RCBL1 LT3090 50µA IN VIN ≤–6V SHDN IMONP ILIM 10k 3090 F06 Figure 6. Simple Cable Drop Compensation For a positive current monitor application, as illustrated in Figure 7, tie IMONP through a resistor to GND—this generates a positive voltage (proportional to output current) on IMONP. And tie IMONN to a supply at least 2V above the maximum operating IMONP voltage. 0.1µF 49.9k 0.1µF SET GND 4.7µF VIN –3V TO –10V IOUT IN VOUT: –2.5V MAX IOUT: 600mA IMONP 2000 SHDN IMONN OUT ILIM 1mV PER mA 2k 10k 3090 F07 Figure 7. Positive Output Current Monitor When unused, IMONN and IMONP pins can be left floating; however, this slightly reduces (~5%) the device’s internal current limit. Hence, if the current monitor functionality is not used, as shown in Figure 1, it is recommended to tie IMONN to GND and IMONP to IN. 16 Externally Programmable Current Limit The ILIM pin internally regulates to 225mV above IN. Connecting a resistor from ILIM to IN sets the current flowing out of the ILIM pin, which in turn programs the LT3090’s current limit. The programming scale factor is 10kΩ • A. For example, a 20k resistor between ILIM and IN programs current limit to 500mA. For good accuracy, Kelvin connect this resistor to the LT3090’s IN pin. In cases where the OUT-to-IN differential is greater than 7V, the LT3090’s foldback circuitry decreases the internal current limit. Therefore, internal current limit may override the externally programmed current limit level to keep the LT3090 within its Safe-Operating-Area (SOA). See the Internal Current Limit vs Input-to-Output differential graph in the Typical Performance Characteristics section. ILIM can be tied to IN if external programmable current limit is not needed. However, because the ILIM pin is internally regulated to 225mV above IN, if ILIM pin is shorted to IN, then this loop will current limit, thereby causing the LT3090’s quiescent current to increase by about 300µA. Hence, when unused, it is recommended to tie ILIM to IN through a 10k resistor. Load Regulation 4.7µF ≥3V LT3090 The LT3090’s positive or negative current monitor circuitry is designed to remain accurate even under short circuit or dropout conditions. The LT3090 does not have a separate Kelvin connection for sensing output voltage. Therefore, it is not possible to provide true remote load sensing. The connectivity resistance between the regulator and the load limits load regulation. The data sheet specification for load regulation is Kelvin sensed at the OUT pin of the package. GND side Kelvin sensing is a true Kelvin connection, with the top of the voltage setting resistor returned to the positive side of the load (see Figure 8). Connected as shown, system load regulation is the sum of the LT3090 load regulation and the parasitic line resistance multiplied by the output current. It is therefore important to keep the negative connection between the regulator and the load as short as possible and to use wide wires or PC board traces. For more information www.linear.com/LT3090 3090fa LT3090 Applications Information PARASITIC RESISTANCE RP SET RP IMONN GND LOAD RP RSET 49.9k OUT + COUT 4.7µF – CIN 4.7µF VOUT –2.5V MAX IOUT 600mA LT3090 50µA IN VIN –3V TO –10V ILIM IMONP SHDN RILIM 3090 F08 10k Figure 8. Connections for Best Load Regulation Floating 3-Terminal Regulator The LT3090’s rail-to-rail error amp allows the LDO to be configured as a floating three-terminal regulator. With proper protection, the LT3090 can be used in arbitrarily high voltage applications. Figure 9 illustrates this configuration. In this mode, the GND pin current is supplied by the load; hence, a minimum 1mA load current is required to maintain regulation. If true zero output voltage operation is required, return the 1mA load current to a positive supply. Note that in three terminal operation, the minimum input voltage is now the device’s dropout voltage. Furthermore, the ILIM pin is internally regulated to 225mV above IN. This servo loop will current limit if ILIM is shorted to IN, thereby causing LT3090’s quiescent current to increase by about 300µA. Hence, when unused, it is recommended to tie ILIM to IN through a 10k resistor. 0.1µF COUT 15µF RSET 301k GND SET IMONN OUT + – CIN 4.7µF VIN –17V TO –22V VOUT –15V MAX IOUT 600mA It is important to note that in a floating configuration and with slow VIN ramp-up and ramp-down (as shown in Figures 10 and 11), the LT3090 may exhibit oscillations during start-up if SHDN is tied to VIN. This occurs because the SHDN comparator’s turn-ON and turn-OFF thresholds are referenced to the GND pin of LT3090. Since in floating configuration the GND pin of LT3090 is tied to the OUT pin, which is slowly increasing as VIN is ramping up, the reference point for the SHDN comparator is changing; hence, it causes start-up oscillations. This oscillation can be minimized by placing at least 0.1µF and 15µF capacitor at the SET and OUT pins, respectively—although it won’t be eliminated, as per Figures 10 and 11 below. For fast VIN ramp-up and ramp-down the LT3090 does not oscillate. If however, the SHDN pin is tied to a positive supply, 1.3V and above (as shown in Figure 12), then there are no startup oscillations and a 4.7µF minimum output capacitor can be used—but having some SET pin capacitance is still recommended. In addition to tying the GND pin to the OUT pin (for floating configuration), the GND pin of LT3090 can also be tied to a positive voltage as shown in the next section. VOUT 1V/DIV VIN 2V/DIV 10ms/DIV VIN: 0V TO –5V COUT: 15µF, CSET: 0.1µF VOUT: 0V TO –3V IL: 600mA, SHDN = IN 3090 F10 Figure 10. Floating Mode: Input Supply Ramp-Up VOUT 1V/DIV VIN 2V/DIV LT3090 50µA IN SHDN IMONP 1ms/DIV VIN: –5V TO 0V COUT: 15µF, CSET: 0.1µF VOUT: –3V TO 0V IL: 600mA, SHDN = IN ILIM RILIM 10k 3090 F09 Figure 9. Floating 3-Terminal Adjustable Regulator 3090 F11 Figure 11. Floating Mode: Input Supply Ramp-Down 3090fa For more information www.linear.com/LT3090 17 LT3090 Applications Information set below the LT3090’s –1.9V minimum input voltage. As long as there is 1.9V between IN and GND pins of LT3090, the minimum operating voltage is satisfied. Now it can operate with much lower dropout voltage, with the device dropout set by the pass device as illustrated in Figure 14. VOUT 1V/DIV VIN 2V/DIV 50ms/DIV VIN: –5V TO 0V COUT: 15µF, CSET: 0.1µF VOUT: –3V TO 0V IL: 600mA, VSHDN = 1.5V 3090 F12 0.1µF Figure 12. Floating Mode: Input Supply Ramp-Up and Down Using Positive SHDN CGND 0.47µF RSET 4.02k +1.2V OR HIGHER SET GND IMONN OUT + GND Pin Versatility of LT3090 – For applications requiring very low output voltages such as below –1V, the minimum input voltage of –1.9V limits how low VIN can drop before the device stops regulating. As shown in Figure 13, this results in a much higher dropout voltage set by the minimum VIN specification rather than the actual dropout of the NPN pass device. 0.1µF RSET 4.02k COUT 4.7µF SET GND VOUT –0.2V MAX IOUT 600mA IMONN OUT + – CIN 4.7µF VIN –1.9V TO –7V CIN 4.7µF VIN –0.7V TO –7V VOUT –0.2V MAX IOUT 600mA LT3090 50µA IN IMONP SHDN ILIM RILIM 10k 3090 F14 Figure 14. Low Dropout Operation for Very Low Output Voltages Note that if the LT3090’s SHDN capability is not desired, then tie the SHDN pin to VIN. However, if it is desired to turn the device ON and OFF, then the SHDN logic signal needs to be referenced to the LT3090’s GND pin. A simple way to achieve this is shown Figure 15, but the GND pin needs to be at least +1.4V. LT3090 50µA 0.1µF IN SHDN COUT 4.7µF IMONP CGND 0.47µF RSET 4.02k COUT 4.7µF +1.4V OR HIGHER ILIM 100k RILIM 10k SET 3090 F13 Figure 13. Generating Very Low Output Voltages A solution to this problem is available from the LT3090 architecture and the flexibility in how its GND pin can be connected. The GND pin does not need to be connected to system ground! It can be connected to a positive voltage as well. If the GND pin of LT3090 is tied to a positive voltage that is at least 1.9V above VIN, then VIN can be GND SHDN IMONN OUT + SHDN (ACTIVE LOW) – CIN 4.7µF VOUT –0.2V MAX IOUT 600mA LT3090 50µA IN VIN –0.7V TO –7V IMONP ILIM RILIM 10k 3090 F15 Figure 15. GND Pin Referenced SHDN Signal 18 3090fa For more information www.linear.com/LT3090 LT3090 Applications Information In summary, the GND pin of LT3090 is highly versatile and can be tied to different places depending on the application’s requirements: a) It can be tied to the system GND for low dropout operation for output voltages greater than –1.6V, b) it can be tied to a positive voltage for low dropout operation for very low output voltages, and c) as illustrated in the Floating 3-Terminal Regulator section, the GND pin can be tied to the OUT pin for very high common mode voltage applications. Direct Paralleling 0.1µF 24.9k 10µF GND SET + – 10µF VIN –3V TO –10V IN 20mil WIDTH* 27.1 2 27.1 13.6 VOUT –2.5V MAX IOUT 1.2A ILIM IMONN 20m OUT SET + – 54.3 IMONP GND Table 2. PC Board Trace Resistance 10mil WIDTH* LT3090 50µA 10k Higher output current is obtained by paralleling multiple LT3090s. Tie all SET pins together and all IN pins together. Connect the OUT pins together using small pieces of PC trace (used as a ballast resistor) to equalize the currents in each LT3090. PC trace resistance in mΩ/inch is shown in Table 2. Ballasting requires only a tiny area. 1 20m OUT SHDN WEIGHT (oz) IMONN LT3090 50µA IN SHDN IMONP ILIM 10k *Trace resistance is measured in mΩ/in 3090 F16 The small worst-case offset of ±2mV for each paralleled LT3090 minimizes the value of required ballast resistance. Figure 16 illustrates that two LT3090s, each using a 20mΩ PCB trace ballast resistor, provide better than 80% output current sharing at full load. The 20mΩ external resistances (10mΩ for the two devices in parallel) only adds 12mV of output regulation drop with a 1.2A maximum load. With an output voltage as low as –1.2V, this only adds 1% to the regulation accuracy. If this additional load regulation error is intolerable, circuits shown in the Typical Applications section highlight how to correct this error using the output current monitor function or the master-slave configuration. Finally, note that more than two LT3090s can be paralleled for higher output current. Paralleling multiple LT3090s is a useful technique for distributing heat on the PCB. For applications with high input-to-output voltage differential, either input series resistors or resistors in parallel with the LT3090s further spread heat. Figure 16. Parallel Devices Thermal Considerations The LT3090 has internal power and thermal limiting circuitry designed to protect it under overload conditions. The typical thermal shutdown temperature is 165°C with about 8°C of hysteresis. For continuous normal load conditions, do not exceed the maximum junction temperature. It is important to consider all sources of thermal resistance from junction to ambient. This includes junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the application dictates. Additionally, consider all heat sources in close proximity to the LT3090. The undersides of the DFN and MSOP packages have exposed metal from the lead frame to the die attachment. Both packages allow heat to directly transfer from the die junction to the PCB metal to limit the maximum operating 3090fa For more information www.linear.com/LT3090 19 LT3090 Applications Information junction temperature. The dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of the PCB. Connect this metal to IN on the PCB. The multiple IN and OUT pins of the LT3090 further assist in spreading heat to the PCB. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PCB and its copper traces. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by power devices. Table 3. Measured Thermal Resistance for DFN Package COPPER AREA BOARD AREA THERMAL RESISTANCE Top Side* Bottom Side 2500mm2 2500mm2 2500mm2 34°C/W 1000mm2 2500mm2 2500mm2 34°C/W 225mm2 2500mm2 2500mm2 35°C/W 100mm2 2500mm2 2500mm2 36°C/W *Device is mounted on topside Table 4. Measured Thermal Resistance for MSOP Package COPPER AREA BOARD AREA THERMAL RESISTANCE Top Side* Bottom Side 2500mm2 2500mm2 2500mm2 33°C/W 1000mm2 2500mm2 2500mm2 33°C/W 225mm2 2500mm2 2500mm2 34°C/W 100mm2 2500mm2 2500mm2 35°C/W *Device is mounted on topside Tables 3 and 4 list thermal resistance as a function of copper area in a fixed board size. All measurements were taken in still air on a 4 layer FR-4 board with 1oz solid internal planes and 2oz top/bottom external trace planes with a total board thickness of 1.6mm. The four layers were electrically isolated with no thermal vias present. PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. For more information on thermal resistance and high thermal conductivity test boards, refer to JEDEC standard JESD51, notably JESD51-7 and JESD51-12. Achieving low thermal resistance necessitates attentions to detail and careful PCB layout. 20 Calculating Junction Temperature Example: Given an output voltage of –2.5V and input voltage of –3.3V ± 5%, output current range from 1mA to 500mA, and a maximum ambient temperature of 85°C, what is the maximum junction temperature? The LT3090’s power dissipation is: IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX) where: IOUT(MAX) = –500mA VIN(MAX) = –3.465V IGND (at IOUT = –500mA and VIN = –3.465V) = –6.5mA Thus: P = (–0.5A) • (–3.465V + 2.5V) + (–6.5mA) • (– 3.465V) = 0.505W Using a DFN package, the thermal resistance is in the range of 34°C/W to 36°C/W depending on the copper area. Therefore, the junction temperature rise above ambient approximately equals: 0.505W • 35°C/W = 18°C The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient: TJMAX = 85°C + 18°C = 103°C Overload Recovery Like many monolithic power regulators, the LT3090 incorporates safe-operating-area (SOA) protection. The SOA protection activates at output-to-input differential voltage greater than 7V. The SOA protection decreases current limit as output-to-input differential increases and keeps the power transistor inside a safe operating region for all values of output-to-input voltage up to the LT3090’s Absolute Maximum Ratings. The LT3090 provides some level of output current for all values of output-to-input differential. Refer to the Current Limit curve in the Typical Performance Characteristics section. When power is first 3090fa For more information www.linear.com/LT3090 LT3090 Applications Information applied and input voltage rises, the output follows the input and keeps the output-to-input differential low to allow the regulator to supply large output current and startup into high current loads. Due to current limit fold back, however, at high input voltages, a problem can occur if the output voltage is low and the load current is high. Such situations occur after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage has already turn ON. The load line for such a load intersects the output current curve at two points. If this happens, the regulator has two stable output operating points. With this double intersection, the input power supply may need to be cycled down to zero and brought back up again to make the output recover. Other LTC negative linear regulators such as the LT3015, LT1964, and LT1175 also exhibit this phenomenon, so it is not unique to the LT3090. with monolithic regulators, such as current limiting and thermal limiting, the device also protects itself against reverse output voltages. Precision current limit and thermal overload protection protect the LT3090 against overload and fault conditions at the device’s output. For normal operation, do not allow the junction temperature to exceed 125°C for E- and I-grades and 150°C for H- and MP-grades. Pulling the LT3090’s output above ground induces no damage to the part. If IN is left open circuited or grounded, OUT can be pulled 36V above GND. In this condition, a maximum current of 7mA flows into the OUT pin and out of the GND pin. If IN is powered by a voltage source, OUT sinks the LT3090’s (fold back) short-circuit current and protects itself by thermal limiting. In this case, however, grounding the SHDN pin turns off the device and stops OUT from sinking the short-circuit current. Protection Features The LT3090 incorporates several protection features that make it ideal for use in battery-powered applications. In addition to the normal protection features associated 3090fa For more information www.linear.com/LT3090 21 LT3090 Typical Applications Parallel Devices 0.1µF LT3090 24.9k 1% 10µF GND SET IMONN OUT 20m + – 10µF VIN –3V TO –10V 50µA IN IMONP SHDN VOUT –2.5V MAX IOUT 1.2A ILIM 10k GND LT3090 SET IMONN OUT 20m + – 50µA IN SHDN IMONP ILIM 10k 3090 TA02 22 3090fa For more information www.linear.com/LT3090 LT3090 Typical Applications Paralleling Devices Using IMONN to Cancel Ballast Resistor Drop CSET 0.1µF RCOMP 10 RCOMP = 1K • RBLST/N 24.9k 1% LT3090 GND SET 20m IMONN OUT 10µF + – 10µF 50µA VOUT = N • 50µA(RSET + RCOMP) IN VIN –3V TO –10V IMONP SHDN VOUT –2.5V MAX IOUT 1.2A ILIM 10k GND LT3090 SET IMONN OUT 20m + – 50µA IN SHDN IMONP ILIM 10k 3090 TA03 Load Sharing without Ballasting (Using IMONP) Master Regulator 0.1µF LT3090 Slave Regulator 24.9k 1% 24.9k 1% 10µF SET GND IMONN IMONN OUT OUT VOUT: –2.5V MAX IOUT: 1.2A + 10µF SET LT3090 + – VIN –3V TO –10V GND 0.1µF – 50µA 50µA IN IN SHDN ILIM IMONP IMONP 10k SHDN ILIM 10k 3090 TA04 2N3904 2N3904 300Ω 300Ω 3090fa For more information www.linear.com/LT3090 23 LT3090 Typical Applications Paralleling Devices without Ballasting (50mA Minimum Load) Master Regulator 24.9k 1% 0.1µF LT3090 SET GND VOUT –2.5V IOUT 1.2A IMONN OUT 20 Slave Regulator + 10µF 20m OUT – 10µF VIN –3V TO –10V 50µA IMONN GND SET + LT3090 IN SHDN – ILIM IMONP 10k 50µA IN ILIM IMONP SHDN 10k 3090 TA05 Using Lower Value RSET for Higher Output Voltages COUT 4.7µF RSET 0.1µF 523Ω 1% 10k 1% LT3090 SET GND IMONN OUT VOUT = –0.5V – 1mA • RSET MAX IOUT: 600mA + – CIN 4.7µF VIN 50µA IN SHDN IMONP ILIM 10k 3090 TA06 24 3090fa For more information www.linear.com/LT3090 LT3090 Typical Applications Constant-Current Constant-Voltage Lab Power Supply 0.1µF RSET LT3090 4.7µF SET GND IMONN OUT VOUT + – 4.7µF 50µA IN VIN IMONP SHDN ILIM RILIM 3090 TA07 Low Dropout Operation for Very Low Output Voltages 0.1µF LT3090 CGND 0.47µF 4.02k 1% +1.2V OR HIGHER SET GND COUT 4.7µF IMONN OUT VOUT: –0.2V MAX IOUT: 600mA + – CIN 4.7µF VIN –0.7V TO –7V 50µA IN SHDN IMONP ILIM 10k 3090 TA08 3090fa For more information www.linear.com/LT3090 25 LT3090 Typical Applications Input Supply Tracking VIN 0.1µF LT3090 100k 1% 4.7µF SET GND VOUT = VIN – 5V MAX IOUT 600mA IMONN OUT + – 50µA 4.7µF IN IMONP SHDN ILIM 10k 3090 TA09 Floating 3-Terminal Regulator (for Arbitrarily High Voltage Applications) 0.1µF LT3090 1M 1% 4.7µF SET 36V GND IMONN OUT + – 4.7µF VIN –52V TO –57V VOUT –50V MAX IOUT 600mA 36V 50µA IN SHDN IMONP ILIM 10k 3090 TA10 26 3090fa For more information www.linear.com/LT3090 LT3090 Typical Applications 500mA LED Driver with Grounded LED Tab (Heatsink) SET GND VIN 500mA 4.02k LT3090 500mA LED Driver with Positive Supply 400m IMONN OUT SET LT3090 + IMONN OUT 400m 4.7µF – 4.7µF 50µA 50µA IN IN VIN GND + 4.7µF – 4.7µF 500mA 4.02k IMONP SHDN ILIM IMONP SHDN ILIM 10k 10k 3090 TA12 3090 TA11 Low Noise Single Inductor Positive-to-Negative Converter 0.1µF 49.9k 1% VIN 12V LT3090 47µF BD VIN RUN/SS RT BOOST SW LT3480 PG D FB SYNC GND 68.1k SET GND IMONN OUT + L 10µH 0.47µF 4.7µF VOUT2 –2.5V MAX IOUT 600mA – 536k 4.7µF VC 50µA IN 18.2k 100k 47µF SHDN 330pF IMONP ILIM 10k –5V D: DIODES INC. DFLS240L L: NEC/TOKIN PLC-0755-100 3090 TA13 3090fa For more information www.linear.com/LT3090 27 LT3090 Typical Applications High Efficiency Low Noise Single Inductor Positive-to-Negative Converter with LDO Input-to-Output Control VIN 12V 47µF BD VIN RUN/SS RT BOOST SW LT3480 PG QP D GND QP 5.36k FB SYNC (500kHz) 68.1k 1% L 10µH 1µF VC 1nF M 47µF 1k 2.2nF LDOOUT – 2V MAX: –5V MIN: –0.8V Z 0.1µF 49.9k 1% LT3090 4.7µF SET GND VOUT –2.5V MAX IOUT 600mA IMONN OUT + – 4.7µF 50µA IN VIN –5V SHDN IMONP ILIM 3090 TA14 10k L: COILCRAFT XAL5050 D: DIODES INC. DFLS230L M: VN2222 QP: 2N3906 Z: 1N5339B (5.6V) 28 3090fa For more information www.linear.com/LT3090 LT3090 Typical Applications 5V to ±2.5V Low Noise Power Supply VIN 5V VIN BD BOOST RUN/SS RT 0.47µF SW LT3480 PG D FB SYNC GND 68.1k 1% fOSC = 500kHz CTRL LT3085 L 10µH 10µA 47µF + 539k – VC 18.2k IN 100k OUT 47µF SET 330pF 249k 1% D: DIODES INC, DFLS240L L: NEC/TOKIN PLC-0755-100 VOUT2 2.5V MAX IOUT 4.7µF 500mA 0.1µF 0.1µF 49.9k 1% LT3090 4.7µF SET GND IMONN OUT + VOUT2 –2.5V MAX IOUT 600mA – 4.7µF 50µA IN VIN –5V SHDN IMONP ILIM 10k 3090 TA15 3090fa For more information www.linear.com/LT3090 29 LT3090 Typical Applications Reference Buffer COUT 4.7µF LT1004-2.5 LT3090 SET GND VOUT –2.5V MAX IOUT 600mA IMONN OUT + – CIN 4.7µF 50µA IN VIN –3V TO –10V SHDN IMONP ILIM 10k 3090 TA16 Coincident Tracking Supplies R1 49.9k 1% LT3090 COUT 4.7µF SET GND IMONN OUT VOUT1, –2.5V 600mA + R2 16.2k 1% – CIN 4.7µF LT3090 50µA VIN –5.5V TO –10V COUT 4.7µF SET IN GND IMONN OUT VOUT2, –3.3V 600mA R3 34k 1% + SHDN IMONP ILIM – 10k LT3090 50µA COUT 4.7µF SET IN GND IMONN OUT VOUT3, –5V 600mA + SHDN IMONP ILIM – 10k 50µA IN SHDN IMONP ILIM 3090 TA17 10k 30 3090fa For more information www.linear.com/LT3090 LT3090 Typical Applications Simple Cable Drop Compensation RCBL2 RCDC = RCBL • 1k 4.7µF LOAD 0.1µF 100k 1% LT3090 SET IMONN GND RCBL1 OUT + RCBL = RCBL1 + RCBL2 – 4.7µF VOUT –5V MAX IOUT 600mA 50µA IN VIN ≤ –6V SHDN ILIM IMONP 10k 3090 TA18 Low Noise 4-Quadrant Power Supply VCC IN CTRL LT3085 4.7µF 10µA + – OUT SET 40m VSET 40m 10µF VOUT (SOURCE/SINK 500mA) VEE + VDROPOUT (LT3090) ≤ VOUT ≤ VCC – VDROPOUT (LT3085) LT3090 SET GND IMONN OUT + – 4.7µF 50µA IN SHDN VEE IMONP 10k ILIM 3090 TA19 3090fa For more information www.linear.com/LT3090 31 LT3090 Typical Applications Two-Terminal Current Source 4.02k, 1% IOUT = 200mV/R1 R1 LT3090 SET GND IMONN OUT + – 50µA IN VIN IMONP SHDN ILIM 10k 10µF 3090 TA20 Positive Output Current Monitor 0.1µF LT3090 TO ADC 49.9k 1% 3.32k 4.7µF SET GND IMONP OUT + VOUT –2.5V MAX IOUT 600mA – 4.7µF 50µA IN VIN –3V TO –10V IMONN 3V ILIM SHDN 0.1µF 10k 3090 TA21 Negative Output Current Monitor 0.1µF LT3090 49.9k 1% 1.67k TO ADC SET GND IMONN OUT + 4.7µF VOUT –2.5V MAX IOUT 600mA – 4.7µF VIN –3V TO –10V 50µA IN SHDN IMONP ILIM 10k 3090 TA22 32 3090fa For more information www.linear.com/LT3090 LT3090 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ±0.10 10 1.65 ±0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 0.00 – 0.05 5 1 (DD) DFN REV C 0310 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3090fa For more information www.linear.com/LT3090 33 LT3090 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 5.10 (.201) MIN 2.845 ±0.102 (.112 ±.004) 0.889 ±0.127 (.035 ±.005) 6 1 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 3.20 – 3.45 (.065 ±.004) (.126 – .136) 12 0.65 0.42 ±0.038 (.0256) (.0165 ±.0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 0.406 ±0.076 (.016 ±.003) REF 12 11 10 9 8 7 DETAIL “A” 0° – 6° TYP 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) GAUGE PLANE 0.53 ±0.152 (.021 ±.006) DETAIL “A” 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 1 2 3 4 5 6 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 34 0.86 (.034) REF 0.1016 ±0.0508 (.004 ±.002) MSOP (MSE12) 0213 REV G 3090fa For more information www.linear.com/LT3090 LT3090 Revision History REV DATE DESCRIPTION A 01/14 Modified Ripple Rejection test condition PAGE NUMBER 3 Added units to internal Current Limit spec 3 Modified ISET Thermal Regulation test condition 4 Modified Load Sharing without Ballasting application circuit 23 Modified Coincident Tracking Supplies application circuit 30 Modified Parallel Devices application circuit 36 3090fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LT3090 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LT3090 Typical Application Parallel Devices 0.1µF LT3090 24.9k 1% 10µF SET GND IMONN OUT 20m + VOUT –2.5V MAX IOUT 1.2A – 10µF 50µA IN VIN –3V TO –10V IMONP SHDN ILIM 10k GND LT3090 SET IMONN OUT 20m + – 50µA IN SHDN IMONP ILIM 10k 3090 TA23 Related Parts PART NUMBER DESCRIPTION COMMENTS LT1185 3A, Negative Linear Regulator 750mV Dropout Voltage, VIN = –6V to –16V, DD-PAK and TO-220 Packages LT1175 500mA, Negative Low Dropout Micropower Regulator 500mV Dropout Voltage, VIN = –4.5V to –20V, N8, S8, DD-PAK, TO-220 and SOT-223 LT1964 200mA, Negative Low Noise Low Dropout Regulator 340mV Dropout Voltage, Low Noise: 30µVRMS, VIN = –1.9V to –20V, DFN and SOT-23 Packages LT3015 1.5A, Fast Transient Response, Negative LDO Regulator 310mV Dropout Voltage, Low Noise: 60µVRMS, VIN = –2.3V to –30V, DFN, MSOP, TO-220 and SOT-223 Packages LT3080 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN, MSOP, TO-220 and DD Packages LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator 275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN, MSOP, TO-220 and DD Packages LT3082 200mA, Parallelable, Low Noise, Low Dropout Linear Regulator Low Noise: 33µVRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN, SOT-223 and SOT-23 Packages LT3081 1.5A, Parallelable, Low Noise, Low Dropout Linear Regulator Low Noise: 33µVRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN, FE, DD-PAK and TO-220 Packages LT3083 3A, Parallelable, Low Noise, Low Dropout Linear Regulator 310mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN, MSOP, TO-220 and DD Packages 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT3090 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3090 3090fa LT 0114 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013