Data Sheet

IP3088CX5; IP3088CX10;
IP3088CX15; IP3088CX20
Integrated 2, 4, 6 and 8-channel passive LC-filter network with
ESD protection to IEC 61000-4-2 level 4
Rev. 01 — 12 February 2010
Product data sheet
1. Product profile
1.1 General description
IP3088CX5, IP3088CX10, IP3088CX15 and IP3088CX20 is a 2, 4, 6 and 8-channel LC
low-pass filter array family which is designed to provide filtering of undesired RF signals
on the I/O ports of portable communication or computing devices. In addition, IP3088CX5,
IP3088CX10, IP3088CX15 and IP3088CX20 incorporates diodes to provide protection to
downstream components from ElectroStatic Discharge (ESD) voltages as high as ±15 kV
according IEC 61000-4-2 level 4.
The devices are fabricated using monolithic silicon technology and integrate and
incorporate up to 16 coils and 24 diodes in a 0.5 mm pitch Wafer-Level Chip-Scale
Package (WLCSP).
1.2 Features and benefits
„
„
„
„
Pb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant)
Integrated 2, 4, 6 and 8-channel π-type LC-filter network
18 Ω channel series resistance; ≤ 45 pF (at 2.5 V DC) channel capacitance
Integrated ESD protection withstanding ±15 kV contact discharge, far exceeding
IEC 61000-4-2 level 4
„ ESD protection to ±30 kV contact discharge, per MIL-STD-883D, Method 3 015
„ WLCSP with 0.5 mm pitch
1.3 Applications
„ Cellular and Personal Communication System (PCS) mobile handsets
„ Cordless telephones
„ Wireless data (WAN/LAN) systems and PDAs
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
2. Pinning information
2.1 Pinning
bump A1
index area
bump A1
index area
1
2
1
A
B
2
3
A
B1
B1
B
C
B2
C
001aak061
001aak062
transparent top view,
solder balls facing down
Fig 1.
4
transparent top view,
solder balls facing down
Pin configuration IP3088CX5
Fig 2.
bump A1
index area
Pin configuration IP3088CX10
bump A1
index area
1
2
3
4
5
1
6
A
2
3
4
5
6
7
A
B1
B
B2
B3
B1
B
C
B2
B3
B4
C
001aak063
001aak064
transparent top view,
solder balls facing down
Fig 3.
8
transparent top view,
solder balls facing down
Pin configuration IP3088CX15
Fig 4.
Pin configuration IP3088CX20
2.2 Pin description
Table 1.
Pinning
Pin
Description
IP3088CX5
IP3088CX10
IP3088CX15
IP3088CX20
A1 and C1
A1 and C1
A1 and C1
A1 and C1
filter channel 1
A2 and C2
A2 and C2
A2 and C2
A2 and C2
filter channel 2
-
A3 and C3
A3 and C3
A3 and C3
filter channel 3
-
A4 and C4
A4 and C4
A4 and C4
filter channel 4
-
-
A5 and C5
A5 and C5
filter channel 5
-
-
A6 and C6
A6 and C6
filter channel 6
-
-
-
A7 and C7
filter channel 7
-
-
-
A8 and C8
filter channel 8
B1
B1 and B2
B1, B2 and B3
B1, B2, B3 and B4
ground
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
2 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
3. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
IP3088CX5
WLCSP5
wafer level chip-size package; 5 bumps; 0.96 × 1.28 × 0.65 mm
IP3088CX5
IP3088CX10
WLCSP10
wafer level chip-size package; 10 bumps; 1.96 × 1.28 × 0.65 mm
IP3088CX10
IP3088CX15
WLCSP15
wafer level chip-size package; 15 bumps; 2.96 × 1.28 × 0.65 mm
IP3088CX15
IP3088CX20
WLCSP20
wafer level chip-size package; 20 bumps; 3.96 × 1.28 × 0.65 mm
IP3088CX20
4. Functional diagram
A1 to A8
C1 to C8
B1 to B4
Fig 5.
008aaa184
Schematic diagram IP3088CX5; IP3088CX10; IP3088CX15; IP3088CX20
5. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VCC
supply voltage
VESD
electrostatic discharge voltage
Min
Max
Unit
−0.5
+5.6
V
all pins to ground
contact discharge
[1]
−15
+15
kV
air discharge
[1]
−15
+15
kV
contact discharge
−8
+8
kV
air discharge
−15
+15
kV
MIL-STD-883D (method 3 015)
HBM contact discharge
−30
+30
kV
per inductor; Tamb = 85 °C
-
30
mA
IEC 61000-4-2 level 4; all pins
to ground
Ich
channel current (DC)
Tstg
storage temperature
−65
+150
°C
Tamb
ambient temperature
−40
+85
°C
[1]
Device is qualified with 1 000 pulses of ±15 kV contact discharges each, according to the IEC 61000-4-2 model and far exceeds the
specified level 4 (8 kV contact discharge).
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
3 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
6. Characteristics
Table 4.
Channel characteristics
Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
Rs(ch)
channel series resistance
Ls(ch)
channel series inductance
Cch
channel capacitance
Min
Typ
Max
Unit
-
18
-
Ω
-
40
-
nH
Vbias(DC) = 0 V;
f = 100 kHz
[1]
-
65
-
pF
Vbias(DC) = 2.5 V;
f = 100 kHz
[1]
-
42
-
pF
VBR
breakdown voltage
positive clamp;
Itest = 1 mA
5.8
-
10
V
VF
forward voltage
negative clamp;
IF = −1 mA
−1.5
-
−0.4
V
ILR
reverse leakage current
per channel; VI = 3.5 V
-
-
0.1
μA
Min
Typ
Max
Unit
800 MHz < f < 1.5 GHz
-
40
-
dB
1.5 GHz < f < 3.0 GHz
-
33
-
dB
-
175
-
MHz
[1]
Guaranteed by design.
Table 5.
Frequency characteristics
Tamb = 25 °C; unless otherwise specified.
Symbol Parameter
Conditions
αil
Rgen = 50 Ω; RL = 50 Ω
f−3dB
insertion loss
cut-off frequency
Rgen = 50 Ω; RL = 50 Ω;
Vbias(DC) = 0 V;
αil at 1 MHz − 3 dB
7. Application information
7.1 Insertion loss
IP3088CX5, IP3088CX10, IP3088CX15 and IP3088CX20 is mainly designed as an
ElectroMagnetic Interference (EMI) and Radio Frequency Interference (RFI) filter for
Subscriber Identity Module (SIM) card interfaces.
The setup for measuring insertion loss in a 50 Ω system is shown in Figure 6.
IN
DUT
OUT
50 Ω
50 Ω
TEST BOARD
Vgen
001aai755
Fig 6.
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
Frequency response measurement configuration
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
4 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
As an example, the measured insertion loss magnitude for all channels of the
IP3088CX10 are shown in Figure 7.
001aak295
0
s21
(dB)
001aak296
0
s21
(dB)
−10
−10
−20
−20
−30
−30
−40
−40
−50
1
10
102
103
104
−50
1
10
102
103
f (MHz)
a. Channel 1 (pins A1 and C1)
b. Channel 2 (pins A2 and C2)
001aak294
0
s21
(dB)
001aak297
0
s21
(dB)
−10
−10
−20
−20
−30
−30
−40
−40
−50
1
10
102
103
104
−50
1
10
102
f (MHz)
c. Channel 3 (pins A3 and C3)
Fig 7.
104
f (MHz)
103
104
f (MHz)
d. Channel 4 (pins A4 and C4)
Measured insertion loss magnitude
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
5 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
8. Package outline
WLCSP20: wafer level chip-size package; 20 bumps (8-4-8)
D
bump A1
index area
A2
E
A
A1
detail X
e
1/2 e
b
C
e1
B1
B
B2
B3
B4
e2
A
1
2
3
4
5
6
7
8
e3
X
European
projection
wlcsp20_8-4-8_po
Fig 8.
Table 6.
Package outline IP3088CX20 (WLCSP20)
Dimensions for Figure 8
Symbol
Min
Typ
Max
Unit
A
0.60
0.65
0.70
mm
A1
0.22
0.24
0.26
mm
A2
0.38
0.41
0.44
mm
b
0.27
0.32
0.37
mm
D
3.91
3.96
4.01
mm
E
1.23
1.28
1.33
mm
e
-
0.5
-
mm
e1
-
0.435
-
mm
e2
-
0.87
-
mm
e3
-
1.0
-
mm
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
6 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
WLCSP15: wafer level chip-size package; 15 bumps (6-3-6)
D
bump A1
index area
A2
E
A
A1
detail X
e
1/2 e
b
C
e1
B1
B
B2
B3
e2
A
1
2
3
4
5
6
e3
X
European
projection
wlcsp15_6-3-6_po
Fig 9.
Table 7.
Package outline IP3088CX15 (WLCSP15)
Dimensions for Figure 9
Symbol
Min
Typ
Max
Unit
A
0.60
0.65
0.70
mm
A1
0.22
0.24
0.26
mm
A2
0.38
0.41
0.44
mm
b
0.27
0.32
0.37
mm
D
2.91
2.96
3.01
mm
E
1.23
1.28
1.33
mm
e
-
0.5
-
mm
e1
-
0.435
-
mm
e2
-
0.87
-
mm
e3
-
1.0
-
mm
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
7 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
WLCSP10: wafer level chip-size package; 10 bumps (4-2-4)
D
bump A1
index area
A2
E
A
A1
detail X
e
b
C
e1
B1
B
B2
e2
A
1
2
3
4
e3
X
1/2 e
European
projection
wlcsp10_4-2-4_po
Fig 10. Package outline IP3088CX10 (WLCSP10)
Table 8.
Dimensions for Figure 10
Symbol
Min
Typ
Max
Unit
A
0.60
0.65
0.70
mm
A1
0.22
0.24
0.26
mm
A2
0.38
0.41
0.44
mm
b
0.27
0.32
0.37
mm
D
1.91
1.96
2.01
mm
E
1.23
1.28
1.33
mm
e
-
0.5
-
mm
e1
-
0.435
-
mm
e2
-
0.87
-
mm
e3
-
1.0
-
mm
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
8 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
WLCSP5: wafer level chip-size package; 5 bumps (2-1-2)
D
bump A1
index area
A2
E
A
A1
detail X
e
1/2 e
b
C
e1
B1
B
e2
A
1
2
X
European
projection
wlcsp5_2-1-2_po
Fig 11. Package outline IP3088CX5 (WLCSP5)
Table 9.
Dimensions for Figure 11
Symbol
Min
Typ
Max
Unit
A
0.60
0.65
0.70
mm
A1
0.22
0.24
0.26
mm
A2
0.38
0.41
0.44
mm
b
0.27
0.32
0.37
mm
D
0.91
0.96
1.01
mm
E
1.23
1.28
1.33
mm
e
-
0.5
-
mm
e1
-
0.435
-
mm
e2
-
0.87
-
mm
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
9 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
9. Soldering of WLCSP packages
9.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
9.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
9.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a PbSn process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 10.
Table 10.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2 000
> 2 000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
10 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
9.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
9.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
9.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
11 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
9.3.4 Cleaning
Cleaning can be done after reflow soldering.
10. Abbreviations
Table 11.
Abbreviations
Acronym
Description
DUT
Device Under Test
EMI
ElectroMagnetic Interference
ESD
ElectroStatic Discharge
HBM
Human Body Model
LAN
Local Area Network
PCB
Printed-Circuit Board
PCS
Personal Communication System
PDA
Personal Digital Assistant
RFI
Radio Frequency Interference
RoHS
Restriction of Hazardous Substances
SIM
Subscriber Identity Module
WAN
Wide Area Network
WLCSP
Wafer-Level Chip-Scale Package
11. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
IP3088CX5_CX10_CX15_CX20_1
20100212
Product data sheet
-
-
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
12 of 15
IP3088CX5/CX10/CX15/CX20
NXP Semiconductors
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
12.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Non-automotive qualified products — Unless the data sheet of an NXP
Semiconductors product expressly states that the product is automotive
qualified, the product is not suitable for automotive use. It is neither qualified
nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
13 of 15
NXP Semiconductors
IP3088CX5/CX10/CX15/CX20
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
IP3088CX5_CX10_CX15_CX20_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
© NXP B.V. 2010. All rights reserved.
14 of 15
NXP Semiconductors
IP3088CX5/CX10/CX15/CX20
2, 4, 6 and 8-channel passive LC-filter network with ESD protection
14. Contents
1
1.1
1.2
1.3
2
2.1
2.2
3
4
5
6
7
7.1
8
9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
10
11
12
12.1
12.2
12.3
12.4
13
14
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Application information. . . . . . . . . . . . . . . . . . . 4
Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6
Soldering of WLCSP packages. . . . . . . . . . . . 10
Introduction to soldering WLCSP packages . . 10
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 10
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 10
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Quality of solder joint . . . . . . . . . . . . . . . . . . . 11
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 February 2010
Document identifier: IP3088CX5_CX10_CX15_CX20_1