HI-5700/883 ® N OT May 1997 REC ED END M M O FO IG DES EW N R NS 8-Bit, 20 MSPS Flash A/D Converter Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HI-5700/883 is a monolithic, 8-bit, CMOS Flash Analogto-Digital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 20 MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5700/883 delivers ±0.5 LSB differential nonlinearity while consuming only 725mW (typical) at 20 MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 9-bit resolution. • 20 MSPS with No Missing Codes • 18MHz Full Power Input Bandwidth • No Missing Codes Over Temperature • Sample and Hold Not Required • Single +5V Supply Voltage • CMOS/TTL • Overflow Bit Applications Ordering Information • Video Digitizing • Radar Systems • Medical Imaging • Communication Systems PART NUMBER TEMPERATURE RANGE HI1-5700S/883 -55oC to +125oC PACKAGE 28 Lead CerDIP • High Speed Data Acquisition Systems Functional Block Diagram HI-5700/883 (28 LEAD CERDIP) TOP VIEW ∅1 ∅2 VIN 28 VREF + 17 28 VIN R 27 VREF - R D6 3 26 AVDD D5 4 25 AGND D4 5 24 AGND 1/4R 6 23 AVDD VDD 7 22 1/2R GND 8 3/4R 9 21 AVDD 20 AGND D3 10 19 AGND D2 11 18 AVDD D1 12 17 VREF + D0 13 16 CE1 OVF 14 15 CE2 ∅1 3/4R 9 D Q CL COMP 256 R R 1/2R 22 R R COMP 193 COMP 129 1/4R 6 R R R VREF - 27 ∅2 R/2 D7 2 CLK 1 ∅1 COMP 65 COMPARATOR LATCHES AND ENCODER LOGIC Pinout COMP 2 R/2 OVERFLOW 14 (OVF) D Q CL 2 D7 (MSB) D Q CL 3 D6 D Q CL 4 D5 D Q CL 5 D4 D Q CL 10 D3 D Q CL 11 D2 D Q CL 12 D1 D Q CL 13 D0 (LSB) COMP 1 16 CE1 15 CE2 ∅1 CLK 1 ∅2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 6-8 VDD 7 GND 8 AVDD 23 21 26 18 AGND 24 25 19 20 Spec Number File Number 512023 3286.1 HI-5700/883 Pin Descriptions Chip Enable Truth Table PIN # NAME DESCRIPTION 1 CLK 2 D7 Bit 7, Output (MSB) 3 D6 Bit 6, Output 4 D5 Bit 5, Output 5 D4 Bit 4, Output 6 1/4R 1/4th Point of Reference Ladder 7 VDD Digital Power Supply 8 GND Digital Ground 9 3/4R 3/4th Point of Reference Ladder 10 D3 Bit 3, Output 11 D2 Bit 2, Output 12 D1 Bit 1, Output 13 D0 Bit 0, Output (LSB) 14 OVF Overflow, Output 15 CE2 Three-State Output Enable Input, Active High. (See Truth Table) 16 CE1 Three-State Output Enable Input, Active Low. (See Truth Table)) 17 VREF + Reference Voltage Positive Input 18 AVDD Analog Power Supply, +5V 19 AGND Analog Ground 20 AGND Analog Ground 21 AVDD Analog Power Supply, +5V 22 1/2R 1/2 Point of Reference Ladder 23 AVDD Analog Power Supply, +5V 24 AGND Analog Ground 25 AGND Analog Ground 26 AVDD Analog Power Supply, +5V 27 VREF - Reference Voltage Negative Input 28 VIN Clock Input D0 - D7 CE1 CE2 OVF 0 1 Valid Valid 1 1 Three-State Valid X 0 Three-State Three-State X = Don’t Care. Analog Input Spec Number 6-9 512023 Specifications HI-5700/883 Absolute Maximum Ratings Thermal Information Supply Voltage, V DD to GND . . . . . . . . . (GND - 0.5) < VDD < +7.0V Analog and Reference Input Pins. .(VSS - 0.5) < VINA < (VDD +0.5V) Digital I/O Pins . . . . . . . . . . . . . . . (GND - 0.5) < VI/O < (VDD +0.5V) Operating Temperature Range HI1-5700S/883 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Storage Temperature Range . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300oC ESD Clasification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC HI1-5700S/883 . . . . . . . . . . . . . . . . . . . . 470C/W 28oC/W Power Dissipation at +75oC (Note 1) HI1-5700S/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100mW Power Dissipation Derating Factor Above +75oC HI1-5700S/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21mW/oC Reliabiliy Information Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14677 Worst Case Density . . . . . . . . . . . . . . . . . . . . . . . . 3.05 x 104A/cm2 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: AVDD = VDD = +5.0V; VREF + = +4.0V; VREF - = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. PARAMETERS LIMITS SYMBOL CONDITIONS GROUP A SUBGROUP INL FS = 15MHz, fIN = DC 1 +25oC - ±2.0 LSB 2, 3 +125oC, -55oC - ±2.65 LSB 1 +25oC - ±2.25 LSB 2, 3 +125oC, -55oC - ±4.1 LSB 1 +25oC - ±0.9 LSB 2, 3 +125oC, -55oC - ±1.0 LSB 1 +25oC - ±0.9 LSB 2, 3 +125oC, -55oC - ±1.0 LSB 1 +25oC - ±8.0 LSB 2, 3 +125oC, -55oC - ±9.5 LSB 1 +25oC - ±8.0 LSB 2, 3 +125oC, -55oC - ±9.5 LSB 1 +25oC - ±4.5 LSB 2, 3 +125oC, -55oC - ±8.0 LSB 1 +25oC - ±4.5 LSB 2, 3 +125oC, -55oC - ±8.0 LSB 1 +25oC 4 - MΩ 2, 3 +125oC, -55oC 4 - MΩ 1 +25oC ±1.0 µA 2, 3 +125oC, -55oC ±1.0 µA 1 +25oC 250 - Ω 2, 3 +125oC, -55oC 235 - Ω TEMPERATURE MIN MAX UNIT ACCURACY Integral Linearity Error (Best Fit Method) FS = 20MHz, fIN = DC Differential Linearity Error (Guaranteed No Missing Codes) DNL FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC Offset Error (Adjustable to Zero) VOS FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC Full Scale Error (Adjustable to Zero) FSE FS = 15MHz, fIN = DC FS = 20MHz, fIN = DC ANALOG INPUT Analog Input Resistance Analog Input Bias Current RIN IB VIN = 4V VIN = 0V, 4V REFERENCE INPUT Total Reference Resistance RL Spec Number 6-10 512023 Specifications HI-5700/883 TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: AVDD = VDD = +5.0V; VREF + = +4.0V; VREF - = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. PARAMETERS SYMBOL CONDITIONS LIMITS GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT 1 +25oC 2.0 - V 2, 3 +125oC, -55oC 2.0 - V 1 +25oC - 0.8 V 2, 3 +125oC, -55oC - 0.8 V 1 +25oC - ±1 µA 2, 3 +125oC, -55oC - ±1 µA 1 +25oC - ±1.0 µA 2, 3 +125oC, -55oC - ±1.0 µA 1 +25oC -3.2 - mA 2, 3 +125oC, -55oC -3.2 - mA 1 +25oC 3.2 - mA 2, 3 +125oC, -55oC 3.2 - mA 1 +25oC - ±2.75 LSB 2, 3 +125oC, -55oC - ±5.5 LSB 1 +25oC - ±2.75 LSB 2, 3 +125oC, -55oC - ±5.5 LSB 1 +25oC - 180 mA 2, 3 +125oC, -55oC - 190 mA DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Logic Input Current IIN VIN = 0V, +5V DIGITAL OUTPUTS Output Leakage IOZ Output Logic Source Current Output Logic Sink Current IOH IOL CE2 = 0V, VO = 0V, 5V VO = 4.5V VO = 0.4V POWER SUPPLY REJECTION ∆VOS Offset Error PSRR ∆FSE Gain Error PSRR VDD = 5V ±10% VDD = 5V ±10% POWER SUPPLY CURRENT Supply Current IDD FS = 20MHz NOTE: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: AVDD = VDD = +5.0V; VREF + = +4.0V; VREF - = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETER SYMBOL Maximum Conversion Rate Data Output Enable Time CONDITIONS No Missing Codes tEN GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT 9 +25oC 20 - MSPS 10, 11 +125oC, -55oC 20 - MSPS 9 +25oC - 25 ns 10, 11 +125oC, -55oC - 30 ns Spec Number 6-11 512023 Specifications HI-5700/883 TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) AVDD = VDD = +5.0V; VREF + = +4.0V; VREF - = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. Device Tested at: LIMITS PARAMETER SYMBOL Data Output Disable Time Data Output Delay CONDITIONS tDIS tOD Data Output Hold tH GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT 9 +25oC - 20 ns 10, 11 +125oC, -55oC - 25 ns 9 +25oC - 25 ns 10, 11 +125oC, -55oC - 30 ns 9 +25oC 10 - ns 10, 11 +125oC, -55oC 5 - ns TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) Device Characterized at: AVDD = VDD = +5.0V; VREF + = +4.0V; VREF - = GND = AGND = 0V; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETER SYMBOL CONDITIONS Minimum Conversion Rate No Missing Codes TEMPERATURE MIN MAX UNIT +25oC, +125oC, -55oC - 0.125 MSPS NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 1), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C & D Endpoints 1 NOTE: 1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA. Spec Number 6-12 512023 HI-5700/883 Die Characteristics DIE DIMENSIONS: 154.3 x 173.2 x 19 ± 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ DIE ATTACH: Material: Gold Silicon Eutectic Alloy Temperature: Ceramic DIP - 460oC (Max) WORST CASE CURRENT DENSITY: 3.05 x 104 A/cm 2 Metallization Mask Layout 1 28 27 AVDD CLK 2 VREF - D7 3 VIN D6 4 26 5 GND 8 GND 8 3/4R 9 D3 10 25 AGND 24 AGND 23 AVDD 22 1/2R 21 AVDD 20 AGND 19 11 12 13 14 15 16 17 VREF + 7 CE1 VDD CE2 7 OVF VDD D0 6 D1 1/4R D2 D4 D5 HI-5700/883 18 AGND AVDD Spec Number 6-13 512023 Specifications HI-5700/883 Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK INPUT SAMPLE N- 2 AUTO BALANCE tAB SAMPLE N-1 AUTO BALANCE ANALOG INPUT SAMPLE N AUTO BALANCE SAMPLE N+ 1 AUTO BALANCE ENCODER DATA IS LATCHED INTO THE OUTPUT REGISTERS SAMPLE N+2 tAP tH tAJ tOD DATA OUTPUT DATA N-4 DATA N-3 DATA N-2 DATA N-1 DATA N FIGURE 1. INPUT-TO-OUTPUT TIMING CE1 CE2 tEN tDIS D0 - D7 OVF DATA HIGH IMPEDANCE DATA tDIS DATA tEN HIGH IMPEDANCE HIGH IMPEDANCE DATA DATA FIGURE 2. OUTPUT ENABLE TIMING Spec Number 6-14 512023 HI-5700/883 Burn-In Circuit HI-5700/883 CERAMIC DIP +5.5V 1:10 DUTY CYCLE 100kHz; 0 < V< 5 VOLTS 0.01µF 1µF GND CLK 2 D7 VREF- 27 3 D6 AVDD 26 4 D5 AGND 25 5 D4 AGND 24 6 1/4R AVDD 23 7 DVDD 1/2R 22 8 DGND AVDD 21 9 3/4R AGND 20 10 D3 TRIANGLE-WAVEFORM; fIN = 12.5kHz VIN 28 1 AGND 19 11 D2 AVDD 18 12 D1 VREF+ 17 13 D0 CE1 16 14 OVF CE2 15 0.01µF 1µF GND GND Spec Number 6-15 512023