HI-5701/883 6-Bit, 30 MSPS Flash A/D Converter June 1994 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HI-5701/883 is a monolithic, 6-bit, CMOS Flash Analogto-Digital Converter. It is designed for high speed applications where wide bandwidth and low power consumption are essential. Its 30 MSPS speed is made possible by a parallel architecture which also eliminates the need for an external sample and hold circuit. The HI-5701/ 883 delivers ±0.7 LSB differential nonlinearity while consuming only 250mW (typical) at 30 MSPS. Microprocessor compatible data output latches are provided which present valid data to the output bus 1.5 clock cycles after the convert command is received. An overflow bit is provided to allow the series connection of two converters to achieve 7-bit resolution. • 30 MSPS with No Missing Codes • 20MHz Full Power Input Bandwidth • No Missing Codes Over Temperature • Sample and Hold Not Required • Single +5V Supply Voltage • CMOS/TTL • Overflow Bit Ordering Information Applications TEMPERATURE RANGE • Video Digitizing PART NUMBER PACKAGE • Radar Systems -55oC to +125oC HI1-5701T/883 • Medical Imaging 18 Lead CerDIP • Communication Systems • High Speed Data Acquisition Systems Functional Block Diagram HI-5701/883 (18 LEAD CERDIP) TOP VIEW D5 (MSB) 1 18 D4 OVF 2 17 D3 VSS 3 15 D2 CE2 5 14 D1 CE1 6 13 D0 (LSB) PHASE 8 VREF + 9 VIN 11 VREF + 9 ∅1 ∅1 R/2 COMP 64 R 16 1/2R NC 4 CLK 7 ∅1 ∅2 R COMP 63 R 1/2R 16 R COMP 32 R 12 VDD 11 VIN COMP 2 R 10 VREF - COMPARATOR LATCHES AND ENCODER LOGIC Pinout VREF - 10 ∅2 D CL Q OVERFLOW 2 (OVF) D CL Q 1 D5 (MSB) D CL Q 3 D4 D CL Q 4 D3 D CL Q 5 D2 D CL Q 10 D1 D CL Q 11 D0 (LSB) R/2 COMP 1 16 CE1 15 CE2 VDD 12 CLK 7 2 (SAMPLE) PHASE 8 1 (AUTO BALANCE) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 6-1 VSS 3 512031 File Number 3378 Spec Number HI-5701/883 Pin Description PIN # NAME DESCRIPTION 1 D5 2 OVF Overflow, Output 3 VSS Digital Ground 4 NC No Connection 5 CE2 Three-State Output Enable Input, Active high (See Truth Table) 6 CE1 Three-State Output Enable Input, Active Low (See Truth Table) 7 CLK Clock Input 8 PHASE Sample Clock Phase Control Input. When Phase is Low, Sample Unknown (φ1) occurs when the Clock is Low and Auto Balance (φ2) occurs when the Clock is High (See Phase Control Table) 9 VREF + Reference Voltage Positive Input 10 VREF - Reference Voltage Negative Input 11 VIN Analog Signal Input 12 VDD Power Supply, +5V 13 D0 Bit 1, Output (LSB) 14 D1 Bit 2, Output 15 D2 Bit 3, Output 16 1/2R 17 D3 Bit 4, Output 18 D4 Bit 5, Output Bit 6, Output (MSB) Reference Ladder Midpoint Chip Enable Truth Table Phase Control D0 - D5 CE1 CE2 0 1 Valid 1 1 X 0 OVF CLOCK PHASE Valid 0 0 Sample Unknown (φ2) Three-State Valid 0 1 Auto Balance (φ1) Three-State Three-State 1 0 Auto Balance (φ1) 1 1 Sample Unknown (φ2) X = Don’t Care. INTERNAL GENERATION Spec Number 6-2 512031 Specifications HI-5701/883 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD to VSS . . . . . . . . . . . (VSS - 0.5) < VDD < +7.0V Analog and Reference Input Pins. .(VSS - 0.5) < VINA < (VDD +0.5V) Digital I/O Pins . . . . . . . . . . . . . . . . (VSS - 0.5) < VI/O < (VDD +0.5V) Operating Temperature Range HI1-5701T/883 . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Storage Temperature Range . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . 300oC ESD Clasification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . 700C/W 28oC/W Power Dissipation at +75oC (Note 1) HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4mW Power Dissipation Derating Factor Above +75oC HI1-5701T/883. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14mW/oC Reliability Information Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4815 Worst Case Density . . . . . . . . . . . . . . . . . . . . . . . . 3.05 x 104A/cm2 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETERS SYMBOL CONDITIONS GROUP A SUBGROUP INL FS = 20MHz, fIN = DC 1 +25oC - ±1.25 LSB 2, 3 +125oC, -55oC - ±2.0 LSB 1 +25oC - ±1.5 LSB 2, 3 +125oC, -55oC - ±2.5 LSB 1 +25oC - ±0.6 LSB 2, 3 +125oC, -55oC - ±0.75 LSB 1 +25oC - ±0.75 LSB 2, 3 +125oC, -55oC - ±1.0 LSB 1 +25oC - ±2.0 LSB 2, 3 +125oC, -55oC - ±2.5 LSB 1 +25oC - ±2.0 LSB 2, 3 +125oC, -55oC - ±2.5 LSB 1 +25oC 4 - MΩ 2, 3 +125oC, -55oC 4 - MΩ 1 +25oC ±1.0 µA 2, 3 +125oC, -55oC ±1.0 µA 1 +25oC 250 - Ω 2, 3 +125oC, -55oC 235 - Ω TEMPERATURE MIN MAX UNIT ACCURACY Integral Linearity Error (Best Fit Method) FS = 30MHz, fIN = DC Differential Linearity Error (Guaranteed No Missing Codes) DNL FS = 20MHz, fIN = DC FS = 30MHz, fIN = DC Offset Error (Adjustable to Zero) Full Scale Error (Adjustable to Zero) VOS FSE FS = 20MHz, fIN = DC FS = 20MHz, fIN = DC ANALOG INPUT Analog Input Resistance Analog Input Bias Current RIN IB VIN = 4V VIN = 0V, 4V REFERENCE INPUT Total Reference Resistance RL Spec Number 6-3 512031 Specifications HI-5701/883 TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETERS SYMBOL CONDITIONS GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT 1 +25oC 2.0 - V 2, 3 +125oC, -55oC 2.0 - V 1 +25oC - 0.8 V 2, 3 +125oC, -55oC - 0.8 V 1 +25oC - ±1 µA 2, 3 +125oC, -55oC - ±1 µA 1 +25oC - ±1.0 µA 2, 3 +125oC, -55oC - ±1.0 µA 1 +25oC -3.2 - mA 2, 3 +125oC, -55oC -3.2 - mA 1 +25oC 3.2 - mA 2, 3 +125oC, -55oC 3.2 - mA 1 +25oC - ±1.0 LSB 2, 3 +125oC, -55oC - ±1.5 LSB 1 +25oC - ±1.0 LSB 2, 3 +125oC, -55oC - ±1.5 LSB 1 +25oC - 60 mA 2, 3 +125oC, -55oC - 75 mA DIGITAL INPUTS Input High Voltage Input Low Voltage Logic Input Current VIH VIL IIN VIN = 0V, +5V DIGITAL OUTPUTS Output Leakage Output Logic Source Current Output Logic Sink Current IOZ IOH IOL CE2 = 0V, VO = 0V, 5V VO = 4.5V VO = 0.4V POWER SUPPLY REJECTION Offset Error PSRR Gain Error PSRR ∆VOS ∆FSE VDD = 5V ±10% VDD = 5V ±10% POWER SUPPLY CURRENT Supply Current IDD FS = 30MHz NOTE: 1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. Spec Number 6-4 512031 Specifications HI-5701/883 TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETER SYMBOL CONDITIONS Maximum Conversion Rate Data Output Enable Time Data Output Disable Time Data Output Delay No Missing Codes tEN tDIS tOD Data Output Hold tH GROUP A SUBGROUP TEMPERATURE MIN MAX UNIT 9 +25oC 30 - MSPS 10, 11 +125oC, -55oC 30 - MSPS 9 +25oC - 20 ns 10, 11 +125oC, -55oC - 20 ns 9 +25oC - 20 ns 10, 11 +125oC, -55oC - 20 ns 9 +25oC - 20 ns 10, 11 +125oC, -55oC - 20 ns 9 +25oC 10 - ns 10, 11 +125oC, -55oC 5 - ns TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) Device Characterized at: VDD = +5.0V; VREF + = +4.0V; VREF - = VSS = GND; FS = Specified Clock Frequency at 50% Duty Cycle; CL = 30pF; Unless Otherwise Specified. LIMITS PARAMETER SYMBOL CONDITIONS Minimum Conversion Rate No Missing Codes TEMPERATURE MIN MAX UNIT +25oC, +125oC, -55oC - 0.125 MSPS NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 AND 2) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 1), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C and D Endpoints 1 NOTE: 1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA. Spec Number 6-5 512031 HI-5701/883 Die Characteristics DIE DIMENSIONS: 2220µm x 3320µm x 19 ± 1mils METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ DIE ATTACH: Material: Gold Silicon Eutectic Alloy Temperature: Ceramic DIP - 460oC (Max) WORST CASE CURRENT DENSITY: 3.05 x 104 A/cm2 Metallization Mask Layout D3 D4 D5 VSS OVF HI-5701/883 VSS 1/2R D2 CE2 D1 D0 VDD VDD VIN VREF - VREF + PHASE CLK CE1 Spec Number 6-6 512031 HI-5701/883 Timing Waveforms CLOCK INPUT PHASE - HIGH CLOCK INPUT PHASE - LOW COMPARATOR DATA IS LATCHED ∅1 ∅2 SAMPLE N-2 ∅1 ∅2 AUTO BALANCE tAB SAMPLE N-1 ∅2 AUTO BALANCE ANALOG INPUT SAMPLE N ∅1 AUTO BALANCE ∅1 ∅2 SAMPLE N+1 AUTO BALANCE ENCODED DATA IS LATCHED INTO THE OUTPUT REGISTERS ∅2 SAMPLE N+2 tAP tH tAJ tOD DATA OUTPUT DATA N-4 DATA N-3 DATA N-2 DATA N-1 DATA N FIGURE 1. INPUT-TO-OUTPUT TIMING CE1 CE2 tEN tDIS D0 - D5 DATA HIGH IMPEDANCE OVF DATA tDIS tEN HIGH DATA DATA IMPEDANCE HIGH IMPEDANCE DATA FIGURE 2. OUTPUT ENABLE TIMING Burn-In Circuit HI-5701/883 CerDIP +5V CAP C1 0.01µF/0.1µF 0V CLK +4V CAP 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 VIN C7 0.01µF/0.1µF 0V NOTES: 1. 2. 3. 4. Power supply and the reference voltage input to be decoupled by 0.01µF in parallel with 1µF capacitor Clock input is a pulse with 1:10 duty cycle, approximately 100KHz and 0V to 4V amplitude VIN, analog input is a slow triangular waveform (FIN = 10KHz) and 0V to 4V amplitude All supplies to be protected with <7V zener diodes Spec Number 6-7 512031 HI-5701/883 Packaging F18.3 MIL-STD-1835 GDIP1-T18 (D-6, CONFIGURATION A) 18 LEAD FRIT SEAL DUAL-IN-LINE CERAMIC PACKAGE FRIT SEAL DUAL-IN-LINE CERAMIC PACKAGE c1 -A- LEAD FINISH INCHES -DBASE METAL (c) E b1 bbb S C A-B S -C- S1 b ccc M C A - B S D S 5.08 NOTES - b 0.014 0.026 0.36 0.66 2 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 2 b2 eA/2 - SECTION A-A eA e 0.200 0.58 α A A - 0.36 A L MAX A 0.023 Q SEATING PLANE MIN 0.014 D BASE PLANE MAX b1 M D S MIN (b) M -B- MILLIMETERS SYMBOL c aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. c 0.008 0.018 0.20 0.46 c1 0.008 0.015 0.20 0.38 3 D - 0.960 - 24.38 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 6 S1 0.005 - 0.13 - 7 S2 0.005 - 0.13 - α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N 18 18 8 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 7. Measure dimension S1 at all four corners. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 6. Dimension Q shall be measured from the seating plane to the base plane. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: Inch. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 6-8 512031