N CLC412 Dual Wideband Video Op Amp General Description Features The CLC412 combines a high-speed complementary bipolar process with National's current-feedback topology to produce a very highspeed dual op amp. The CLC412 provides a 250MHz small-signal bandwidth at a gain of +2V/V and a 1300V/µs slew rate while consuming only 50mW per amplifier from ±5V supplies. ■ The CLC412 offers exceptional video performance with its 0.02% and 0.02° differential gain and phase errors for NTSC and PAL video signals while driving one back terminated 75Ω load. The CLC412 also offers a flat gain response of 0.1dB to 30MHz and very low channel-to-channel crosstalk of -76dB at 10MHz. Additionally, each amplifier can deliver a 70mA continuous output current. This level of performance makes the CLC412 an ideal dual op amp for highdensity broadcast-quality video systems. The CLC412's two very well-matched amplifiers support a number of applications such as differential line drivers and receivers. In addition, the CLC412 is well suited for Sallen Key active filters in applications such as anti-aliasing filters for high-speed A/D converters. Its small 8-pin SOIC package, low power requirement, low noise and distortion allow the CLC412 to serve portable RF applications such as IQ-channels. Wide bandwidth: 330MHz (Av=+1V/V) 250MHz (Av=+2V/V) ■ 0.1dB gain flatness to 30MHz ■ Low power: 5mA/channel ■ Very low diff. gain, phase: 0.02%, 0.02° ■ -76dB channel-to-channel crosstalk (10MHz) ■ Fast slew rate: 1300V/µs ■ Unity-gain stable CLC412 Dual Wideband Video Op Amp June 1999 Applications ■ ■ ■ ■ ■ ■ HDTV, NTSC & PAL video systems Video switching and distribution IQ amplifiers Wideband active filters Cable drivers DC coupled single-to-differential conversions The CLC412 is available in the following versions. CLC412AJP CLC412AJE CLC412AIB CLC412A8B -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C CLC412A8L-2A -55°C to +125°C CLC412AMC -55°C to +125°C 8-pin Plastic DIP 8-pin Plastic SOIC 8-pin CERDIP 8-pin CERDIP, MIL-STD-883, Level B 20-pin LCC, MIL-STD-883, Level B dice, MIL-STD-883, Level B DESC SMD number: 5962-94719 Typical Application Sallen-Key Low-Pass Filter Pinout Vin R1 + Rin Ko Vout Vin = R2 C2 Rf R1R 2 C1C 2 1 1− K 9 1 1 s + s + + + R1C1 R 2 C 2 R 2 C 2 R1R 2 C1C 2 C1 + ½CLC412 - DIP & SOIC Vout ½CLC412 - Rf Rg Vout1 1 Vinv1 2 Vnon-inv1 3 -Vcc 4 + + 8 +Vcc 7 Vout2 6 Vinv2 5 Vnon-inv2 2 1999 National Semiconductor Corporation Printed in the U.S.A. http://www.national.com Ω ; VCC = ±5V; RL = 100Ω Ω) CLC412 Electrical Characteristics (AV = +2; Rf = 634Ω PARAMETERS Ambient Temperature CONDITIONS CLC412 AJ TYP +25°C MIN/MAX RATINGS -40°C +25°C +85°C FREQUENCY DOMAIN RESPONSE -3dB bandwidth Vout < 0.5Vpp Vout < 4.0Vpp gain flatness Vout < 0.5Vpp peaking DC to 30MHz rolloff DC to 30MHz linear phase deviation DC to 75MHz differential gain 4.43MHz, RL=150Ω differential phase 4.43MHz, RL=150Ω TIME DOMAIN RESPONSE rise and fall time 0.5V step 4V step settling time to 0.05% 2V step overshoot 0.5V step slew rate 2V step DISTORTION AND NOISE RESPONSE 2Vpp, 20MHz 2nd harmonic distortion 2Vpp, 20MHz 3rd harmonic distortion 10MHz 3rd order intermodulation intercept equivalent noise input non-inverting voltage >1MHz inverting current >1MHz non-inverting current >1MHz noise floor >1MHz crosstalk input-referred 10MHz - 46 - 50 43 - 42 - 46 - 42 - 46 3.0 12.0 2.0 - 157 - 76 3.4 13.9 2.6 - 156 - 70 STATIC DC PERFORMANCE *input offset voltage average drift *input bias current average drift *input bias current average drift power supply rejection ratio common mode rejection ratio *supply current ±2 ± 30 ±5 ± 30 ±3 ± 20 50 50 10.2 ± 10 ± 60 ± 28 ± 187 ± 34 ± 125 46 45 13.6 1000 1.0 0.04 + 3.8,-3.3 + 3.1,-2.9 300 500 500 2.0 2.0 2.0 0.6 0.3 0.2 + 3.6,-2.9 + 3.7,-3.0 + 3.7,-3.0 + 2.0,-2.5 ± 2.7 ± 2.7 + 2.5,-2.6 ± 1.4 ± 2.0 ± 2.0 25 45 45 non-inverting inverting DC DC RL= ∞ MISCELLANEOUS PERFORMANCE input resistance non-inverting input capacitance non-inverting output resistance closed loop output voltage range RL= ∞ RL=100Ω RL=100Ω (0° to 70°C) input voltage range common mode output current UNITS SYMBOL 250 105 150 80 175 80 135 65 MHz MHz SSBW LSBW 0.1 0.1 0.5 0.02 0.02 0.1 0.4 1.3 0.04 0.04 0.1 0.3 1.0 0.04 0.04 0.2 0.3 1.0 0.08 0.08 dB dB deg % deg GFP GFR LPD DG DP 1.4 3.2 12 8 1300 2.3 4.4 18 15 1000 2.0 4.4 18 15 1000 2.6 4.8 20 15 800 ns ns ns % V/µs TRS TRL TSS OS SR - 38 - 42 dBc dBc dBm1Hz HD2 HD3 IMD 3.4 13.9 2.6 - 156 - 70 3.8 15.5 3.0 - 155 - 70 nV/√Hz pA/√Hz pA/√Hz dBm1Hz dB VN NICN ICN SNF XTLKA ±6 ± 12 ± 60 ± 12 ± 90 ± 20 ± 80 44 43 12.8 mV µV/°C µA nA/°C mA nA/°C dB dB mA VIO DVIO IBN DIBN IBI DIBI PSRR CMRR ICC kΩ pF Ω V V V V mA RIN CIN ROUT VO VOL VOLC CMIR IO ± 2.2 70 ____ ± 12 ____ ± 15 ____ 46 45 12.8 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings V cc Iout Miscellaneous Ratings ±7V short circuit protected to ground, however maximum reliabiliy is obtained if Iout does not exceed... common-mode input voltage maximum junction temperature operating temperature range: AJ storage temperature range lead temperature (soldering 10 sec) ESD (100V machine test) 125mA ±V cc +150°C -40°C to +85°C -65°C to +150°C +300°C 1000V Recommended gain range * AJ : 100% tested at +25°C. Package Thermal Resistance Reliability Information Transistor count http://www.national.com ±1 to ±10V/V Notes: 68 2 Package θ JC θ JA AJP AJE A8B 70°C/W 65°C/W 40°C/W 125°C/W 145°C/W 130°C/W 3 http://www.national.com http://www.national.com 4 +Vcc + Rf C3 +Vcc + C1 Vin C3 + C1 Vout ½CLC412 Rin Ro - Vin Rg C2 Rg Vout ½CLC412 Ro + + C4 -Vcc - C2 Rb + C4 Rf -Vcc Figure 1 Figure 2 Application Introduction Offered in an 8-pin package for reduced space and cost, the wideband CLC412 dual current-feedback op amp provides closely matched DC & AC electrical performance characteristics making the part an ideal choice for wideband signal processing. Applications such as broadcast-quality video systems, IQ amplifiers, filter blocks, high-speed peak detectors, integrators and transimpedance amplifiers will all find superior performance in the CLC412 dual op amp. and phase response to the value of the feedback resistor, Rf. For more information see Application Note OA-13 which describes the relationship between Rf and closedloop frequency response. When configuring the CLC412 for other inverting or noninverting gains, it is necessary to adjust the value of the feedback resistor in order to optimize the device’s frequency and phase response. The two plots below provide the means of selecting the recommended feedback-resistor value for both inverting and non- Feedback Resistor Selection The loop gain and frequency response for a currentfeedback operational amplifier is determined largely by the feedback resistor, Rf. The Electrical Characteristics and Typical Performance plots specify an Rf of 634Ω, a gain of +2V/V and operation with ±5V power supplies (unless otherwise stated). Generally, lowering Rf from its recommended value will peak the frequency response and extend the bandwidth while increasing its value will roll off the response. Reducing the value of Rf too far below its recommended value will cause overshoot, ringing and eventually oscillation. inverting gain selections. Both plots show the value of Rf approaching a non-zero minimum (dashed line) at high gains, which is characteristic of current-feedback op amps, while the linear portion of the two (solid) curves (i.e. -5>Av>+6) results from the limitation placed on Rg (i.e. Rg ≥50Ω). This limitation is due to the desire to keep Rg greater in value than that of the inverting input resistance. Therefore, the resulting small-signal The plot above labeled "Frequency Response vs. Rf" shows the CLC412’s frequency and phase response as Rf is varied while the gain remains constant at +2V/V (RL=100Ω). This plot shows that one particular value of Rf will optimize the frequency and phase response at the specified gain setting, i.e. 634Ω at a gain of +2V/V. Current-feedback op amps, unlike voltage-feedback op amps, have a direct relationship between their frequency 5 http://www.national.com bandwidth curves, labeled "BW", correspond to the two (solid) "Rf" curves. These results may deviate from that produced by the analysis of OA-13 since these plots were produced from an actual board layout that included parasitic capacitances not accounted for by the analysis of OA-13. It should be noted that a non-inverting gain of +1V/V requires an Rf =1kΩ and the output voltage used for both plots is 2Vpp. surface mount package. Either of these layouts can assist the designer in obtaining the desired performance. In addition, the boards can serve as an example layout for the final production printed circuit board. Care must also be taken with the CLC412's layout in order to achieve the best circuit performance, particularly channel-to-channel isolation. The decoupling capacitors (both tantalum and ceramic) must be chosen with good high frequency characteristics to decouple the power supplies and the physical placement of the CLC412’s external components is critical. Grouping each amplifier’s external components with their own ground connection and separating them from the external components of the opposing channel with the maximum possible distance is recommended. The input (Rin) and gain-setting resistors (Rg) are the most critical. It is also recommended that the ceramic decoupling capacitor (0.1µF chip or radial-leaded with low ESR) should be placed as closely to the power pins as possible. In order to bandlimit the CLC412 at any particular gain setting, a larger value of Rf (than previously recommended in the plots above) is needed. Following the analysis in OA-13, we find the CLC412’s "optimum feedback transimpedance", Z t *, below. R ∗ Z t = R f + Rin 1 + f R g 634 = 634 + 60 1 + 634 = 754Ω Package Parasitics In addition to the parasitic capacitances arising from the board layout, each of the CLC412's packages has its own characteristic set of parasitic capacitances and inductances causing frequency response variation from package to package as shown in the plot below labeled "Frequency Response vs. Package Type". Due to its much smaller size, the CLC412AJE (8-pin SOIC) shows the least amount of peaking. 20LOG (754) = 57.5dB The "optimum feedback transimpedance" is unique for each current-feedback op amp and determines the recommended value of Rf for a particular gain setting. Drawing a horizontal line on the “Open-loop Transimpedance, Z(s)” plot from 57.5dB (on the left vertical axis), we find the intersection with the transimpedance magnitude trace occurs at a frequency of 180MHz. This frequency is only an approximation of the CLC412’s small-signal bandwidth. From this intersection, one can see that an increase in Z t will produce a new intersection occurring at a lower frequency. This is the process to follow when bandlimiting. Once the target small-signal bandwidth is determined, the new value of Zt is picked off the graph at the point where the this frequency and the transimpedance magnitude trace intersect. One can then back track to figure the value of the feedback resistor, Rf=Z t-Rin(1+Rf /Rg). This new value of Rf will produce the desired frequency roll-off. Circuit Layout With all high-frequency devices, board layouts with stray capacitances have a strong influence over AC performance. The CLC412 is no exception and its input and output pins are particularly sensitive to the coupling of parasitic capacitances (to ac ground) arising from traces or pads placed too closely (<0.1") to power or ground planes. In some cases, due to the frequency response peaking caused by these parasitics, a small adjustment of the feedback resistor value will serve to compensate the frequency response. Also, it is very important to keep the parasitic capacitance across the feedback resistor to an absolute minimum. Matching Performance With proper board layout, the AC performance match between the two CLC412’s amplifiers can be tightly 634Ω Vin 314Ω ½CLC412 50Ω + 50Ω 25Ω Vout 50Ω + 50Ω ½CLC412 - The performance plots in the data sheet can be reproduced using the evaluation boards available from Comlinear. There are two types of boards; the DIP (#730038) and SOIC (#730036). The #730036 board uses all SMT parts for the evaluation of the CLC412 in its http://www.national.com 59Ω 634Ω 634Ω Figure 3 6 voltage at the output by the following equation: controlled as shown in Typical Performance plot labeled “Small-Signal Channel Matching”. The measurements were performed with SMT components using the recommended value of feedback resistor of 634Ω at a gain of +2V/V. The pulse response plot labeled "Pulse Matching" found below shows the group delay matching between amplifiers of the CLC412. The circuit topology is described in Figure 3. R R Voffset = ± Ibn ∗R s 1 + f + Vio 1 + f + Ibi ∗R f R R g g The input resistor Rin is the resistance looking from the non-inverting input back towards the source. For inverting DC-offset calculations, the source resistance seen by the input resistor Rg must be included in the output offset calculation as a part of the non-inverting gain equation. Application note OA-7 gives several circuits for DC offset correction. The noise currents for the inverting and noninverting inputs are graphed in the Typical Performance plot labeled “Equivalent Input Noise”. A more complete discussion of amplifier input-referred noise and external resistor noise contribution can be found in OA-12. Differential Gain & Phase The CLC412 can drive multiple video loads with very low differential gain and phase errors. The Typical Performance plots labeled “Differential Gain vs. Frequency” and "Differential Phase vs. Frequency" show performance for loads from 1 to 4. The Electrical Characteristics table also specifies guaranteed performance for one 150Ω load at 4.43MHz. For NTSC video, the guaranteed performance specifications also apply. Application note OA-08, “Differential Gain and Phase for Composite Video Systems,” describes in detail the techniques used to measure differential gain and phase. The CLC412's amplifiers, built on the same die, provide the advantage of having tightly matched DC characteristics. The typical DC matching specifications of the CLC412 are: ∆Vio = ±0.60mV, ∆Ibn = ±0.25µA, ∆Ibi = ±1.5µA. Slew Rate and Settling Time One of the advantages of current-feedback topology is an inherently high slew rate which produces a wider fullpower bandwidth. The CLC412 has a typical slew rate of 1300V/µs. The required slew rate for a design can be calculated by the following equation: SR=2πfVpk I/O Voltage & Output Current The usable common-mode input voltage range (CMIR) of the CLC412 specified in the Electrical Characteristics table of the data sheet shows a range of ±2.2 volts. Exceeding this range will cause the input stage to saturate and clip the output signal. Careful attention to parasitic capacitances is critical to achieving the best settling time performance. The CLC412 has a typical short term settling time to 0.05% of 12ns for a 2 volt step. Also, the amplifier is virtually free of any long term thermal tail effects at low gains as shown in the Typical Performance plot labeled “Long Term Settling Time”. The output voltage range is determined by the load resistor and the choice of power supplies. With ±5 volts the class A/B output driver will typically drive +3.1/-2.7 volts into a load resistance of 100Ω. Increasing the supply voltages will change the common-mode input and output voltage swings while at the same time increase the internal junction temperature. The output voltage for different load resistors can be determined from the data sheet plots labeled “Frequency Response vs. Load (RL)" and “Maximum Output Swing vs. Frequency". When measuring settling time, a solid ground plane should be used in order to reduce ground inductance which can cause common-ground-impedance coupling. Power supply and ground trace parasitic capacitances and the load capacitance will also affect settling time. Placing a series resistor (Rs) at the output pin is recommended for optimal settling time performance when driving a capacitive load. The Typical Performance plot labeled “Rs and Settling Time vs. Capacitive Load” provides a means for selecting a value of Rs for a given capacitive load. The plot also shows the resulting settling time to 0.05 and 0.01%. Applications Circuits Single-to-Differential Line Driver. The CLC412's well matched AC channel-response allows a single-ended input to be transformed to highly-matched push-pull driver. From a 1V single-ended input the circuit of Figure 4 produces 1V differential signal between the two outputs. For larger signals, the input voltage divider (R1=2R2) is necessary to limit the input voltage on channel 2. To achieve the same performance when driving a matched load, see Figure 3. DC & Noise Performance A current-feedback amplifier’s input stage does not have equal nor correlated bias currents, therefore they cannot be canceled and each contributes to the total DC offset 7 http://www.national.com CMRR over frequency can be achieved through the placement of an RC network between the outputs (A and B) of the two amplifiers of the CLC412. R f1 Rg1 Vin ½CLC412 Ro1 + R1 Non-Inverting Current-Feedback Integrator. The circuit of Figure 7 achieves its high-speed integration by placing one of the CLC412's amplifiers in the feedback loop of the second amplifier configured as shown. R Vout Av1 = -0.5V/V V in 3 R1 R2 + ½CLC412 Ro2 - ½CLC412 R f2 Rg2 + Rb + - Differential Line Receiver. Figures 5 and 5a show two different implementations of an instrumentation amplifier which convert differential signals to single-ended. Figure 5a allows CMRR adjustment through R2. Rg - ½CLC412 + + R1 Low-Noise Wide-Bandwidth Transimpedance Amplifier. Figure 8 implements a low-noise transimpedance amplifier using both channels of the CLC412. This circuit takes advantage of the lower inputbias-current noise of the non-inverting input and achieves negative feedback through the second CLC412 channel. The output voltage is set by the value of Rf while frequency compensation is achieved through the adjustment of RT. R (Av2 = -1V/V) (Av1 = -1V/V) +Vin Figure 7 Vout1 Ro -Vin Cf Figure 5 Rf + R2 Rf + Vout -Vin Rg2 RT Ro +Vin Av = -10 R1=Rf Vin R1 + + Rin ½CLC412 - R2 C1 + ½CLC412 - C2 Rf R f1 R A CLC420 + - + Vin2 B Vout Ko Ro Vout Ra Vin Rb Rin2 Rin1=Rin2 1 1− K 9 1 1 2 + + + s + s R1C1 R 2 C 2 R 2 C 2 R1R 2 C1C 2 Figure 9 Figure 6 http://www.national.com = R1R 2 C1C 2 8 Vout ½CLC412 - Rf Rg R f2 ½CLC412 I JJ JJ K Buffered 2nd-Order Sallen-Key Low-Pass Filter. Figure 9 shows one implementation of a 2nd order Sallen-Key low pass filter buffered by one of the CLC412's channels. The CLC412 enables greater precision since it provides the advantage of very low output impedance and very linear phase throughout the pass-band. High-Speed Instrumentation Amplifier. For applications requiring higher CMRR the composite circuit of Figure 6 uses the two amplifiers of the CLC412 to create balanced inputs for the CLC420 voltagefeedback op amp. The DC CMRR can be fine tuned through the adjustment of Rb. Further improvement of Rin1 F GG GG H 1 R 1+ T Z(s) A 2ω p s+ ωp Rg=Rf/10 Figure 5a Vin1 IR s f Vo = Figure 8 R R R f2 R A 2 = − f2 R g2 ½CLC412 Av = +1 Vo - ½CLC412 Cin Is Rg ½CLC412 Ro ½CLC412 R Rf R1 R2 R1 Vo = Vin sRC Rg Rf ½CLC412 R Vout ½CLC412 Figure 4 Rf + C Vin Av2 = 1.5V/V R1 - R R2 Rf Rg This page intentionally left blank. 9 http://www.national.com This page intentionally left blank. 10 http://www.national.com This page intentionally left blank. 11 http://www.national.com CLC412 Dual Wideband Video Op Amp Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12