ISL54230 ® Data Sheet December 26, 2008 FN6825.0 Octal Multiprotocol Switch Features The Intersil ISL54230 is a multiprotocol Quad Double-Pole Double-Throw (DPDT) analog switch that can operate from a single +2.0V to +5.5V supply. It contains eight SPDT (Single Pole/Double Throw) switches configured into four DPDT blocks. Each DPDT block is independently controlled by a logic input for Normally Open (NO) or Normally Closed (NC) switch configuration.The part is designed for switching or routing a combination of USB High-Speed, USB Full-Speed, digital, and analog signals in portable battery powered products. • High Speed (480Mbps) and Full Speed (12Mbps) Signaling Capability per USB 2.0 The digital inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL54230 has two switch enable pins to disable certain blocks of the switch. The ISL54230 is available in a 32 Ld TQFN 5mmx5mm package. It operates over a temperature range of -40 to +85°C. • Two DPDT USB 2.0 FS/HS Capable Switches Applications • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . 1µA • Cellular/Mobile Phones • Low I+ Current when VINH is not at the V+ Rail • Compliant with USB 2.0 Short Circuit and Overvoltage Requirements Without Additional External Components • 1.8V Logic Compatible (+2.7V to +3.6V Supply) • Switch Terminals Overvoltage Protected Up to +5.5V • Enable Pin to disable Switch Blocks • Two DPDT 1Ω/6Ω Switches • USB Switch Low ON Capacitance. . . . . . . . . . . . . . . 12pF • USB Switch Low ON-Resistance. . . . . . . . . . . . . . . . . 6Ω • Single Supply Operation (VDD) . . . . . . . . . . +2.0V to +5.5V • Available in 32 Ld 5mmx5mm TQFN package • PDA’s • Pb-Free (RoHS Compliant) • Digital Cameras and Camcorders • USB/UART/Audio Switching Block Diagram VDD COM1A IN1 COM1B 1Ω NO1A NC1A 6Ω NO1B NC1B COM2A HS_USB NC2A IN2 COM2B NO2A HS_USB NO2B NC2B COM3A HS_USB IN3 COM3B NO3A NC3A HS_USB NO3B NC3B COM4A 1Ω NC4A IN4 COM4B OE1 OE2 1 NO4A 6Ω NO4B NC4B GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54230 Pinouts COM_3B OE2 COM_4B COM_1B OE1 COM_2B COM_2A *Refer to OE Control Truth Table, page 3 COM_3A ISL54230 (32 LD 5X5 TQFN) TOP VIEW 32 31 30 29 28 27 26 25 NC_4A 1 24 NC_1A COM_4A 2 23 COM_1A NC_3A 3 22 NC_2A NO_4A 4 21 NO_1A NO_3A 5 20 NO_2A NC_3B 6 19 NC_2B NO_3B 7 18 NO_2B NC_4B 8 17 NC_1B 12 13 GND IN3 IN2 SWITCHES 1 AND 2 14 15 16 NO_1B 11 IN1 10 VDD 9 IN4 *RIGHT PLANE NO_4B *LEFT PLANE SWITCHES 3 AND 4 VDD VDD NO1A COM1A COM1B USB HS SWITCH NO3A NC1A NC3A NO1B USB HS SWITCH NO3B 1Ω SWITCH COM3A 6Ω SWITCH COM3B NC1B COM2A COM2B NC3B NO4A USB HS SWITCH NO2A NC2A NC4A USB HS SWITCH NO2B NO4B COM4A COM4B 1Ω SWITCH 6Ω SWITCH NC4B NC2B IN1 IN2 OE1 OE2 IN3 IN4 OE1 OE2 LOGIC CONTROL GND LOGIC CONTROL GND NOTE: Switches shown in Logic “0” position. Logic “0” when INx <0.5V 2 FN6825.0 December 26, 2008 ISL54230 Pin Descriptions (Continued) OE Control Truth Table SWITCH ON SWITCH OFF MODE 0 COM2x, COM3x COM1x, COM4x USB 0 1 COM3x, COM4x COM1x, COM2x Left Plane 1 0 COM1x, COM2x COM3x, COM4x Right Plane ALL NONE All On OE1 OE2 0 1 1 Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. Input Select Truth Table INx NOx NCx 0 OFF ON 1 ON OFF Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. Pin Descriptions PIN NAME PIN NUMBER TQFN VDD 14 Power Supply Pin GND 11 Ground Connection OE1 27 Switch Enable Control 1 OE2 30 Switch Enable Control 2 IN1 15 Switch Input Select 1 IN2 13 Switch Input Select 2 IN3 12 Switch Input Select 3 IN4 10 Switch Input Select 4 PIN NAME PIN NUMBER TQFN COM_1A 23 HS Switch Common 1A COM_1B 28 HS Switch Common 1B COM_2A 25 HS Switch Common 2A COM_2B 26 HS Switch Common 2B COM_3A 32 6Ω Switch Common 3A COM_3B 31 1Ω Switch Common 3B COM_4A 2 6Ω Switch Common 4A COM_4B 29 1Ω Switch Common 4B NC_1A 24 Switch Normally Closed 1A NC_1B 17 Switch Normally Closed 1B NC_2A 22 Switch Normally Closed 2A NC_2B 19 Switch Normally Closed 2B NC_3A 3 Switch Normally Closed 3A NC_3B 6 Switch Normally Closed 3B NC_4A 1 Switch Normally Closed 4A NC_4B 8 Switch Normally Closed 4B NO_1A 21 Switch Normally Open 1A NO_1B 16 Switch Normally Open 1B NO_2A 20 Switch Normally Open 2A NO_2B 18 Switch Normally Open 2B NO_3A 5 Switch Normally Open 3A NO_3B 7 Switch Normally Open 3B NO_4A 4 Switch Normally Open 4A NO_4B 9 Switch Normally Open 4B DESCRIPTION DESCRIPTION Ordering Information PART NUMBER (Note) PART MARKING ISL54230IRTZ-T* 54230 IRTZ TEMP. RANGE (°C) -40 to +85 PACKAGE (Pb-Free) 32 Ld 5x5 TQFN (Tape and Reel) PKG. DWG. # L32.5x5A *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3 FN6825.0 December 26, 2008 ISL54230 Absolute Maximum Ratings Thermal Information VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5V Input Voltages NCx, NOx (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +6.5V INx, OEx (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5V Output Voltages COMx (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Continuous Current (NC2x, NO3x) . . . . . . . . . . . . . . . . . . . . ±40mA Continuous Current (NC1x, NO4x) . . . . . . . . . . . . . . . . . . . ±150mA Peak Current (NC2x, NO3x) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±100mA Peak Current (NC1x, NO4x) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±300mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV Thermal Resistance (Typical, Notes 2, 3) θJA (°C/W) θJC (°C/W) 32 Ld 5x5mm TQFN Package . . . . . . . 30 1.5 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . . +2.0V to +5.5V Logic Control Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Signals on NCx, NOx, COMx, INx, and OEx exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 3. For θJC, the “case temperature” location is the center of the exposed metal pad on the package underside. Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +2.7V, GND = 0V, VINxH = 1.4V, VINxL = 0.5V, VOExH = 1.4V, VOExL = 0.5V, (Note 4), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP MIN MAX (°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS ANALOG SWITCH CHARACTERISTICS USB HS Switch, COM2x and COM3x Analog Signal Range, VANALOG Full 0 - VDD V ON-Resistance, rON High Speed VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNCx = 0V to 400mV (see Figure 1) 25 - 8.3 - Ω Full - 9.25 - Ω rON Matching Between Channels, ΔrON, High Speed VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNCx = Voltage at max rON, (Note 8) 25 - 0.11 - Ω Full - 0.22 - Ω rON Flatness, RFLAT(ON) High Speed VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNCx = 0V to 400mV, (Note 7) 25 - 1.45 - Ω Full - 1.8 - Ω ON-Resistance, rON Full Speed VDD = 2.7V, VOEx = VOExH, ICOMx = 1mA, VNOx or VNCx =0V to 2.7V (see Figure 1, Note 9) 25 - 130 150 Ω Full - 150 178 Ω rON Matching Between Channels, ΔrON, Full-Speed VDD = 2.7V, VOEx = VOExH, ICOMx = 1mA, VNOx or VNCx = Voltage at max RON over signal range of 0V to 2.7V (Note 8) 25 - 1.2 - Ω Full - 2.6 - Ω rON Flatness, RFLAT(ON) Full-Speed VDD = 2.7V, VOEx = VOExH, ICOMx = 1mA, VNOx or VNCx = 0V to 1V (Note 7) 25 - 4 - Ω ON-Resistance, RON VDD = 2.7V, VOEx = VOExH, ICOMx = 1mA, VNOx or VNCx = 0V to 1.8V (see Figure 1) OFF Leakage Current, INOx(OFF) or VDD = 3.6V, VOEx = Such that switch is disabled, INCx(OFF) VCOMx = 0.3V, 3.3V, VNOx = 3.3V, 0.3V, VNCx = 3.3V, 0.3V VDD = 3.6V, VOEx = VOExH, VCOMx = 0.3V, 3.3V, VNOx = 0.3V, 3.3V, VNCx = 0.3V, 3.3V ON Leakage Current, ICOMx(ON) 4 Full - 5 - Ω 25 - 128 - Ω Full - 140 - Ω 25 -20 4 20 nA Full -100 - 100 nA 25 -50 4 50 nA Full -100 - 100 nA FN6825.0 December 26, 2008 ISL54230 Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +2.7V, GND = 0V, VINxH = 1.4V, VINxL = 0.5V, VOExH = 1.4V, VOExL = 0.5V, (Note 4), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS Power OFF Leakage Current, ID+, ID- VDD = 0V, VNOx = 0V to 5.25V, VNCx= 0V to 5.25V, VINX = 0V, VOEX such that switch is disabled (see Figure 5) TEMP MIN MAX (°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS 25 - 2 100 nA Full - - 2 µA Full 0 - VDD V 25 - 1.26 1.5 Ω Full - 1.5 1.74 Ω 1Ω Switch, COM1A and COM4A Analog Signal Range, VANALOG VDD = 2.7V, VOEx = VOExH, ICOMx = 100mA, VNOx or VNCx = 0V to 2.7V (see Figure 1, Note 9) ON-Resistance, RON rON Matching Between Channels, ΔrON VDD = 2.7V, VOEx = VOExH, ICOMx = 100mA, VNOx or VNCx = Voltage at max rON over signal range of 0V to 2.7V, (Note 8) rON Flatness, RFLAT(ON) VDD = 2.7V, VOEx = VOExH, ICOMx = 100mA, VNOx or VNCx = 0V to 2.7V (Note 7) VDD = 2.7V, VOEx = VOExH, ICOMx = 100mA, VNOx or VNCx = 0V to 1.8V (see Figure 1) ON-Resistance, RON OFF Leakage Current, INOx(OFF) or VDD = 3.6V, VOEx = VOExL, VCOMx = 0.3V, 3.3V, INCx(OFF) VNOx = 3.3V, 0.3V, VNCx = 3.3V, 0.3V VDD = 3.6V, VOEx = VOExH, VCOMx = 0.3V, 3.3V, VNOx = 0.3V, 3.3V, VNCx = 0.3V, 3.3V ON Leakage Current, ICOMx(ON) 25 - 0.05 - Ω Full - 0.07 - Ω 25 - 0.37 0.52 Ω Full - 0.37 0.6 Ω 25 - 1.3 - Ω Full - 1.4 - Ω 25 -20 4 20 nA Full -150 - 150 nA 25 -50 10 50 nA Full -300 - 300 nA Full 0 - VDD V 25 - 8 9.2 Ω 6Ω Switch, COM1B and COM4B Analog Signal Range, VANALOG ON-Resistance, rON VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNCx = 0V to 2.7V (see Figure 1, Note 9) rON Matching Between Channels, ΔrON VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNC x= Voltage at max rON over signal range of 0V to 2.7V, (Note 8) rON Flatness, RFLAT(ON) VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNCx = 0V to 2.7V (Note 7) VDD = 2.7V, VOEx = VOExH, ICOMx = 40mA, VNOx or VNCx = 0V to 1.8V (see Figure 1) ON-Resistance, RON Full - 9.2 10.8 Ω 25 - 0.08 - Ω Full - 0.3 - Ω 25 - 1.9 2.8 Ω Full - 1.9 3.3 Ω 25 - 8 - Ω Full - 8.8 - Ω OFF Leakage Current, INOx(OFF) or VDD = 3.6V, VOEx = VOExL, VCOMx = 0.3V, 3.3V, INCx(OFF) VNOx = 3.3V, 0.3V, VNCx = 3.3V, 0.3V 25 -20 4 20 nA Full -100 - 100 nA VDD = 3.6V, VOEx = VOExH, VCOMx = 0.3V, 3.3V, VNOx = 0.3V, 3.3V, VNCx = 0.3V, 3.3V 25 -50 4 50 nA Full -130 - 130 nA ON Leakage Current, ICOMx(ON) DYNAMIC CHARACTERISTICS USB HS Switch Skew, tSKEW VDD = 3.0V, VOEx = VOExH, RL = 45Ω, CL = 10pF, tR = tF = 720ps at 480Mbps, Duty Cycle = 50% (see Figure 6) 25 - 50 - ps Total Jitter, tJ VDD =3.0V, VOEx = VOExH, RL = 45Ω, CL = 10pF, tR = tF = 750ps at 480Mbps 25 - 210 - ps Propagation Delay, tPD VDD = 3.0V, VOEx = VOExH, RL = 45Ω, CL = 10pF (see Figure 6) 25 - 250 - ps OFF-Isolation VDD = 3.0V, RL = 50Ω, f = 240MHz (see Figure 2) 25 - -15 - dB HS Switch -3dB Bandwidth, Signal = 50mVRMS, RL = 50Ω 25 - 500 - MHz 5 FN6825.0 December 26, 2008 ISL54230 Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +2.7V, GND = 0V, VINxH = 1.4V, VINxL = 0.5V, VOExH = 1.4V, VOExL = 0.5V, (Note 4), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP MIN MAX (°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS OFF Capacitance, CNOxOFF or CNCxOFF f = 1MHz, VDD = 3.0V, VOEx = VOExH, VNOx or VNCx = 0V (see Figure 3) 25 - 6.2 - pF COM ON Capacitance, CCOMxON f = 1MHz, VDD = 3.0V, VOEx = VOExH, VNOx or VNCx = 0V (see Figure 3) 25 - 12.5 - pF Crosstalk VDD = 3.0V, RL = 50Ω, f = 10MHz (see Figure 4) 25 - -90 - dB OFF-Isolation VDD = 3.0V, RL = 50Ω, f = 1MHz (see Figure 2) 25 - 55 - dB 1Ω Switches Switch -3dB Bandwidth Signal = 50mVRMS, RL = 50Ω 25 - 78 - MHz OFF Capacitance, CNOxOFF or CNCxOFF f = 1MHz, VDD = 3.0V, VOEx = VOExH, VNOx or VNCx = 0V (see Figure 3) 25 - 21 - pF COM ON Capacitance, CCOMxON f = 1MHz, VDD = 3.0V, VOEx = VOExH, VNOx or VNCx = 0V (see Figure 3) 25 - 61 - pF 6Ω Switches Crosstalk VDD = 3.0V, RL = 50Ω, f = 10MHz (see Figure 4) 25 - -67 - dB OFF-Isolation VDD = 3.0V, RL = 50Ω, f = 10MHz (see Figure 2) 25 - 50 - dB Switch -3dB Bandwidth 50mVRMS, RL = 50Ω 25 - 310 - MHz OFF Capacitance, CNOxOFF or CNCxOFF f = 1MHz, VDD = 3.0V, VOEx = VOExH, VNOx or VNCx = 0V (see Figure 3) 25 - 6 - pF COM ON Capacitance, CCOMxON f = 1MHz, VDD = 3.0V, VOEx = VOExH, VNOx or VNCx = 0V (see Figure 3) 25 - 15 - pF Full 2.7 3.6 V 25 - 1 2 µA Full - 1.24 - µA 25 - 1 - µA POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 3.6V, VOEx = VINx = 0V, VNOx or VNCx = 0V, VCOMx = 0V Power Supply Current, IDD VDD = 3.6V, VLogic = 1.8V, VNOx or VNCx = 0V, VCOMx = 0V. Driving one logic pin only. DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINLx, VOELx VDD = 2.7V to 3.6V Full - - 0.5 V Input Voltage High, VINHx, VOEHx VDD = 2.7V to 3.6V Full 1.4 - - V Input Current Low, IINLx, IOELx VDD = 2.7V to 3.6V Full -50 20 50 nA Input Current High, IINHx, IOEHx VDD = 2.7V to 3.6V Full -2 1 2 µA NOTES: 4. Vlogic = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range 8. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between NCx or NOx. 9. Limits established by characterization and are not production tested. 6 FN6825.0 December 26, 2008 ISL54230 Test Circuits and Waveforms VDD VDD C C 50Ω SIGNAL GENERATOR NO OR NC rON = V1/Icom NOx OR NCx IN VNO/NC Icom 0V OR V+ INx V1 COM ANALYZER VIN COMx GND RL GND Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 2. OFF-ISOLATION TEST CIRCUIT FIGURE 1. rON TEST CIRCUIT VDD VDD C 50Ω SIGNAL GENERATOR NOx/NCx NO1/NC1 INx C RL COM1 INx IMPEDANCE ANALYZER 0V OR VDD COMx VIN 50Ω COM is connected to NO or NC during ON capacitance measurement. NOx/NCx COMx ANALYZER GND NC GND Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 3. CAPACITANCE TEST CIRCUIT FIGURE 4. CROSSTALK TEST CIRCUIT VDD A NOx OR NCx 5.25V INx COMx GND NOTE: OEx such that switch is disabled FIGURE 5. POWER OFF LEAKAGE TEST CIRCUIT 7 FN6825.0 December 26, 2008 ISL54230 Test Circuits and Waveforms (Continued) VDD tri C 90% DIN+ 10% 50% VINx tskew_i DIN- 90% INx 15.8Ω DIN+ 50% COM2A 143Ω 10% tfi tro DIN- 15.8Ω COM2B NO2A OR NC2A NO2B OR NC2B OUT+ CL OUTCL 143Ω 45Ω 45Ω 90% OUT+ OUT- 10% 50% GND tskew_o |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. 50% 90% |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals 10% tf0 |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. FIGURE 6A. MEASUREMENT POINTS FIGURE 6B. TEST CIRCUIT FIGURE 6. SKEW TEST Detailed Description Power Supply Considerations The ISL54230 is a multiprotocol switch containing eight switches configured as a Quad DPDT. Each DPDT switch is independently controlled by a logic pin. The ISL54230 has four switches that are compliant in passing USB2.0 signals and four switches with low rON that can be used to pass analog or digital signals such as audio or UART. It is offered in a 32 Ld 5x5mm TQFN package for applications which require small package size such as cellphones and PDAs. The power supply connected to the VDD and GND pins provides the DC bias voltage necessary to operate the IC. The ISL54230 can be operated with a supply voltage in the range of +2.0V to +5.5V. For USB applications the supply voltage should be in the range of +3.0V to +5.5V to ensure proper signal levels on the USB data lines. The ISL54230 contains four switches capable of passing USB2.0 Full-Speed and High-Speed signals with minimal distortion, two 1Ω switches and two 6Ω switches for analog/digital signals. The USB capable switches were designed with low capacitance and high bandwidth to pass USB HS signals (480Mbps) with minimal edge and phase distortion. The 1Ω switches are designed for passing low bandwidth signals (<8MHz) and are ideal for switching power lines since the low ON-resistance minimizes power dissipation. The 6Ω switches are designed to pass audio or data signals up to 100MHz while maintaining a low rON for good THD performance. In addition to the four independent logic control pins that control each DPDT switch, the ISL54230 contains two Output Enable (OE) logic pins that permits the IC to disable certain switches giving the user a high degree of flexibility in signal routing. Please see “OE Control Truth Table” on page 3 for an explanation of the OE pins. All logic pins on the ISL54230 are 1.8V logic compatible up to a +3.3V supply. 8 A decoupling capacitor in the range 0.01µF to 0.1µF should be connected to the VDD supply pin of the IC to filter out any power supply noise that may be present on the supply lines. The capacitor should be place as closed as possible to the VDD pin. Supply Sequencing and Power-On Reset Protection Proper power supply sequencing is necessary to protect the ISL54230 from operating in fault conditions. The ISL54230 integrates Power-On Reset (POR) circuitry that prevents the switches from turning ON until the supply voltage is at least +1.4V. The POR has a 100mV hysteresis built in that will turn the switches OFF when the supply has gone below +1.3V. This function prevents signals from the switch input being passed to the output when the device operating voltage has not reached appropriate levels yet, protecting the switch from fault conditions. The POR circuitry also protects the switch from operating in a fault condition should the power supply to the IC drop below the POR threshold. Thus, the recommended operational supply voltage is within +2.0V to +5.5V. Operating at supply voltages below +2.0V may still be functional but the noise margin between the POR threshold FN6825.0 December 26, 2008 ISL54230 and supply voltage will be reduced. The device may unexpectedly shut down if transient voltages trigger the POR. Overvoltage and Short Circuit Considerations The ISL54230 should be protected from overvoltage conditions. The IC contains ESD protection diodes that are back biased from the switch terminals to ground. Negative voltages on the switch terminals that are large enough to forward-bias these ESD protection diodes will result in a large current flowing from ground that may destroy these diodes. Thus signals on the switch terminals should not swing below ground and cannot exceed the specified “Absolute Maximum Ratings” on page 4 for safe operation. The ISL54230 can have signals that go above the positive supply rail with no adverse effects up to +5.5V. The ESD protection circuitry permits the signal from going beyond the VDD supply (even with VDD = 0V) without inducing large leakage currents on the switch pins when the supply voltage is less than +5.5V. This feature complies with the USB 2.0 Specifications for short circuit protection in the event that the 5.25V VBUS line shorts to the USB signal lines. Note: When the supply voltage is above the POR threshold but below the VBUS voltage and a VBUS fault conditions occurs, the VBUS signal will be passed to the other side of the switch if the logic control pins are biased such that the switch is turned ON. USB Switches (COM2x and COM3x) The four USB FS and HS capable switches are bi-directional analog switches that can pass rail-to-rail signals with minimal distortion. With a 3.0V power supply these switches have a nominal ON-resistance of 6Ω in the 0V to 400mV signal range. The low capacitance and high bandwidth of the switches makes them ideal for USB applications. They are specifically designed to pass both USB FS (12Mbps) and USB HS (480Mbps) differential signals while meeting the USB 2.0 signal quality eye diagrams (Figures 25 and 26). The USB switches are designed with integrated protection circuitry for fault conditions as defined in the USB 2.0 Specifications-Section 7.1.1. If a condition where VBUS (5.25V) is shorted to the D+ or D- pin this will not damage the device, even without power to the IC. 1Ω Switches (COM1A and COM4A) And 6Ω Switches (COM1B and COM4B) The two 1Ω switches are bi-directional analog switches that can pass rail-to-rail signals, making them well suited for analog or digital signal routing. The low ON-resistance of the switches makes them ideal for switching ON/OFF power supply lines for applications that interface with devices that require power (ie: SIM cards or flash memory devices). With a ON-resistance of 1Ω the power dissipation through the switch is minimal. 9 The two 6Ω switches are bi-directional analog switches that can pass rail-to-rail signals, making them well suited for analog or digital signal routing such as audio, UART or Full-Speed USB. The low ON-resistance of these switches are well suited for passing audio signals with good THD performance, even with low impedance loads such as 32Ω headphones (see Figure 24 for THD performance curves). Logic Control Pins The ISL54230 contains six logic control pins, IN1 through IN4 for independently controlling each DPDT switch and two OE enable pins. The logic control pins determine the state of the switches. Refer to the “Input Select” and “OE Control” Truth Tables on page 3. When the OEx control pins are logic LOW, only the switches on COM2x and COM3x are active and the switch state determined by IN2 and IN3 respectively. When the OEx control pins are logic HIGH, all switches are active and the switch state determined by the INx control pins. When the OEx control pins are in opposing logic states either COM1x and COM2x are active or COM3x and COM4x are active depending on what states OE1 and OE2 are at. The active switches are controlled by the respective INx control pin. This feature is useful for applications that interface the ISL54230 to Master/Slave devices or controlling two SIM cards in Dual SIM Card cellphones. The OEx control pins permit total deactivation of each half of the switch blocks to disable devices connected to those switches. LOGIC CONTROL VOLTAGE LEVELS OEx = Logic “0” (Low) when VOEx ≤ 0.5V OEx = Logic “1” (High) when VOEx ≥ 1.4V INx = Logic “0” (Low) when VINx ≤ 0.5V INx = Logic “1” (High) when VINx ≥ 1.4V The logic control pins are +1.8V CMOS logic compatible (0.45V VOLMAX and 1.35V VOHMIN) for supply voltages from +1.8V to +3.6V. over a supply range of 1.8V to 3.3V (see Figure 23). At 3.6V the VIL level is 0.5V maximum. This is still below the 1.8V CMOS guaranteed low output maximum level of 0.45V, but noise margin is reduced. At 3.6V the VIH level is 1.4V minimum. While this is above the 1.8V CMOS guaranteed high output minimum of 1.35V under most operating conditions the switch will recognize this as a valid logic high. The digital input stages draws a larger supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54230 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 1.8V logic high while operating with a 3.6V supply the device draws only 1µA of current. FN6825.0 December 26, 2008 ISL54230 Application Block Diagram VDD MAIN MICROPHONE NO1A COM1A IN1 NC1A NO1B COM1B COM2A NC1B EAR BUD MICROPHONE NO2A BASEBAND CODEC NC2A IN2 NO2B COM2B NC2B MULTIMEDIA CODEC USB CONNECTOR AUDIO JACK NO3A COM3A COM4A USB TRANSCEIVER A NC3A IN3 NO3B COM3B USB TRANSCEIVER B NC3B NO4A AUDIO CODEC A NC4A IN4 NO4B COM4B OE1 OE2 NC4B GND AUDIO CODEC B µCONTROLLER OR BASEBAND PROCESSOR Typical Performance Curves TA = +25°C, Unless Otherwise Specified 10 8.0 VDD = 3.0V 9 ICOM = 40mA T = +25°C ICOM = 40mA 7.5 +85°C 7.0 7 +25°C 6 rON (Ω) rON (Ω) 8 +2.7V 6.5 +3V 6.0 -40°C 5 5.5 4 5.0 3 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 VCOM (V) FIGURE 7. ON-RESISTANCE vs SWITCH VOLTAGE; COM2x AND COM3x 10 4.5 +3.6V 0 0.05 0.10 0.15 0.20 0.25 VCOM (V) 0.30 0.35 0.40 0.45 FIGURE 8. ON- RESISTANCE vs SWITCH VOLTAGE, COM2, COM3 FN6825.0 December 26, 2008 ISL54230 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 160 160 VDD = 3.0V 140 140 ICOM = 1mA 120 120 +85°C +25°C 80 100 rON (Ω) 100 rON (Ω) T = +25°C ICOM = 1mA +2.7V 60 -40°C 60 80 +3V +3.6V 40 40 20 20 0 0 0.5 1.0 1.5 2.0 VCOM (V) 2.5 3.0 0 0 3.5 FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE; COM2x AND COM3x 1.0 1.5 2.0 2.5 VCOM (V) 3.0 3.5 4.0 FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE; COM2x AND COM3x 2.50 2.50 VDD = 3.0V 2.25 T = +25°C ICOM = 100mA 2.25 ICOM = 100mA 2.00 2.00 1.75 1.75 1.50 +85°C rON (Ω) rON (Ω) 0.5 1.25 1.50 +2.7V 1.25 +3V +25°C -40°C 0.75 0.75 0.50 +3.6V 1.00 1.00 0 0.5 1.0 1.5 2.0 2.5 3.0 0.50 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VCOM (V) VCOM (V) FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE; COM1A AND COM4A FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE;, COM1A AND COM 4A 12 12 VDD = 3.0V 11 T = +25°C ICOM = 100mA 11 ICOM = 100mA 10 10 9 9 8 8 +2.7V 7 +3V 7 +25°C 6 6 +3.6V -40°C 5 5 4 3 rON (Ω) rON (Ω) +85°C 4 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VCOM (V) FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE; COM1B AND COM4B 11 3 0 0.5 1.0 1.5 2.0 2.5 VCOM (V) 3.0 3.5 4.0 FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE; COM1B AND COM4B FN6825.0 December 26, 2008 ISL54230 1 0 0 -10 -1 -20 -2 -30 -3 -4 -5 -6 VDD = 3.0V RL = 50Ω 1M 10M 100M FREQUENCY (Hz) -50 -60 -70 -100 1k 1G 10k 100k 1M FREQUENCY(Hz) 10M 100M 1G FIGURE 16. OFF-ISOLATION; COM2x and COM3x 0 1 -10 VDD = 3.0V -20 RL = 50Ω VIN = 50mVRMS OFF-ISOLATION (dB) 0 NORMALIZED GAIN (dB) -40 -90 FIGURE 15. FREQUENCY RESPONSE; COM2x and COM3x -1 -2 -3 VDD = 3.0V -30 -40 -50 -60 -70 -80 VIN = 50mVRMS -90 RL = 50Ω -5 1M 10M 100M FREQUENCY (Hz) -100 1k 1G 10k 100k 1M FREQUENCY(Hz) 10M 100M FIGURE 18. OFF-ISOLATION; COM1A AND COM4A FIGURE 17. FREQUENCY RESPONSE; COM1A AND COM4A 0 1 -10 0 -20 VDD = 3.0V VIN = 50mVRMS RL = 50Ω OFF-ISOLATION (dB) NORMALIZED GAIN (dB) RL = 50Ω -80 VIN = 0dBm 100mVDC OFFSET -4 VDD = 3.0V VIN = 50mVRMS OFF-ISOLATION (dB) NORMALIZED GAIN (dB) Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) -1 -2 -3 VDD = 3.0V -4 -5 1M -30 -40 -50 -60 -70 VIN = 50mVRMS -8 0 RL = 50Ω -90 10M 100M FREQUENCY (Hz) 1G FIGURE 19. FREQUENCY RESPONSE; COM1B and COM4B 12 -100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 20. OFF-ISOLATION; COM1B and COM4B FN6825.0 December 26, 2008 ISL54230 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 0 0 VDD = 3.0V -40 VDD = 3.0V -20 VIN = 0dBm COM3A TO COM4A RL = 50Ω CROSSTALK (dB) CROSSTALK (dB) -20 -60 -80 -100 -40 -60 -80 10M 100M FREQUENCY (Hz) -120 1M 1G 10M 100M FREQUENCY (Hz) 1G FIGURE 22. CROSSTALK FIGURE 21. CROSSTALK 0.95 0.20 0.90 0.18 0.85 0.16 COM1B AND COM 4B 0.14 0.80 THD + N (%) THRESHOLD VOLTAGE (V) COM3A TO COM4B RL = 50Ω -100 -120 1M 0.75 0.70 0.65 0.12 0.10 VDD = 3.3V VIN = 100mVRMS WITH 1.5VDC OFFSET RL = 32Ω 0.08 0.06 0.60 0.04 0.55 0.50 2.6 VIN = 0dBm COM1A AND COM 4A 0.02 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 3.7 FIGURE 23. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE 13 0 20 100 200 1k 2k FREQUENCY (Hz) 10k 20k FIGURE 24. TOTAL HARMONIC DISTORTION vs FREQUENCY FN6825.0 December 26, 2008 ISL54230 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE SCALE (0.5V/DIV) VDD = 3.3V TIME SCALE (10ns/DIV) FIGURE 25. EYE PATTERN: 12Mbps; COM2x or COM3x SWITCH IN THE SIGNAL PATH 14 FN6825.0 December 26, 2008 ISL54230 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE SCALE (0.1V/DIV) VDD = 3.3V TIME SCALE (0.2ns/DIV) FIGURE 26. EYE PATTERN: 480Mbps; COM2x or COM 3x SWITCH IN THE SIGNAL PATH Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 1216 PROCESS: Submicron, Dual Gate, Analog CMOS 15 FN6825.0 December 26, 2008 ISL54230 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) L32.5x5A 2X 0.15 C A D A 32 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WJJD-1 ISSUE C) D/2 MILLIMETERS 2X 6 INDEX AREA N 0.15 C B 1 2 3 SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.30 5, 8 3.55 7, 8 A3 E/2 b E D D2 B TOP VIEW 0.20 REF 0.18 5.00 BSC 3.30 C 0.08 C SEATING PLANE A3 SIDE VIEW A1 3.45 - E 5.00 BSC - 5.75 BSC 9 3.30 e / / 0.10 C - E1 E2 A 0.25 3.45 3.55 0.50 BSC 7, 8 - k 0.20 - - - L 0.30 0.40 0.50 8 N 32 2 Nd 8 3 Ne 8 3 Rev. 2 05/06 NX b 5 0.10 M C A B D2 NX k D2 2 (DATUM B) 8 7 N (DATUM A) 6 INDEX AREA E2 E2/2 3 2 1 NX L N 7 (Ne-1)Xe REF. 8 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. e 8 (Nd-1)Xe REF. BOTTOM VIEW A1 NX b 5 SECTION "C-C" All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6825.0 December 26, 2008