PHT www.vishay.com Vishay Sfernice High Stability - High Temperature (230 °C) Thin Film Wraparound Chip Resistors, Sulfur Resistant FEATURES • Operating temperature range: -55 °C; +215 °C • Storage temperature: -55 °C; +230 °C • Gold terminations (< 1 μm thick) • 5 sizes available (0402, 0603, 0805, 1206, 2010); other sizes upon request INTRODUCTION For applications such as down hole applications, the need for parts able to withstand very severe conditions (temperature as high as 215 °C powered or up to 230 °C un-powered) has leaded Vishay Sfernice to push out the limit of the thin film technology. Designers might read the application note: Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chip Resistors and Arrays (P, PRA etc…) (High Temperature Application) www.vishay.com/doc?53047 in conjunction with this datasheet to help them to properly design their PCBs and get the best performances of the PHT. Vishay Sfernice R&D engineers will be willing to support any customer design considerations. • Temperature coefficient down to 15 ppm (-55 °C; +215 °C) • Tolerance down to 0.01 % • Load life stability: 0.35 % max. after 2000 h at 220 °C (ambient) at Pn • Shelf life stability: 0.7 % typ. (1 % max.) after 15 000 h at 230 °C • SMD wraparound • TCR remains constant after long term storage at 230 °C (15 000 h) • Sulfur resistant (per ASTM B809-95 humid vapor test) • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 STANDARD ELECTRICAL SPECIFICATIONS MODEL SIZE RESISTANCE RANGE RATED POWER (1)(2) P215 °C W LIMITING ELEMENT VOLTAGE V TOLERANCE (2) ±% TEMPERATURE COEFFICIENT (3) ± ppm/°C PHT0402 0402 10 to 130K 0.0189 50 0.01, 0.02, 0.05, 0.1, 0.5, 1 10, 15, 25, 30, 50, 55 PHT0603 0603 10 to 320K 0.0375 75 0.01, 0.02, 0.05, 0.1, 0.5, 1 10, 15, 25, 30, 50, 55 PHT0805 0805 10 to 720K 0.06 150 0.01, 0.02, 0.05, 0.1, 0.5, 1 10, 15, 25, 30, 50, 55 PHT1206 1206 10 to 2.7M 0.1 200 0.01, 0.02, 0.05, 0.1, 0.5, 1 10, 15, 25, 30, 50, 55 PHT2010 2010 10 to 7.5M 0.2 (4) 300 0.01, 0.02, 0.05, 0.1, 0.5, 1 10, 15, 25, 30, 50, 55 Notes (1) For power handling improvement, please refer to application note 53047: “Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chip Resistors and Arrays (High Temperature Applications)” www.vishay.com/doc?/53047 and consult Vishay Sfernice (2) See Table 2 on next page (3) See Table 1 on next page (4) It is possible to dissipate up to 0.3 W, but there will be an additional drift of 0.1 % after load life CLIMATIC SPECIFICATIONS Operating temperature range -55 °C; +215 °C MECHANICAL SPECIFICATIONS Substrate Alumina Resistive Element Storage temperature range -55 °C; +230 °C Passivation Nichrome (NiCr) Silicon nitride (Si3N4) Protection Terminations PERFORMANCE VS. HUMID SULFUR VAPOR Test conditions Test results Revision: 14-Jan-15 50 °C ± 2 °C, 85 % ± 4 % RH, exposure time 500 h Epoxy + silicone Gold (< 1 μm) over nickel barrier Note • For other terminations, please consult Resistance drift < (0.05 % R + 0.05 ), no corrosion products observed Document Number: 53050 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PHT www.vishay.com Vishay Sfernice TABLE 1 - TEMPERATURE COEFFICIENT Y E H 10 ppm/°C -55 °C; +155 °C 15 ppm/°C -55 °C; +215 °C 25 ppm/°C -55 °C; +155 °C 30 ppm/°C -55 °C; +215 °C 50 ppm/°C -55 °C; +155 °C 55 ppm/°C -55 °C; +215 °C TABLE 2 - BEST TOLERANCE AND TCR VS. OHMIC VALUE SERIES 0402 0603 0805 1206 2010 RANGE () TOL. (± %) TCR CODE 10 to < 100 0.05; 0.1; 0.5; 1 Y; E; H 100 to < 90K 0.01; 0.02; 0.05; 0.1; 0.5; 1 Y; E; H 90K to 130K 0.01; 0.02; 0.05; 0.1; 0.5; 1 E; H 10 to < 100 0.05; 0.1; 0.5; 1 Y; E; H 100 to < 210K 0.01; 0.02; 0.05; 0.1; 0.5; 1 Y; E; H 210K to 320K 0.01; 0.02; 0.05; 0.1; 0.5; 1 E; H 10 to < 100 0.05; 0.1; 0.5; 1 Y; E; H 100 to < 480K 0.01; 0.02; 0.05; 0.1; 0.5; 1 Y; E; H 480K to 720K 0.01; 0.02; 0.05; 0.1; 0.5; 1 E; H 10 to < 100 0.05; 0.1; 0.5; 1 Y; E; H 100 to < 1.8M 0.01; 0.02; 0.05; 0.1; 0.5; 1 Y; E; H 1.8M to 2.7M 0.01; 0.02; 0.05; 0.1; 0.5; 1 E; H 10 to < 100 0.05; 0.1; 0.5; 1 Y; E; H 100 to < 5M 0.01; 0.02; 0.05; 0.1; 0.5; 1 Y; E; H 5M to 7.5M 0.01; 0.02; 0.05; 0.1; 0.5; 1 E; H PHT STABILITY CURVE High Temperature Drift vs. Time 2.0 1.8 1.6 Drift in % 1.4 1.2 1.0 T = 230 °C 0.8 With Pd 0.6 (Tj = 230 °C) T = 215 °C T = 200 °C T = 185 °C 0.4 0.2 0.0 0 2000 4000 6000 8000 10 000 12 000 14 000 Time in h Note • Stability will be dependent on resistivity of resistor. Above curves are worst case. Revision: 14-Jan-15 Document Number: 53050 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PHT www.vishay.com Vishay Sfernice Rated Power (%) POWER DERATING CURVE 350 300 250 200 150 100 50 0 0 50 100 150 200 250 Ambient Temperature in °C DIMENSIONS in millimeters (inches) A D D B C E E CASE SIZE A B MAX. TOL. +0.152 (+0.006) MIN. TOL. -0.152 (-0.006) MAX. TOL. +0.127 (+0.005) MIN. TOL. -0.127 (-0.005) NOMINAL NOMINAL 0402 1.00 (0.039) 0.60 (0.024) 0603 1.52 (0.060) 0.85 (0.033) 0805 1.91 (0.075) 1.27 (0.050) 1206 3.06 (0.120) 1.60 (0.063) 2010 5.08 (0.200) 2.54 (0.100) D/E C Termination N: 0.5 (0.02) ± 0.127 (0.005) Termination G: 0.4 (0.016) ± 0.051 (0.002) NOMINAL TOLERANCE 0.25 (0.010) 0.1 (0.004) 0.38 (0.015) 0.40 (0.016) 0.13 (0.005) 0.48 (0.019) SUGGESTED LAND PATTERN (TO IPC-7351A) Gmin. Xmax. Zmax. DIMENSIONS (in millimeter) CHIP SIZE Zmax. Gmin. Xmax. 0402 1.55 0.15 0.73 0603 2.37 0.35 0.98 0805 2.76 0.74 1.40 1206 3.91 1.85 1.73 2010 5.93 3.71 2.67 Caution: Performances obtained with following mounting conditions: PCB: polyimide Solder paste: PbSnAg (93.5/5/1.5) Revision: 14-Jan-15 Document Number: 53050 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PHT www.vishay.com Vishay Sfernice POPULAR OPTIONS It is recommended to consult Vishay Sfernice for availability first. Option: Enlarged terminations: For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heatsink (see application note: 53048 “Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA Arrays, CHP Thick Film)” www.vishay.com/doc?53048. Option to order: 0063 (applies to size 1206 / 2010). DIMENSIONS (Option 0063) in millimeters Bottom view for mounting Uncoated ceramic A Enlarged termination B F D E CASE SIZE A B E D MAX. TOL. +0.152 MIN. TOL. -0.152 MAX. TOL. +0.127 MIN. TOL. -0.127 MAX. TOL. +0.13 MIN. TOL. -0.13 MAX. TOL. +0.13 MIN. TOL. -0.13 NOMINAL NOMINAL NOMINAL NOMINAL 1206 3.06 1.60 0.40 1.215 2010 5.08 2.54 0.48 2.25 F NOMINAL MIN. MAX. 0.63 0.50 0.76 SUGGESTED LAND PATTERN (Option 0063) Gmin. Xmax. Zmax. CHIP SIZE DIMENSIONS (in millimeter) Zmax. 1206 3.91 2010 5.93 Revision: 14-Jan-15 Gmin. 0.50 Xmax. 1.73 2.67 Document Number: 53050 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PHT www.vishay.com Vishay Sfernice PACKAGING PACKAGING RULES ESD packaging available: waffle-pack and plastic tape and reel (low conductivity). Paper tape available in standard (for size 0402) and upon request (ESD only) (for sizes 0603, 0805, and 1206). Waffle Pack Can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. When quantity ordered exceeds maximum quantity of a single waffle pack, the waffle packs are stacked up on the top of each other and closed by one single cover. To get “not stacked up” waffle pack in case of ordered quantity > maximum number of pieces per package: Please consult Vishay Sfernice for specific ordering code. Tape and Reel Can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. When quantity ordered is between the MOQ and the maximum reel capacity, only one reel is provided. When several reels are needed for ordered quantity within MOQ and maximum reel capacity: please consult Vishay Sfernice for specific ordering code. NUMBER OF PIECES PER PACKAGE SIZE MOQ TAPE AND REEL WAFFLE PACK 2" × 2" MIN. MAX. 0402 0603 0805 5000 100 100 8 mm 100 1206 140 2010 60 TAPE WIDTH 4000 2000 8 mm (1) Note (1) 12 mm on request GLOBAL PART NUMBER INFORMATION Global Part Numbering: PHT1206Y1001BGT063 P H GLOBAL MODEL PHT T 1 2 0 6 Y 1 0 0 1 B G T 0 6 3 SIZE TCR VALUE TOLERANCE TERMINATION PACKAGING OPTION 0402 0603 0805 1206 2010 Y E H The first three digits are significant figures and the last digit specifies the number of zeros to follow, R designates decimal point L = 0.01 % P = 0.02 % W = 0.05 % B = 0.1 % D = 0.5 % F=1% G = gold N = tin/silver (1) For more information see codification of Packaging table Leave blank if no option 10R0 = 10 3901 = 3900 1004 = 1 M Note (1) For usage at temperatures up to 200 °C maximum N (tin/silver termination are available upon request) CODIFICATION OF PACKAGING CODE 18 WAFFLE PACK W WA PLASTIC TAPE (in standard for all sizes except 0402) T TA TB TC TD TE TF PAPER TAPE (in standard for 0402, option for other sizes) PT PA PB PC PD PE PF Revision: 14-Jan-15 PACKAGING 100 min., 1 mult 100 min., 100 mult (available only on size 1206) 100 min., 1 mult 100 min., 100 mult 250 min., 250 mult 500 min., 500 mult 1000 min., 1000 mult 2500min., 2500 mult Full tape (quantity depending on size of chips) 100 min., 1 mult 100 min., 100 mult 250 min., 250 mult 500 min., 500 mult 1000 min., 1000 mult 2500min., 2500 mult Full tape (quantity depending on size of chips) Document Number: 53050 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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