CHPHT www.vishay.com Vishay Sfernice High Temperature (245 °C) Thick Film Chip Resistor FEATURES • High temperature (245 °C) • Large ohmic value range 0.1 to 100 M Available • Operating temperature range (-55 °C to +230 °C) • SMD wraparound chip resistor For applications such as down hole applications or aircraft breaking systems, the need for parts able to withstand very severe conditions (temperature as high as 230 °C powered or up to 245 °C un-powered) has leaded Vishay Sfernice to push out the limit of the thick film technology. Designers might read the application note “Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chips Resistors and Arrays (P, PRA etc.) (High Temperature Applications)” (www.vishay.com/doc?53047) in conjunction with this data sheet to help them to properly design their PCBs and get the best performances of the CHPHT. Vishay Sfernice R&D engineers will be willing to support any customer design considerations. • Storage temperature range (-55 °C to +245 °C) • Gold terminations for HMP process (< 1 μm thick) for temperature up to 245 °C • Tin/silver terminations for operating temperature up to 200 °C • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DIMENSIONS in millimeters D C B E CASE SIZE A A B C D E ± 0.152 ± 0.127 ± 0.127 ± 0.127 ± 0.127 0603 1.60 0.90 0.38 0.31 0.40 0805 1.85 1.25 0.38 0.31 0.50 1206 3.00 1.73 0.38 0.40 0.50 2010 5.03 2.64 0.50 0.50 0.50 SUGGESTED LAND PATTERN (to IPC-7351A) Gmin. Xmax. Zmax. CASE SIZE Zmax. Gmin. Xmax. 0603 2.15 0.39 1.03 0805 2.70 0.44 1.38 1206 3.85 1.59 1.85 2010 5.88 3.62 2.77 Revision: 21-Jul-14 Document Number: 52032 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CHPHT www.vishay.com Vishay Sfernice STANDARD ELECTRICAL SPECIFICATIONS RATED POWER Pn W (at 230 °C) LIMITING ELEMENT VOLTAGE V MAX. OVERLOAD VOLTAGE V TOLERANCE ±% TEMPERATURE COEFFICIENT ± ppm/°C MODEL SIZE RESISTANCE RANGE CHPHT 0603 0.1 to 25M 0.0125 50 100 1, 2, 5 100, 200 CHPHT 0805 0.1 to 25M 0.02 150 300 1, 2, 5 100, 200 CHPHT 1206 0.1 to 50M 0.025 200 400 1, 2, 5 100, 200 CHPHT 2010 0.1 to 100M 0.1 200 400 1, 2, 5 100, 200 PACKAGING CLIMATIC SPECIFICATIONS Operating temperature range -55 °C to +230 °C Storage temperature range -55 °C to +245 °C ESD packaging available: Waffle pack and plastic tape and reel (low conductivity). Paper tapes available on request (ESD only). (For 0603, 0805, and 1206 only.) MECHANICAL SPECIFICATIONS Substrate NUMBER OF PIECESPER PACKAGE Alumina SIZE Technology Thick film (Ruthenium oxyde) Protection Parts have double and organic coating (0R5 to 100M) BEST TOL. AND TCR VERSUS OHMIC VALUE OHMIC VALUES BEST TCR ppm/°C 1 % (F) 5 < R < 10M 100 (K) 2 % (G) 1 < R < R max. 200 (L) 5 % (J) 0.1 < R < R max. 200 (L) MAX. 5000 0805 100 1206 140 2010 60 4000 8 mm 2000 PACKAGING RULES Waffle Pack Can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. When quantity ordered exceeds maximum quantity of a single waffle pack, the waffle packs are stacked up on the top of each other and closed by one single cover. To get “not stacked up” waffle pack in case of ordered quantity > maximum number of pieces per package: Please consult Vishay Sfernice for specific ordering code Tape and Reel Can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. When quantity ordered is between the MOQ and the maximum reel capacity, only one reel is provided. When several reels are needed for ordered quantity within MOQ and maximum reel capacity: Please consult Vishay Sfernice for specific ordering code POWER DERATING CURVE Rated Power (%) MIN. TAPE WIDTH 100 Note • Refer to Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Components” (document number: 52029) for recommended reflow profile. Profile #3 applies. TIGHTEST TOLERANCE TAPE AND REEL 0603 N (W/A): SnAg over nickel barrier for temperature up to 200 °C G (W/A) type: Gold (< 1 μm) over nickel barrier for temperature up to 245 °C Terminations WAFFLE PACK 1200 1000 800 600 400 200 0 0 50 100 150 200 250 300 Ambient Temperature in °C Revision: 21-Jul-14 Document Number: 52032 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CHPHT www.vishay.com Vishay Sfernice POPULAR OPTIONS For any option it is recommended to consult Vishay Sfernice for availability first. Option: Enlarged terminations: For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heat sinks (see application note: “Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA Arrays, CHP Thick Film” (www.vishay.com/doc?53048). Option to order: 0063 (applies to size 1206/2010). DIMENSIONS (Option 0063) in millimeters Bottom view for mounting Uncoated ceramic A Enlarged termination B F D E A B E D MAX. TOL. + 0.152 MIN. TOL. - 0.152 MAX. TOL. + 0.127 MIN. TOL. - 0.127 MAX. TOL. + 0.13 MIN. TOL. - 0.13 MAX. TOL. + 0.13 MIN. TOL. - 0.13 NOMINAL NOMINAL NOMINAL NOMINAL NOMINAL MIN. MAX. 1206 3.06 (0.120) 1.60 (0.063) 0.40 (0.016) 1.22 (0.048) 0.63 (0.024) 0.50 (0.020) 0.76 (0.030) 2010 5.08 (0.200) 2.54 (0.100) 0.48 (0.019) 2.23 (0.088) 0.63 (0.024) 0.50 (0.020) 0.76 (0.030) CASE SIZE F SUGGESTED LAND PATTERN (Option 0063) Gmin. Xmax. Zmax. DIMENSIONS (in millimeters) CHIP SIZE Zmax. Gmin. Xmax. 1206 3.91 (0.154) 0.50 (0.020) 1.73 (0.068) 2010 5.93 (0.233) 0.50 (0.020) 2.67 (0.105) Revision: 21-Jul-14 Document Number: 52032 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CHPHT www.vishay.com Vishay Sfernice PERFORMANCE TESTS CONDITIONS REQUIREMENTS TYPICAL VALUES AND DRIFTS 5N for 10 s ± (0.25 % + 0.05 ) < ± 0.1 % Resistance to solder heat Immersion 10 s in Sn/Pb 60/40 at +260 °C ± (0.25 % + 0.05 ) < ± 0.1 % Rapid temperature change 5 cycles -55 °C to +155 °C ± (0.25 % + 0.05 ) < ± 0.1 % Phase A dry heat Phase B damp heat Phase C cold -55 °C Phase D damp heat 5 cycles ± (1 % + 0.05 ) < ± 0.2 % Termination adhesion Climatic sequence 56 days ± (1 % + 0.05 ) < ± 0.2 % Moisture resistance AEC-Q200 85 °C/85 % RH/Pn 1000 h 3 % + 0.05 Max. < 3 % + 0.05 Short time overload 6.25 Pn for 2 s ± (0.25 % + 0.05 ) < ± 0.1 % Load life 1000 h at rated power at 230 °C - 1 % max. Shelf life 1000 h at 245 °C - 1 % max. Humidity (steady state) GLOBAL PART NUMBER INFORMATION Global Part Numbering: CHPHT0805K1001FGT C GLOBAL MODEL CHPHT H P H T 0 8 0 5 K 1 0 0 1 F G T SIZE TCR VALUE TOLERANCE TERMINATION (1) PACKAGING OPTION 0603 0805 1206 2010 K = 100 ppm L = 200 ppm The first 3 digits are significant figures and the last digit specifies the number of zeros to follow. R designates decimal point F=±1% G=±2% J=±5% N: SnAg over nickel barrier G: Gold over nickel barrier For more information see “Codification of packaging” table Leave blank if no option 10R0 = 10 3901 = 3900 1004 = 1 M Note (1) N terminations for temperature up to 200 °C G terminations for temperature up to 230 °C Revision: 21-Jul-14 Document Number: 52032 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CHPHT www.vishay.com Vishay Sfernice CODIFICATION OF PACKAGING WAFFLE PACK W 100 min., 1 mult WA 100 min., 100 mult (available only in size 1206) PLASTIC TAPE (Standard for all sizes.) T 100 min., 1 mult TA 100 min., 100 mult TB 250 min., 250 mult TC 500 min., 500 mult TD 1000 min., 1000 mult TE 2500min., 2500 mult TF Full tape (quantity depending on size of chips) PAPER TAPE (Available for 0603, 0805, and 1206. Please consult Vishay Sfernice for other sizes.) PT 100 min., 1 mult PA 100 min., 100 mult PB 250 min., 250 mult PC 500 min., 500 mult PD 1000 min., 1000 mult PE 2500min., 2500 mult PF Full tape (quantity depending on size of chips) CODIFICATION OF OPTIONS ON TWO DIGITS OPTION OPTION 2 DIGITS OPTION OPTION 2 DIGITS CODIFICATION OF SIZES CODE 18 CODE 40 CODE 18 CODE 40 7 02016 M 22 1A 8 0302 N 33 0127 1B 9 0402 O 44 0128 1C A 0502 P 55 .. B 0505 Q 515 0320 8M C 0603 R 48 0321 8N D 0805 S 408 0E 0322 8O E 1005 T 816 0F 0323 8P F 1010 U 914 .. 0324 8Q G 1020 V 073 0124 0Y 0325 8R H 1206 W 074 0125 0Z .. .. I 1505 X 100 J 2010 Y 135 K 2208 Z 182 L 2512 .. .. 0126 0099 99 0100 0A 0101 0B .. 0102 0C 0103 0D 0104 0105 .. Revision: 21-Jul-14 Document Number: 52032 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000