AN2817 Application note Guidelines for application design using L5962 Introduction L5962 is a multi-regulator especially intended for high-end automotive car-radio applications. L5962 integrates 3 linear voltage regulators, 2 high side drivers and a switching regulator to provide complete car-radio system control. It has an extremely low quiescent current in standby mode of operation, that guarantees a proper supply to the microcontroller even with the system in 'sleep' condition. 3 regulators are VSTBY, VLR1 and VLR2. VSTBY is a 3.3V/5V stand-by linear regulator with 150mA maximum current capability. VLR1 is a 5V/8.5V switched linear regulator able to deliver 350mA. VLR2 is a 3.3V/5.0V/5.5V/6.0V/7.0V/7.5V/8.0V/10.0V switched linear regulator with 1A load current capability. The output voltages of VLR1 and VLR2 are configurable with I2C bus. Device embeds also 2 high side drivers (HSD1/2) that can be activated/deactivated through I2C bus. Additional features provided by the L5962 are: reset function, load dump protection, thermal shutdown, under voltage detection and over current limitation for every block. Figure 1. September 2013 Demonstration board Rev 2 1/33 www.st.com Contents AN2817 Contents 1 Pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Low voltage warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.1 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.2 Oscillator and synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3.3 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.4 PWM output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.5 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Compensating linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Trimming the threshold of low-voltage warning . . . . . . . . . . . . . . . . . . 14 6 Compensating switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 LC filter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 PWM comparator transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 Examples of system compensation: impact of ESR . . . . . . . . . . . . . . . . . 19 7 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 Device performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 8.1 Switching regulator efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2 Switching regulator transient response . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 VSTBY transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.4 VLR1 transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 VLR2 transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device utilization hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.1 10 2/33 Positive-output buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AN2817 List of tables List of tables Table 1. Table 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3/33 List of figures AN2817 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. 4/33 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PowerSO36 (slug up) outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Linear regulator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Low voltage warning high level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switch regulator block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Synchronizer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Diagram of current protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PWM output stage block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Linear regulator general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bode plot of VLR1 with ESR=0.1ohm and C=1µF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Low-voltage warning block diagram with external resistor divider . . . . . . . . . . . . . . . . . . . 14 Switching regulator block diagram with compensation network . . . . . . . . . . . . . . . . . . . . . 15 Bode diagram of LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bode plots of a type-3 compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Case 1 open-loop Bode plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Case 2 open-loop Bode plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Case 3 open-loop Bode plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 L5962 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Switching regulator undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Switching regulator overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VSTBY undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 VSTBY overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 VLR1 undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VLR1 overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VLR2 undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VLR2 overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Diagram of positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 10V). 28 Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 8V). . 29 Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 5V). . 29 Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 3.3V) 30 Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 1.2V) 30 L5962 behavior in buck-boost configuration (Iload = 500mA) . . . . . . . . . . . . . . . . . . . . . . . 31 AN2817 1 Pins function Pins function Figure 2. PowerSO36 (slug up) outline drawing Figure 3. Pin connection (top view) N.C. 36 1 TAB N.C. 35 2 PGND CLIM 34 3 CBS VFB 33 4 PH VCMP 32 5 N.C. SOST 31 6 N.C. SYNC 30 7 SUBGND SCL 29 8 VINsw EN 28 9 HSD1 RST 27 10 VBAT VLR2 26 11 HSD2 VINLR2 25 12 VBATP SDA 24 13 RSTDLY VLR1 23 14 VSTBY VBATW 22 15 VSTBYSEL LVWIN 21 16 AGND N.C. 20 17 N.C. N.C. 19 18 N.C. AC00429 Table 1. Pin connection Pin # Pad Name Function 1 TAB 2 PGND 3 CBS 4 PH Switching stage output 5 N.C. Not connected 6 N.C. Not connected 7 SUBGND 8 VINsw Switching regulator supply voltage 9 HSD1 High Side Driver 1 10 VBAT VLR1/HSD1/HSD2 supply voltage 11 HSD2 High Side Driver 2 Switching regulator ground Bootstrap for switching regulator Substrate ground 5/33 Pins function AN2817 Table 1. 6/33 Pin connection (continued) Pin # Pad Name Function 12 VBATP 13 RSTDLY Reset delay function 14 VSTBY Stand-by regulator output 15 VSTBYSEL 16 AGND Analog ground 17 N.C. Not connected 18 N.C. Not connected 19 N.C. Not connected 20 N.C. Not connected 21 LVWIN Battery detector adjustment input 22 VBATW Battery detector output (open-drain) 23 VLR1 Switched linear regulator 1 24 SDA I2Cbus DATA 25 VINLR2 26 VLR2 Switched linear regulator 2 27 RST Reset 28 EN Enable 29 SCL I2Cbus CLOCK 30 SYNC Switching regulator SYNC function 31 SOST Switching regulator soft-start 32 VCMP Switching regulator compensation 33 VFB Switching regulator feedback 34 CLIM Switching regulator current limit selector 35 N.C. Not connected 36 N.C. Not connected Stand-by regulator supply voltage Stand-by regulator selector VLR2 supply voltage AN2817 2 Block diagram Block diagram Figure 4. Block diagram VINSW VBATP Bandgap External Storage Reference PH Switching Regulator POR & Startup Logic CBS CLIM VFB VCMP SOST Standby Regulator Oscillator SYNCH LVWIN VBATVW RST RSTDLY VSTBYSEL VSTBY Clock UV / OV Detect Linear Regulator #1 Synch Logic Reset & Delay Linear Regulator #2 SDA SCL I2Cbus Logic VLR1 VINLR2 VLR2 HSD HSD1 HSD HSD2 EN Ground AC00428 TAB PGND AGND SUBS VBAT 7/33 Functional description 3 AN2817 Functional description The main internal blocks are shown in Figure 4, where is reported the device block diagram. They are: 3.1 ● One standby linear regulator (VSTBY) ● Two switched linear regulators selectable between 5/8.5 V (VLR1) and 3.3 V/5.0 V/ 5.5 V/ 6.0 V/7.0 V/7.5 V/8.0 V/10.0 V (VLR2) respectively ● One independent, adjustable, step-down, synchronous switching voltage regulator using internal DMOS transistors ● Synchronization function for switching regulator ● Soft-start control for switching regulator to protect external components from in-rush currents during turn-on ● Two protected, switched high-side drivers (HSD1, HSD2) ● VSTBY out-of-regulation detection with configurable delay (RST, RSTDLY) ● Battery voltage (under/over) warning output (VBATVW). Under-voltage threshold adjustable with external divider through dedicated pin ● I2C interface for output voltage configuration of linear regulators and control functions ● Current-limit and independent thermal shutdown protection on all regulators and high side drivers ● Over-voltage detection and shutdown on all switched outputs ● Under-voltage lockout on low-voltage reset output Linear regulators Figure 5 shows the general block diagram of a linear regulator. It consists of Error Amplifier (EA), Driver (DR), Compensation Network, Load Dump Protection, Thermal Shutdown, Current Limiter and resistor divider for output level setting. The compensation consists of R1 and C1, whose introduce a zero in the transfer function to obtain enough Phase Margin in OUT_REG and thus guarantee loop stability. The output PMOS has a resistor in series at its Source terminal, RCL: the current is sensed through RCL and, if it reaches a predetermined threshold, the internal current limiting circuit will increase the gate voltage of power PMOS to clamp the output current. 8/33 AN2817 Functional description Figure 5. Linear regulator circuit block diagram VIN INTERNAL CURRENT LIMITING THERMAL SHUTDOWN LOADDUMP PROTECTION RCL VBG EA DR R1 OUT_REG EN_REG C1 R2 R3 3.2 Low voltage warning Figure 6 shows an high-level block diagram of low-voltage warning circuit. VBAT is divided by R1 and R2, whose values are internally fixed. When VBAT is decreasing so that LVWIN voltage gets lower than an internal reference (VBG) the comparator turns on the NPN transistor: VBATW is thus pulled down to ground, and warning is signaled. Figure 6. Low voltage warning high level block diagram VBAT VBATW R1 comparator LVWIN VBG R2 9/33 Functional description 3.3 AN2817 Switching regulator L5962 switching regulator (shown in Figure 7) works in voltage mode. An error amplifier compares VFB and VBG and amplifies the difference, its output voltage is compared with the output of an internal Ramp Generator by a voltage comparator to produce the PWM signal. In the logic block other signals as Freq and the over current protection flag are elaborated along with PWM signal to control DC/DC behavior. The logic block output is provided to the drivers of high side NDMOS and low side NDMOS separately to drive the internal power switches. Figure 7. Switch regulator block diagram CLIM VINsw Overcurrent protection Freq CBS Ramp Generator Logic and Dead time Control BG PHASE + Slow Start PWM + EA – – SOST 3.3.1 VFB VCMP SWGND PGND Soft-start The soft-start block (Slow Start inFigure 7) protects external components from inrush current during switching regulator turn-on. Actually, soft-start function is realized by an internal resistor in series with an external capacitor, to obtain a low enough time constant for the turn-on transition. 3.3.2 Oscillator and synchronizer Figure 8 shows the block diagram of the internal synchronizer. Oscillator provides the signal (OSC) that sets the switching frequency of the device, fixed at 200 kHz. SYNC represents the external frequency signal. OSC and SYNC are compared by Freq_Comparator block: if the frequency of SYNC is higher than the one of OSC the Out_Freq of Multiplexer is equal to the frequency of SYNC and vice versa. Out_Freq signal is used as the PWM control signal and as the input of Ramp Generator. User should take into account that SYNC signal can't be applied/disconnected/ quickly changed during regulator operation, otherwise a significant voltage transition may be generated on the regulated voltage due to the intrinsic relatively slow loop response 10/33 AN2817 Functional description characterizing voltage mode DC/DC converters. Higher transients occur in particular in high Vout and high load current conditions. Figure 8. Synchronizer block diagram Multiplexer SYNC S1 Out_Freq D OSC S2 C ENB Freq_Comparator 3.3.3 Current protection Switching regulator is equipped with two over current protection circuits (OCP), the former called PWM_OCP and the latter STG_OCP, which are shown in Figure 9. When output current level is in normal range both PWM_OCP and STG_OCP output flags are low. When output current increase above a certain threshold (fixed by CLIM) PWM_OCP is pulled high: when this happens PH pin is forced to 0V, clamping duty-cycle value. In extreme conditions like short circuit to ground of the output, PWM_OCP protection could be not enough: if current through high side NDMOS continued to increase even when PWM_OCP protection is operating, STG_OCP gets activated and turns immediately off the regulator, keeping it off for 8 periods. STG_OCP threshold is ~2A higher than the PWM_OCP one. Figure 9. Diagram of current protection circuit VBAT Current of High side NDMOS 5V PWM_OCP R2 R3 5V STG_OCP R4 VBG 11/33 Functional description 3.3.4 AN2817 PWM output stage Switching regulator output stage (shown inFigure 10) consists basically of two driver circuits, two NDMOS, a diode and a bootstrap circuit. In order to avoid shoot-through the two NDMOS can not be turned on at the same time: prior of turning on H-NDMOS drivers detect the gate voltage of L-NDMOS to verify it's effectively in OFF state. In the same way, before L-NDMOS is turned on drivers verify that H-NDMOS is in OFF state. Thanks to the presence of bootstrap capacitor H-NDMOS gate is driven with a Vs+10V voltage and works in linear region with small output impedance. Figure 10. PWM output stage block diagram VBAT H-NDMOS Strap Cap DR OUTPUT PH L-NDMOS DR 3.3.5 Thermal shutdown Switching regulator embeds a thermal protection circuit that turns off the power stage if the local internal temperature of the chip gets higher than a fixed threshold (160°C). The thermal shutdown signal is one of the input signals of Logic Block and thus influences directly the power stage control. The sensing element inside the chip is very close to the power NDMOS area ensuring an accurate and fast temperature detection. 12/33 AN2817 4 Compensating linear regulators Compensating linear regulators In Figure 11 the high-level block diagram of linear regulators is shown. The majority of cases of oscillations in LDO applications are caused by the ESR of the output capacitor being too high or too low. When selecting an output capacitor for an LDO, a solid tantalum capacitor is usually the best choice. The value of the capacitor shouldn't be too small, otherwise it won't be able to prevent arising of high overshoots and undershoots on the output voltage. LDO regulators require the ESR of the output capacitor to be within a certain range to assure regulator stability. Increasing the capacitor ESR will decrease the frequency of the zero in the transfer function consequently increasing the loop bandwidth but, when ESR is too high, there will not be enough phase margin at the unity gain frequency, eventually causing instability. L5962 linear regulators have been designed to guarantee stability even when ceramic capacitors are applied to their output and thus ESR is very small, all over temperature range. Consequently, it is just recommended to use capacitors with C > 0.5µF for filtering the output of VSTBY, VLR1 and VLR2. Figure 11. Linear regulator general block diagram VBAT VBG Output R1 ESR R2 C Figure 12. Bode plot of VLR1 with ESR=0.1ohm and C=1µF 13/33 Trimming the threshold of low-voltage warning 5 AN2817 Trimming the threshold of low-voltage warning Figure 13 shows the block diagram of L5962 Low-voltage Detector to which an external resistor divider R3-R4 has been connected. By changing the values of R3 and R4 a trimming of the low-voltage detector threshold can be obtained: R3 and R4 values must be chosen in a way that, at the desired VBAT level to be detected, LVWIN pin voltage is equal to 1.25V. Being R1 and R2 in the range of M, in order for the detection not to be affected by them R3 and R4 should be chosen with an order of magnitude of k. Figure 13. Low-voltage warning block diagram with external resistor divider VBAT R3 VBATW R1=13.89M ohm comparator LVWIN VBG R4 14/33 R2=2.83M ohm AN2817 6 Compensating switching regulator Compensating switching regulator To compensate the switching regulator a Type-3 compensation network is suggested, realized by R6,C2,C3,R3,C4 and R5 as shown in Figure 14. This kind of network implements two zeroes to counteract the effects of the double pole introduced by output L-C filter, helping in stabilizing the system. Figure 14. Switching regulator block diagram with compensation network SAW TOOTH Vcc ERROR AMPLIFIER L VBG VFB Output R6 R3 PWM COMPARATOR LC FILTER C3 C2 C4 R4 C R5 COMPENSATION NETWORK In the following paragraphs the transfer function of every block is described, to summarize all the singularities present in the regulation loop and thus allow the user to properly define external components values. 6.1 LC filter transfer function The transfer function of LC filter is given by: Equation 1 R LOAD 1 + s ESR C A LC s = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------2 s L C ESR + R LOAD + s ESR C R LOAD + L + R LOAD where RLOAD is defined as the ratio between VOUT and IOUT. If RLOAD>>ESR, the previous expression of ALC can be simplified and becomes Equation 2 1 + s ESR C A LC s = ----------------------------------------------------------2 s LC + s ESR C + 1 The zero of this transfer function is given by: Equation 3 1 f o = --------------------------------2 ESR C 15/33 Compensating switching regulator AN2817 fo is the zero introduced by the ESR of the output capacitor and it is fundamental to increase the phase margin of the loop. The poles of the transfer function can be calculated from the following expression: 2 Equation 4 – ESR C ESR C – 4 L C f PLC1,2 = ------------------------------------------------------------------------------------------2LC In the denominator of ALC the typical second order system equation can be recognized: Equation 5 2 2 s + 2 n s + n If the damping factor is very close to zero, the roots of the equation become a double root whose value is n. Similarly, for ALC the poles can usually be defined as a double pole whose value is: Equation 6 1 f PLC = ----------------------2 L C Given for instance L = 22µH, C = 200µF, ESR=250m, the gain and phase bode diagram of LC filter are plotted in Figure 15. Figure 15. Bode diagram of LC filter 16/33 AN2817 6.2 Compensating switching regulator PWM comparator transfer function The PWM comparator compares the sawtooth signal and the Error Amplifier output signal. Its transfer function is given by the following formula: Equation 7 V CC G PWM s = -----------------V OSC where VOSC is the peak to peak voltage of the oscillator: when the switching frequency is determined by the internal oscillator VOSC = 2.3V, while if the switching frequency is forced with a SYNC signal to f=400kHz, VOSC = 1.2188V. Being the relationship between fsw and VOSC linear, VOSC for other switching frequencies can be deduced starting from these two values. Considering VCC = 14V, GPWM value is 6.08695 in free-run condition and 11.4867 at 400kHz respectively. 6.3 Error amplifier and compensation network The transfer function (equation1) for the output filter shows the well known double pole of an LC filter. It is very important to note that the ESR of capacitor is very small, so the system phase will experience a very sharp decrement at the double pole frequency while the gain will have a rather high peak. Systems that have such output filter are more difficult to compensate since the phase will need an extra boost to provide the necessary phase margin for stability. In these cases a Type-3 compensation is typically used to achieve stability. Figure 16 shows the block diagram of Error Amplifier and the Type-3 compensation network, consisting of R6, C2, R3, C3, C4 and R5, that introduce two poles, two zeros and a pole at 0Hz frequency. The transfer function of the error amplifier and its compensation network is: 1 + s R5 C4 1 + s R3 + R6 C2 A 0 s = -------------------------------------------------------------------------------------------------------------------------------------------------1 + s R5 C3 C4 s R3 C3 + C4 1 + s R6 C2 ------------------------------------------------- C3 + C4 The poles of this transfer function are: Equation 8 Equation 9 Equation 10 Equation 11 1 f P0 = --------------------------------------------------2 R3 C3 + C4 1 f P1 = -------------------------------2 R6 C2 1 f P2 = -------------------------------------------2 R5 C3 C4 ------------------------------------------- C3 + C4 17/33 Compensating switching regulator AN2817 While the zeroes are defined as: Equation 12 1 f z1 = -------------------------------2 R5 C4 Equation 13 1 f z2 = --------------------------------------------------2 R3 + R6 C2 fz1 and fz2 are usually set near the LC filter double pole frequency to increase the phase margin while fp1 and fp2 are usually set at high frequency in order to reduce the high frequency gain. Figure 16. Error amplifier and compensation network 5V VBG COMP EA Output R6 R3 C3 C2 C4 R5 R4 Following these indications and considering for example L = 22µH, C = 200µF the following set of values is determined: R6 = 470, R3 = 22k, C2 = 3.3nF, C3 = 2.7nF, C4 = 1.8nF, R5 = 75k. Bode plots of this type-3 compensation network are plotted in Figure 17. Figure 17. Bode plots of a type-3 compensation network 18/33 AN2817 6.4 Compensating switching regulator Examples of system compensation: impact of ESR Case 1 ● C = 2 x 100µF electrolytic capacitors (total ESR = 0.25 with a 2.2µF ceramic capacitor in parallel; L = 22µH ● R6 = 470, R3 = 22k, R4 = 22k/(VDCOUT-1), (VDCOUT = 1.2~8V), C2 = 3.3nF, C3 = 2.7nF, C4 = 1.8nF, R5 = 75k ● GPWM = 6.08695 (free-run) or 11.4867 (400kHz) Open-loop gain/phase Bode plots are plotted in Figure 18. Figure 18. Case 1 open-loop Bode plots The unit gain bandwidth and phase margin are: fC1 = 14.3kHz Phase margin = 71.5° (free-run) fC2 = 25.6kHz Phase margin = 70° (400kHz) 19/33 Compensating switching regulator AN2817 Case 2 ● C = 220µF electrolytic capacitor (ESR = 4) + 1 x 2.2µF ceramic capacitor; L = 22µH ● R6 = 330, R3 = 22k, R4 = 3.1k (VDCOUT = 8), C2 = 3.3nF, C3 =1 0nF, C4 = 1nF, R5 = 75k ● GPWM = 6.08695 or 11.4867 Open-loop gain/phase Bode plots are plotted in Figure 19. Figure 19. Case 2 open-loop Bode plots Under the conditions above, the unit gain bandwidth and phase margin are: 20/33 fC1 = 48.2kHz Phase margin=100° (free_run) fC2 = 90.3kHz Phase margin=74.7° (400kHz) AN2817 Compensating switching regulator Case 3 ● C = 2 x100µF tantalum capacitor (ESR = 0.1) + 1 x 2.2µF ceramic capacitor; L = 22µH ● R6 = 470, R3 = 22k, R4 = 22k/(VDCOUT-1), (VDCOUT = 1.2~8V), C2 = 3.3nF, C3 = 330µF, C4 = 1.8nF, R5 = 75k ● GPWM = 6.08695 or 11.4867 Open-loop gain/phase Bode plots are plotted in Figure 20. Figure 20. Case 3 open-loop Bode plots Under the conditions above, the unit gain bandwidth and phase margin are: fC1= 41.9kHz Phase margin = 63.8° (free-run) fC2 =70.2kHz Phase margin = 53.2° (400kHz) 21/33 22/33 0.1u 2.7nF 3.3nF 1u 0.1u 1u VLR1 VSTBY 10K VLR2 RESET 1.8nF 75k 22k/(VDCOUT-1) 22K +5V S2 VBATW 10K EN 10K SDA VBAT1 SCL SYNC VSTBY 10K +5V 47K 47K S1 MRSH L5962 UH8903 NC 18 0.1u NC 17 19 NC AGND 16 VSTBYS 15 20 NC 21 LVWIN 22 VBATW VSTBY 14 23 VLR1 VBATP 12 RSTDLY 13 24 SDA 25 VINLR HSD2 11 26 VLR2 HSD1 9 VBAT 10 27 RESET 28 EN 29 SCL VINsw 8 SUBGND 7 NC 6 30 SYNC NC 5 31 SOST PHASE 4 32 VCMP 33 VFB CBS 3 35 NC 34 CLIM TAB 1 PGND 2 36 NC 0.1uF S3 SUBGND SUBGND 1u VSTBY 30u/35V 0.1u 0.1u 4.7u 1500pF 22 22uH 200u/10V HSD2 VBAT1 PGND HSD1 2.2u VDCOUT 0.1u 40uH VBAT 7 470 Application diagram AN2817 Application diagram Figure 21. L5962 application diagram 1000 u/25V 0.1u 0.1u 470 u/25V AN2817 8 Device performance Device performance Performance mentioned in the following paragraphs have been tested in these conditions: Vcc = 14.4V, T = 25°C, switching regulator in free-run condition. 8.1 Switching regulator efficiency Figure 22. Efficiency vs. output current 23/33 Device performance 8.2 AN2817 Switching regulator transient response Figure 23. Switching regulator undershoot Vout = 8.09V (C2), ILOAD (C4) varying from 0 to 2.87A => undershoot = 460mV Figure 24. Switching regulator overshoot Vout = 8.09V (C2), ILOAD (C4) varying from 2.75A to 0A=> overshoot = 468mV 24/33 AN2817 8.3 Device performance VSTBY transient response Figure 25. VSTBY undershoot VSTBY = 3.31V (C2), ILOAD (C4) varying from 0 to 150mA => undershoot = 129mV Figure 26. VSTBY overshoot VSTBY = 3.31V (C2), ILOAD (C4) varying from150mA to 0A=> overshoot = 106mV 25/33 Device performance 8.4 AN2817 VLR1 transient response Figure 27. VLR1 undershoot VLR1 = 5.05V (C2), ILOAD (C4) varying from 0 to 357.8mA => undershoot = 68mV Figure 28. VLR1 overshoot VLR1 = 5.05V (C2), ILOAD (C4) varying from355.7mA to 0A=> overshoot = 80mV 26/33 AN2817 8.5 Device performance VLR2 transient response Figure 29. VLR2 undershoot VLR2 = 3.3V (C2), ILOAD (C4) varying from 0 to 1.07A => undershoot = 102mV Figure 30. VLR2 overshoot VLR2 = 3.3V (C2), ILOAD (C4) varying from 1.07A to 0A => undershoot = 124mV 27/33 Device utilization hints AN2817 9 Device utilization hints 9.1 Positive-output buck-boost regulator L5962 can be used to realize an Up-Down converter with a positive output voltage. In Figure 31 is shown the schematic circuit of this topology. The output voltage is given by VO = VIN · D/(1-D), where D is the duty cycle. The output current is equal to IOUT = I · (1-D). When ILOAD = 0, the input voltage VBAT can range from 3.55V to 28.5V. Figure 31. Diagram of positive buck-boost regulator 22uH 470 VDCOUT 22K 3.3nF 35 NC PGND 2 1.8nF 31 SOST NC 6 30 SYNC SUBGND 7 29 SCL RESET I2C 28 EN MRSH L5962 UH8903 HSD1 9 VBAT 10 26 VLR2 HSD2 11 22 VBATW 21 LVWIN Battery VBATP 12 RSTDLY 13 VSTBY 14 VSTBYS 15 470uF/25V 23 VLR1 40uH 1000uF/25V 24 SDA 15uF/35V 0.1u 4.7u 15uF/35V VINsw 8 27 RESET 25 VINLR 2.2u 0.1u NC 5 32 VCMP EN NMOS 22 PHASE 4 33 VFB 0.1u 500 0.1uF CBS 3 34 CLIM 2.7nF 100uF/10V NC 1 100uF/10V 75k 36 NC 1500pF 22k/(Vout-1) +5V 0.1u 0.1u 470 uF/25V AGND 16 20 NC NC 17 19 NC NC18 At a fixed output level the current capability of this topology is limited by the DC/DC converter OCP circuits: setting VDCOUT = 10/8/5/3.3/1.2V, Figure 32/33/34/35/36/ show the relationship between maximum load current (Io_MAX) and battery voltage (VBAT). Figure 32. Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 10V) 28/33 AN2817 Device utilization hints Figure 33. Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 8V) Figure 34. Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 5V) 29/33 Device utilization hints AN2817 Figure 35. Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 3.3V) Figure 36. Maximum output current vs. input voltage VBAT in buck-boost config. (VDCOUT = 1.2V) Figure 37 shows buck-boost behavior in the case Iload=500mA (C3 = VBAT, C2 = PH, C4 = Vout). VBAT varies from 5.25V to 28.3V and then from 28.3V to 5.25V: PH amplitude varies accordingly, while Vout is kept perfectly constant by the regulator. 30/33 AN2817 Device utilization hints Figure 37. L5962 behavior in buck-boost configuration (Iload = 500mA) 31/33 Revision history 10 AN2817 Revision history Table 2. 32/33 Document revision history Date Revision Changes 08-Sep-2008 1 Initial release. 18-Sep-2013 2 Updated Disclaimer. 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