PCA9540B
2-channel I2C-bus multiplexer
Rev. 6 — 5 May 2014
Product data sheet
1. General description
The PCA9540B is a 1-of-2 bidirectional translating multiplexer, controlled via the I2C-bus.
The SCL/SDA upstream pair fans out to two SCx/SDx downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time, determined by the contents of the
programmable control register.
A power-on reset function puts the registers in their default state and initializes the I2C-bus
state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD pin can be used to
limit the maximum high voltage that is passed by the PCA9540B. This allows the use of
different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
can pull the bus up to the desired voltage level for this channel. All I/O pins are 5 V
tolerant.
2. Features and benefits
1-of-2 bidirectional translating multiplexer
I2C-bus interface logic; compatible with SMBus standards
Channel selection via I2C-bus
Power-up with all multiplexer channels deselected
Low Ron switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8, XSON8
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
3. Ordering information
Table 1.
Ordering information
Type number
PCA9540BD
Topside
marking
Package
Name
Description
Version
PA9540B
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
PCA9540BDP
9540B
TSSOP8
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
PCA9540BGD
40B
XSON8
plastic extremely thin small outline package; no leads; 8 terminals; SOT996-2
body 3 2 0.5 mm
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order
quantity
Temperature range
PCA9540BD
PCA9540BD,112
SO8
Standard marking
* IC’s tube - DSC bulk pack
2000
Tamb = 40 C to +85 C
PCA9540BD,118
SO8
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9540BDP,118
TSSOP8
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
PCA9540BDP/DG,118
TSSOP8
Reel 13” Q1/T1
*Standard mark SMD
2500
Tamb = 40 C to +85 C
XSON8
Reel 7” Q3/T4
*Standard mark
3000
Tamb = 40 C to +85 C
PCA9540BDP
PCA9540BGD PCA9540BGD,125
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
4. Block diagram
PCA9540B
SD0
SD1
SC0
SC1
VSS
VDD
SCL
SDA
SWITCH CONTROL LOGIC
POWER-ON
RESET
INPUT
FILTER
I2C-BUS
CONTROL
002aae715
Fig 1.
PCA9540B
Product data sheet
Block diagram of PCA9540B
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
5. Pinning information
5.1 Pinning
SCL
1
8
SC1
SDA
2
7
SD1
VDD
3
6
VSS
VDD
3
SD0
4
5
SC0
SD0
4
PCA9540BD
SCL
1
8
SC1
SDA
2
7
SD1
PCA9540BDP
VSS
5
SC0
002aae714
002aae713
Fig 2.
6
Pin configuration for SO8
SCL
1
SDA
2
Fig 3.
Pin configuration for TSSOP8
8
SC1
7
SD1
PCA9540BGD
VDD
3
6
VSS
SD0
4
5
SC0
002aae753
Transparent top view
Fig 4.
Pin configuration for XSON8
5.2 Pin description
Table 3.
PCA9540B
Product data sheet
Pin description
Symbol
Pin
Description
SCL
1
serial clock line
SDA
2
serial data line
VDD
3
supply voltage
SD0
4
serial data 0
SC0
5
serial clock 0
VSS
6
supply ground
SD1
7
serial data 1
SC1
8
serial clock 1
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
6. Functional description
Refer to Figure 1 “Block diagram of PCA9540B”.
6.1 Device addressing
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9540B is shown in Figure 5.
slave address
1
1
1
0
0
0
fixed
Fig 5.
0
R/W
002aae716
Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master sends a
byte to the PCA9540B which is stored in the Control register. If multiple bytes are received
by the PCA9540B, it saves the last byte received. This register can be written and read via
the I2C-bus.
channel selection bits
(read/write)
7
6
5
4
3
2
1
0
X
X
X
X
X
B2
B1
B0
002aae717
enable bit
Fig 6.
Control register
6.2.1 Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the Control
register. This register is written after the PCA9540B has been addressed. The 2 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, it will become active after a STOP condition has been placed on the I2C-bus.
This ensures that all SCx/SDx lines are in a HIGH state when the channel is made active,
so that no false conditions are generated at the time of connection.
PCA9540B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
Table 4.
Control register: Write — channel selection; Read — channel status
D7
D6
D5
D4
D3
B2
B1
B0
Command
X
X
X
X
X
0
X
X
no channel selected
X
X
X
X
X
1
0
0
channel 0 enabled
X
X
X
X
X
1
0
1
channel 1 enabled
X
X
X
X
X
1
1
X
no channel selected
0
0
0
0
0
0
0
0
no channel selected;
power-up default state
6.3 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9540B in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9540B registers and I2C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.4 Voltage translation
The pass gate transistors of the PCA9540B are constructed such that the VDD voltage can
be used to limit the maximum voltage that is passed from one I2C-bus to another.
DDD
9RVZ
9
9''9
(1) maximum
(2) typical
(3) minimum
Fig 7.
Pass gate voltage versus supply voltage
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this
data sheet). In order for the PCA9540B to act as a voltage translator, the Vo(sw) voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to clamp the downstream bus voltages effectively. Looking at
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
Figure 7, we see that Vo(sw)(max) is at 2.7 V when the PCA9540B supply voltage is 3.5 V or
lower so the PCA9540B supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see Figure 14).
More Information can be found in application note AN262, “PCA954X family of I2C/SMBus
multiplexers and switches”.
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure 8).
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Fig 8.
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Bit transfer
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9).
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Fig 9.
PCA9540B
Product data sheet
Definition of START and STOP conditions
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
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Fig 10. System configuration
7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
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Fig 11. Acknowledgement on the I2C-bus
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
7.5 Bus transactions
slave address
SDA
S
1
1
1
0
0
control register
0
0
START condition
0
A
R/W
X
X
X
X
X
B2
acknowledge
from slave
B1
B0
A
P
acknowledge
from slave
STOP condition
002aae719
Fig 12. Write control register
slave address
SDA
S
1
1
1
0
0
last byte
control register
0
START condition
0
1
A
R/W
X
X
acknowledge
from slave
X
X
X
B2
B1
B0
NA
P
no acknowledge
from master
STOP condition
002aae720
Fig 13. Read control register
8. Application design-in information
VDD = 2.7 V to 5.5 V
VDD = 3.3 V
V = 2.7 V to 5.5 V
SDA
SDA
SD0
SCL
SCL
SC0
PCA9540B
channel 0
V = 2.7 V to 5.5 V
I2C-bus/SMBus master
SD1
channel 1
SC1
VSS
002aae721
Fig 14. Typical application
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to ground (VSS = 0 V).
Symbol
Parameter
VDD
VI
Min
Max
Unit
supply voltage
0.5
+7.0
V
input voltage
0.5
+7.0
V
II
input current
-
20
mA
IO
output current
-
25
mA
IDD
supply current
-
100
mA
ISS
ground supply current
-
100
mA
Ptot
total power dissipation
-
400
mW
Tstg
storage temperature
60
+150
C
Tamb
ambient temperature
Tj(max)
maximum junction
temperature
[1]
Conditions
operating
[1]
40
+85
C
-
125
C
The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.
10. Thermal characteristics
Table 6.
PCA9540B
Product data sheet
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction
to ambient
SO8 package
158
C/W
TSSOP8 package
120
C/W
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Rev. 6 — 5 May 2014
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PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
11. Static characteristics
Table 7.
Static characteristics at VDD = 2.3 V to 3.6 V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
See Table 8 for VDD = 3.6 V to 5.5 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.3
-
3.6
V
Supply
VDD
supply voltage
IDD
supply current
operating mode; VDD = 3.6 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
-
20
50
A
Istb
standby current
standby mode; VDD = 3.6 V;
no load; VI = VDD or VSS;
fSCL = 0 kHz
-
0.1
1
A
VPOR
power-on reset voltage
no load; VI = VDD or VSS
-
1.6
2.1
V
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
6
V
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
VOL = 0.6 V
6
-
-
mA
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Ci
input capacitance
VI = VSS
-
7
8
pF
ON-state resistance
VDD = 3.0 V to 3.6 V; VO = 0.4 V;
IO = 15 mA
5
11
31
VDD = 2.3 V to 2.7 V; VO = 0.4 V;
IO = 10 mA
7
16
55
Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A
-
1.9
-
V
Vi(sw) = VDD = 3.0 V to 3.6 V;
Io(sw) = 100 A
1.6
-
2.8
V
Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A
-
1.5
-
V
Vi(sw) = VDD = 2.3 V to 2.7 V;
Io(sw) = 100 A
1.1
-
2.0
V
Pass gate
Ron
Vo(sw)
switch output voltage
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Cio
input/output capacitance
VI = VSS
-
2.5
5
pF
[1]
VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
Table 8.
Static characteristics at VDD = 3.6 V to 5.5 V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
See Table 7 for VDD = 2.3 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3.6
-
5.5
V
Supply
VDD
supply voltage
IDD
supply current
operating mode; VDD = 5.5 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
-
65
100
A
Istb
standby current
standby mode; VDD = 5.5 V;
no load; VI = VDD or VSS
-
0.3
1
A
VPOR
power-on reset voltage
no load; VI = VDD or VSS
-
1.6
2.1
V
[1]
Input SCL; input/output SDA
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-
6
V
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
VOL = 0.6 V
6
-
-
mA
IIL
LOW-level input current
VI = VSS
1
-
+1
A
IIH
HIGH-level input current
VI = VDD
1
-
+1
A
Ci
input capacitance
VI = VSS
-
6
8
pF
Ron
ON-state resistance
VDD = 4.5 V to 5.5 V; VO = 0.4 V;
IO = 15 mA
4
9
24
Vo(sw)
switch output voltage
Vi(sw) = VDD = 5.0 V; Io(sw) = 100 A
-
3.6
-
V
Vi(sw) = VDD = 4.5 V to 5.5 V;
Io(sw) = 100 A
2.6
-
4.5
V
Pass gate
IL
leakage current
VI = VDD or VSS
1
-
+1
A
Cio
input/output capacitance
VI = VSS
-
2.5
5
pF
[1]
VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
12. Dynamic characteristics
Table 9.
Symbol
Dynamic characteristics
Parameter
Conditions
Standard-mode
I2C-bus
from SDA to SDx,
or SCL to SCx
Fast-mode I2C-bus
Unit
Min
Max
Min
Max
-
0.3[1]
-
0.3[1]
ns
0
100
0
400
kHz
4.7
-
1.3
-
s
4.0
-
0.6
-
s
s
tPD
propagation delay
fSCL
SCL clock frequency
tBUF
bus free time between a STOP and
START condition
tHD;STA
hold time (repeated) START
condition
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
s
[2]
tHD;DAT
data hold time
0[3]
3.45
0[3]
0.9
s
tSU;DAT
data set-up time
250
-
100
-
ns
tr
rise time of both SDA and SCL
signals
-
1000
20 + 0.1Cb[4]
300
ns
tf
fall time of both SDA and SCL
signals
-
300
20 + 0.1Cb[4]
300
ns
Cb
capacitive load for each bus line
-
400
-
400
pF
tSP
pulse width of spikes that must be
suppressed by the input filter
-
50
-
50
ns
tVD;DAT
data valid time
tVD;ACK
HIGH-to-LOW
[5]
-
1
-
1
s
LOW-to-HIGH
[5]
-
0.6
-
0.6
s
-
1
-
1
s
data valid acknowledge time
[1]
Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance.
[2]
After this period, the first clock pulse is generated.
[3]
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4]
Cb = total capacitance of one bus line in pF.
[5]
Measurements taken with 1 k pull-up resistor and 50 pF load.
PCA9540B
Product data sheet
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Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
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Fig 15. Definition of timing on the I2C-bus
PCA9540B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 27
PCA9540B
NXP Semiconductors
2-channel I2C-bus multiplexer
13. Package outline
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2-channel I2C-bus multiplexer
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PCA9540B
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2-channel I2C-bus multiplexer
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PCA9540B
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2-channel I2C-bus multiplexer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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2-channel I2C-bus multiplexer
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 11.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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15. Soldering: PCB footprints
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PCA9540B
Product data sheet
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2-channel I2C-bus multiplexer
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PCA9540B
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2-channel I2C-bus multiplexer
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16. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CDM
Charged-Device Model
ESD
ElectroStatic Discharge
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
IC
Integrated Circuit
LSB
Least Significant Bit
POR
Power-On Reset
SMBus
System Management Bus
17. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9540B v.6
20140505
Product data sheet
-
PCA9540B v.5
Modifications:
•
corrected “XSON8U” to “XSON8” throughout data sheet (correction to documentation only; no
change to device)
•
Table 1 “Ordering information”: corrected package description for XSON8 by deleting phrase
“UTLP based” (correction to documentation only; no change to device)
•
Table 2 “Ordering options”: ‘Packing method’ descriptions are updated (text only, no change to
packing method)
•
Section 6.3 “Power-on reset”, first paragraph, third sentence corrected:
from “Thereafter, VDD must be lowered below 0.2 V to reset the device.”
to “Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device.”
(correction to documentation only; no change to device)
•
Table 7 “Static characteristics at VDD = 2.3 V to 3.6 V”:
Table note [1] corrected by inserting phrase “for at least 5 s” (correction to documentation only;
no change to device)
•
Table 8 “Static characteristics at VDD = 3.6 V to 5.5 V”:
Table note [1] corrected by inserting phrase “for at least 5 s” (correction to documentation only;
no change to device)
PCA9540B v.5
20130212
Product data sheet
-
PCA9540B v.4
PCA9540B v.4
20090903
Product data sheet
-
PCA9540B v.3
PCA9540B v.3
20090528
Product data sheet
-
PCA9540B v.2
PCA9540B v.2
(9397 750 13731)
20040929
Product data sheet
-
PCA9540B v.1
PCA9540B v.1
(9397 750 12918)
20040413
Product data
-
-
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9540B
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 5 May 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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2-channel I2C-bus multiplexer
20. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.3
6.4
7
7.1
7.2
7.3
7.4
7.5
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device addressing . . . . . . . . . . . . . . . . . . . . . . 5
Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5
Control register definition . . . . . . . . . . . . . . . . . 5
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6
Voltage translation . . . . . . . . . . . . . . . . . . . . . . 6
Characteristics of the I2C-bus . . . . . . . . . . . . . 7
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
START and STOP conditions . . . . . . . . . . . . . . 7
System configuration . . . . . . . . . . . . . . . . . . . . 8
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9
Application design-in information . . . . . . . . . . 9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal characteristics . . . . . . . . . . . . . . . . . 10
Static characteristics. . . . . . . . . . . . . . . . . . . . 11
Dynamic characteristics . . . . . . . . . . . . . . . . . 13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Soldering of SMD packages . . . . . . . . . . . . . . 18
Introduction to soldering . . . . . . . . . . . . . . . . . 18
Wave and reflow soldering . . . . . . . . . . . . . . . 18
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19
Soldering: PCB footprints. . . . . . . . . . . . . . . . 21
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24
Legal information. . . . . . . . . . . . . . . . . . . . . . . 25
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Contact information. . . . . . . . . . . . . . . . . . . . . 26
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 May 2014
Document identifier: PCA9540B