74LVC273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 6 — 31 December 2012 Product data sheet 1. General description The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Inputs accept voltages up to 5.5 V CMOS low power consumption Direct interface with TTL levels Output drive capability 50 transmission lines at +85 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C and 40 C to +125 C 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC273D 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVC273DB 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 74LVC273PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVC273BQ 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm SOT764-1 4. Functional diagram CP 11 1 MR C1 R 11 3 4 7 8 13 14 17 18 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 5 Fig 1. Logic symbol 74LVC273 Product data sheet 5 7 6 8 9 13 12 14 15 17 16 18 19 D2 9 D3 12 D4 15 16 D5 19 D6 D7 2 1D 4 D1 6 MR 1 3 D0 2 mna763 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna764 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 2 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 5. Pinning information 1 terminal 1 index area MR 1 20 VCC 20 VCC MR 5.1 Pinning Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 5 Q0 2 19 Q7 D0 3 18 D7 Q1 16 Q6 273 D1 4 17 D6 Q2 6 15 Q5 Q1 5 16 Q6 D2 7 14 D5 Q2 6 D3 8 D2 7 Q3 9 15 Q5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP GND(1) 001aad093 13 D4 12 Q4 GND 10 14 D5 CP 11 273 001aad094 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration for SO20 and (T)SSOP20 Fig 4. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) CP 11 clock input (LOW-to-HIGH; edge-triggered) D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 flip-flop output GND 10 ground (0 V) VCC 20 supply voltage 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 3 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 6. Functional description Table 3. Function table[1] Operating mode Input Output MR CP Dn Qn L X X L Load ‘1’ H h H Load ‘0’ H l L Reset (clear) [1] H = HIGH voltage level L = LOW voltage level X = don’t care h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW-to-HIGH clock transition 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] Min Max Unit 0.5 +6.5 V 50 - mA 0.5 +6.5 V - 50 mA 0.5 VCC + 0.5 V IO output current - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions functional Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 4 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Min HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL Typ[1] 40 C to +125 C Max Min Unit Max VCC = 1.2 V 1.08 - - 1.08 - V VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35 VCC - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V IO = 100 A; VCC = 1.65 V to 3.6 V VCC 0.2 - - VCC 0.3 - V IO = 4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = 8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = 18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = 24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - VI = VIH or VIL VI = VIH or VIL - 0.55 - 0.8 V II input leakage VCC = 3.6 V; VI = 5.5 V or GND current 0.1 5 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; - 5 500 - 5000 A VCC = 2.7 V to 3.6 V; VI = VCC 0.6 V; IO = 0 A input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF CI [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 5 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter tpd tPHL tW propagation delay HIGH to LOW propagation delay pulse width 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max - 18 - - - ns VCC = 1.65 V to 1.95 V 2.5 9.7 19.2 2.5 22.2 ns VCC = 2.3 V to 2.7 V 1.8 4.9 9.9 1.8 11.4 ns VCC = 2.7 V 1.5 4.5 8.4 1.5 10.5 ns VCC = 3.0 V to 3.6 V 1.5 4.1 8.2 1.5 10.5 ns - 18 - - - ns VCC = 1.65 V to 1.95 V 2.4 10.2 20.4 2.4 23.5 ns VCC = 2.3 V to 2.7 V 1.7 5.2 10.5 1.7 12.1 ns VCC = 2.7 V 1.5 4.7 8.9 1.5 11.5 ns VCC = 3.0 V to 3.6 V 1.5 4.3 8.7 1.5 11.0 ns VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns VCC = 2.7 V 5.0 1.8 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns VCC = 1.65 V to 1.95 V 6.0 - - 6.0 - ns VCC = 2.3 V to 2.7 V 5.0 - - 5.0 - ns VCC = 2.7 V 5.0 1.7 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns 2.0 - - 2.0 - ns CP to Qn; see Figure 5 VCC = 1.2 V [2] MR to Qn; see Figure 6 VCC = 1.2 V clock HIGH or LOW; see Figure 5 master reset LOW; see Figure 6 trec recovery time MR to CP; see Figure 6 VCC = 1.65 V to 1.95 V tsu th set-up time hold time 74LVC273 Product data sheet VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns VCC = 2.7 V 2.0 1.0 - 2.0 - ns VCC = 3.0 V to 3.6 V 2.0 1.0 - 2.0 - ns Dn to CP; see Figure 7 VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 3.5 - - 3.5 - ns VCC = 2.7 V 3.0 1.0 - 3.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.0 - 1.0 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 2.0 0.2 - 2.0 - ns VCC = 3.0 V to 3.6 V 1.0 0.0 - 1.0 - ns Dn to CP; see Figure 7 All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 6 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter fmax maximum frequency 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max see Figure 5 VCC = 1.65 V to 1.95 V 80 - - 64 - MHz VCC = 2.3 V to 2.7 V 100 - - 80 - MHz VCC = 2.7 V 150 - - 150 - MHz 150 230 - 150 - MHz - - 1.0 - 1.5 ns - 14.0 - - - pF VCC = 2.3 V to 2.7 V - 17.7 - - - pF VCC = 3.0 V to 3.6 V - 21.0 - - - pF VCC = 3.0 V to 3.6 V [3] tsk(o) output skew time CPD power dissipation per flip-flop; VI = GND to VCC capacitance VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V [4] [1] Typical values are measured at Tamb = 25 C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volt N = number of inputs switching (CL VCC2 fo) = sum of the outputs 11. Waveforms 1/fmax VI CP input VM VM GND tW t PHL t PLH VOH VM Qn output mna765 VOL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum frequency 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 7 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger VI VM MR input GND tW trec VI CP input VM GND tPHL VOH VM Qn output VOL mna464 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Master reset (MR) pulse width, the master reset to output (Qn) propagation delays, and the master reset to clock (CP) recovery time VI VM CP input GND t su t su th th VI VM Dn input GND VOH VM Qn output VOL mna767 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Data set-up and hold times for the data input (Dn) 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 8 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Table 9. Load circuitry for switching times Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC 2 ns 30 pF 1 k open 2 VCC GND 1.65 V to 1.95 V VCC 2 ns 30 pF 1 k open 2 VCC GND 2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND 74LVC273 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 9 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT163-1 (SO20) 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 10 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT339-1 (SSOP20) 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 11 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT360-1 (TSSOP20) 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 12 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT764-1 (DHVQFN20) 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 13 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC273 v.6 20121231 Product data sheet - 74LVC273 v.5 - 74LVC273 v.4 Modifications: 74LVC273 v.5 Modifications: • General description changed (errata). 20121206 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVC273 v.4 20040312 Product specification - 74LVC273 v.3 74LVC273 v.3 20031030 Product specification - 74LVC273 v.2 74LVC273 v.2 19980520 Product specification - 74LVC273 v.1 74LVC273 v.1 19960606 Product specification - - 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 14 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC273 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 15 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC273 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 31 December 2012 © NXP B.V. 2012. All rights reserved. 16 of 17 74LVC273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 31 December 2012 Document identifier: 74LVC273