74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 2 December 2015
Product data sheet
1. General description
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP)
and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be
stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
(nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ
output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the
circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +80 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC73D
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
74HC73DB
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads; body width
5.3 mm
SOT337-1
74HC73PW
40 C to +125 C
TSSOP14 plastic thin shrink small outline package; 14 leads; body
width 4.4 mm
SOT402-1
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
4. Functional diagram
-
&3
.
-
4
4 ))
&3
4
.
4 5
5
-
&3
.
-
4
4 ))
&3
4
.
4 5
5
DDE
Fig 1.
Functional diagram
-
&3
&3
.
.
-
4
4 4 ))
.
4
5 5
Logic symbol
74HC73
Product data sheet
&
.
5
&3
4 4 5
Fig 2.
-
-
&
.
5
DDE
DDE
Fig 3.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 16
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
&
&
&
&
.
4
&
&
&
&
5
4
&
&3
DDE
&
Fig 4.
Logic diagram (one flip-flop)
5. Pinning information
5.1 Pinning
+&
&3
-
5
4
.
4
9&&
*1'
&3
.
5
4
-
4
DDE
Fig 5.
Pin configuration SO14, SSOP14 and TSSOP14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1CP, 2CP
1, 5
clock input (HIGH-to-LOW edge-triggered); also referred to as nCP
1R, 2R
2, 6
asynchronous reset input (active LOW); also referred to as nR
1K, 2K
3, 10
synchronous K input; also referred to as nK
VCC
4
positive supply voltage
GND
11
ground (0 V)
1Q, 2Q
12, 9
true output; also referred to as nQ
1Q, 2Q
13, 8
complement output; also referred to as nQ
1J, 2J
14, 7
synchronous J input; also referred to as nJ
74HC73
Product data sheet
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Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 16
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
6. Functional description
Table 3.
Function table[1]
Input
Output
Operating mode
nR
nCP
nJ
nK
nQ
nQ
L
X
X
X
L
H
H
h
h
q
q
toggle
H
l
h
L
H
load 0 (reset)
H
h
l
H
L
load 1 (set)
H
l
l
q
q
hold (no change)
[1]
asynchronous reset
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to VCC + 0.5 V
Min
Max
Unit
0.5
+7.0
V
[1]
-
20
mA
[1]
-
20
mA
IO
output current
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
SO14 package
[2]
-
500
mW
(T)SSOP14 package
[3]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 8 mW/K above 70 C.
[3]
Ptot derates linearly with 5.5 mW/K above 60 C.
74HC73
Product data sheet
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Rev. 5 — 2 December 2015
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74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
ambient temperature
t/V
input transition rise and fall rate
Min
Typ
Max
Unit
2.0
5.0
6.0
V
0
-
VCC
V
0
-
VCC
V
40
-
+125
C
VCC = 2.0 V
-
-
625
ns/V
VCC = 4.5 V
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
25 C
Conditions
40 C to +85 C
40 C to +125 C Unit
Min
Typ Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4 mA; VCC = 4.5 V
3.98 4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48 5.81
-
5.34
-
5.2
-
V
VI = VIH or VIL
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4 mA; VCC = 4.5 V
-
0.15 0.26
-
0.33
-
0.4
V
-
0.16 0.26
IO = 5.2 mA; VCC = 6.0 V
-
0.33
-
0.4
V
-
-
0.1
-
1.0
-
1.0
A
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
4.0
-
40.0
-
80.0
A
input
capacitance
-
3.5
-
-
-
-
-
pF
II
input leakage
current
ICC
CI
74HC73
Product data sheet
VI = VCC or GND;
VCC = 6.0 V
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Rev. 5 — 2 December 2015
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74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
tpd
propagation
delay
nCP to nQ; see Figure 6
Min
Max
Min
Max
[1]
VCC = 2.0 V
-
52
160
-
200
-
240
ns
VCC = 4.5 V
-
19
32
-
40
-
48
ns
VCC = 6.0 V
-
15
27
-
34
-
41
ns
VCC = 5.0 V; CL = 15 pF
-
16
-
-
-
-
-
ns
VCC = 2.0 V
-
52
160
-
200
-
240
ns
VCC = 4.5 V
-
19
32
-
40
-
48
ns
34
-
41
ns
nCP to nQ; see Figure 6
VCC = 6.0 V
-
15
27
VCC = 5.0 V; CL = 15 pF
-
16
-
-
VCC = 2.0 V
-
50
145
-
180
-
220
ns
VCC = 4.5 V
-
18
29
-
36
-
44
ns
VCC = 6.0 V
-
14
25
31
-
38
ns
-
15
-
-
-
-
ns
ns
nR to nQ, nQ; see Figure 7
VCC = 5.0 V; CL = 15 pF
tt
tW
transition time nQ, nQ; see Figure 6
pulse width
-
[2]
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
16
-
19
ns
VCC = 2.0 V
80
22
-
100
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
VCC = 2.0 V
80
22
-
100
VCC = 4.5 V
16
8
-
20
VCC = 6.0 V
14
6
-
17
VCC = 2.0 V
80
22
-
100
VCC = 4.5 V
16
8
-
20
VCC = 6.0 V
14
6
-
17
VCC = 2.0 V
80
22
-
100
VCC = 4.5 V
16
8
-
20
VCC = 6.0 V
14
6
-
17
nCP input, HIGH or LOW;
see Figure 6
ns
nR input, HIGH or LOW;
see Figure 7
trec
tsu
recovery time
set-up time
74HC73
Product data sheet
120
-
ns
-
24
-
ns
-
20
ns
nR to nCP; see Figure 7
120
-
ns
-
24
-
ns
-
20
ns
nJ, nK to nCP; see Figure 6
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
120
-
ns
-
24
-
ns
-
20
ns
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 16
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter
th
hold time
maximum
frequency
fmax
25 C
Conditions
power
dissipation
capacitance
Min
Max
Min
Max
VCC = 2.0 V
3
8
-
3
3
-
ns
VCC = 4.5 V
3
3
-
3
-
3
-
ns
VCC = 6.0 V
3
2
-
3
-
3
ns
nCP input; see Figure 6
VCC = 2.0 V
6.0
23
-
4.8
4.0
-
MHz
VCC = 4.5 V
30
70
-
24
-
20
-
MHz
VCC = 6.0 V
35
83
-
28
-
24
-
MHz
-
77
-
-
MHz
-
30
-
-
pF
[3]
per flip-flop;
VI = GND to VCC
[1]
tpd is the same as tPHL, tPLH.
[2]
tt is the same as tTHL, tTLH.
[3]
Min Typ Max
nJ, nK to nCP; see Figure 6
VCC = 5.0 V; CL = 15 pF
CPD
40 C to +85 C 40 C to +125 C Unit
-
-
-
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC73
Product data sheet
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Rev. 5 — 2 December 2015
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74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
11. Waveforms
9,
Q-Q.
LQSXW
*1'
90
WK
WVX
9,
WK
WVX
IPD[
90
Q&3LQSXW
*1'
W:
W3/+
W3+/
92+
Q4RXWSXW
90
92/
W7+/
92+
W7/+
Q4RXWSXW
90
92/
W7/+
W7+/
W3/+
W3+/
DDE
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J
and K to nCP set-up and hold times, the output transition times and the maximum clock frequency
9,
90
Q&3LQSXW
*1'
WUHF
W:
9,
90
Q5LQSXW
*1'
W3+/
92+
Q4RXWSXW
92/
92+
W3/+
Q4RXWSXW
DDE
92/
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width
and the nR to nCP removal time
74HC73
Product data sheet
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Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 16
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 8.
Measurement points
Type
Input
74HC73
Output
VI
VM
VM
VCC
0.5VCC
0.5VCC
9,
QHJDWLYH
SXOVH
W:
90
90
*1'
WI
9,
WI
SRVLWLYH
SXOVH
*1'
WU
WU
90
90
W:
9&&
*
9,
92
'87
57
&/
DDK
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Fig 8.
Table 9.
Test circuit for measuring switching times
Test data
Type
74HC73
74HC73
Product data sheet
Input
Load
VI
tr, tf
CL
VCC
6 ns
15 pF, 50 pF
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
12. Package outline
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74HC73
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 16
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
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Fig 10. Package outline SOT337-1 (SSOP14)
74HC73
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 16
74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
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Fig 11. Package outline SOT402-1 (TSSOP14)
74HC73
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC73 v.5
20151202
Product data sheet
-
74HC73 v.4
Modifications:
74HC73 v.4
Modifications:
•
Type number 74HC73N (SOT27-1) removed.
20080319
Product data sheet
-
74HC73 v.3
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Quick reference data incorporated into Section 9 and 10.
Section 8 “Recommended operating conditions” tr, tf converted to t/V.
74HC73 v.3
20041112
Product data sheet
-
74HC_HCT73_CNV v.2
74HC_HCT73_CNV v.2
December 1990
Product specification
-
-
74HC73
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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74HC73
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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All information provided in this document is subject to legal disclaimers.
Rev. 5 — 2 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Contact information. . . . . . . . . . . . . . . . . . . . . 15
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 December 2015
Document identifier: 74HC73