PCF8537 Industrial LCD driver for multiplex rates up to 1:8 Rev. 1 — 31 May 2012 Product data sheet 1. General description The PCF8537 is a fully featured Liquid Crystal Display (LCD)1 driver, specifically designed for high-contrast Vertical Alignment (VA) LCD with multiplex rates up to 1:8. It generates the drive signals for any static or multiplexed LCD containing up to eight backplanes, 46 segments, and up to 352 elements. The PCF8537 features an internal charge pump with internal capacitors for on-chip generation of the LCD driving voltage. To ensure an optimal and stable contrast over the full temperature range, the PCF8537 offers a programmable temperature compensation of the LCD supply voltage. The PCF8537 can be easily connected to a microcontroller by either the two-line I2C-bus (PCF8537AH) or a three-line bidirectional SPI-bus (PCF8537BH). 2. Features and benefits Low-power single-chip LCD controller and driver 352 elements allowing to drive: up to 44 7-segment alphanumeric characters up to 22 14-segment alphanumeric characters Selectable backplane drive configuration: static, 2, 4, 6, or 8 backplane multiplexing Software programmable internal charge pump for on-chip LCD voltage generation up to 9 V with internal capacitors 400 kHz I2C-bus interface (PCF8537AH) 5 MHz SPI-bus interface (PCF8537BH) Programmable temperature compensation of VLCD in four regions Selectable display bias configuration Wide range for digital power supply: from 1.8 V to 5.5 V Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high threshold twisted nematic LCDs Display memory bank switching in static, duplex, and quadruplex drive modes 352-bit RAM for display data storage Programmable frame frequency in the range of 60 Hz to 300 Hz in steps of 10 Hz; factory calibrated Integrated temperature sensor with temperature readout On chip calibration of internal oscillator frequency and VLCD Manufactured in silicon gate CMOS process 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17. PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 3. Applications White goods Handheld electronics Battery operated equipment Machine control systems Measuring equipment Information boards Panels Consumer Industrial Medical and health care 4. Ordering information Table 1. Ordering information Type number Interface type Package Name Description Version PCF8537AH/1 I2C-bus TQFP64 plastic thin quad flat package; 64 leads; body 10 10 1.0 mm SOT357-1 PCF8537BH/1 SPI-bus TQFP64 plastic thin quad flat package; 64 leads; body 10 10 1.0 mm SOT357-1 5. Marking Table 2. PCF8537 Product data sheet Marking codes Type number Marking code PCF8537AH/1 PCF8537AH PCF8537BH/1 PCF8537BH All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 2 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 6. Block diagram VLCD BP0 to BP5 VDD2 S44/BP7 S45/BP6 BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR CHARGE PUMP (VOLTAGE MULTIPLIER) S0 to S43 DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT LCD BIAS GENERATOR VSS DISPLAY RAM TEMPERATURE SENSOR CLK CLOCK SELECT AND TIMING PCF8537AH OSCILLATOR POWER-ON RESET RESET SCL COMMAND DECODER WRITE DATA CONTROL DATA POINTER, AUTO INCREMENT I2C-BUS CONTROLLER SDA 013aaa671 A0 Fig 1. VSS VDD1 T1 T2 T3 Block diagram of PCF8537AH PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 3 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 VLCD BP0 to BP5 VDD2 S44/BP7 S45/BP6 BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR CHARGE PUMP (VOLTAGE MULTIPLIER) S0 to S43 DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT LCD BIAS GENERATOR VSS DISPLAY RAM TEMPERATURE SENSOR CLK CLOCK SELECT AND TIMING PCF8537BH OSCILLATOR POWER-ON RESET RESET SCL COMMAND DECODER WRITE DATA CONTROL DATA POINTER, AUTO INCREMENT SPI-BUS CONTROLLER SDIO 013aaa672 CE Fig 2. VSS VDD1 T1 T2 T3 Block diagram of PCF8537BH PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 4 of 82 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCF8537 49 BP4 50 BP5 51 S45/BP6 52 S44/BP7 53 S43 54 S42 55 S41 56 S40 57 S39 58 S38 59 S37 60 S36 61 S35 62 S34 63 S33 64 S32 49 BP4 50 BP5 51 S45/BP6 52 S44/BP7 53 S43 54 S42 55 S41 56 S40 57 S39 58 S38 59 S37 60 S36 61 S35 62 S34 63 S33 64 S32 7.1 Pinning 1 48 BP3 S31 1 48 BP3 S30 2 47 BP2 S30 2 47 BP2 S29 3 46 BP1 S29 3 46 BP1 S28 4 45 BP0 S28 4 45 BP0 S27 5 44 VLCD S27 5 44 VLCD S26 6 43 VDD2 S26 6 43 VDD2 S25 7 42 VDD1 S25 7 42 VDD1 S24 8 41 VSS S24 8 S23 9 40 T3 S23 9 S22 10 39 CLK S22 10 39 CLK S21 11 38 T2 S21 11 38 T2 S20 12 37 T1 S20 12 37 T1 S19 13 36 A0 S19 13 36 SDIO S18 14 35 SCL S18 14 35 SCL S17 15 34 SDA S17 15 34 CE S16 16 33 RESET S16 16 33 RESET Top view. For mechanical details, see Figure 62. Fig 3. Pin configuration for TQFP64 (PCF8537AH) Top view. For mechanical details, see Figure 62. Fig 4. Pin configuration for TQFP64 (PCF8537BH) S0 32 S1 31 S2 30 S3 29 S4 28 40 T3 S5 27 S6 26 S7 25 S8 24 S9 23 S10 22 S11 21 S12 20 S13 19 S14 18 013aaa673 41 VSS PCF8537BH S15 17 S0 32 S1 31 S2 30 S3 29 S4 28 S5 27 S6 26 S7 25 S8 24 S9 23 S10 22 S11 21 S12 20 S13 19 S15 17 PCF8537AH 013aaa674 PCF8537 5 of 82 © NXP B.V. 2012. All rights reserved. Industrial LCD driver for multiplex rates up to 1:8 Rev. 1 — 31 May 2012 All information provided in this document is subject to legal disclaimers. S31 S14 18 Product data sheet 7. Pinning information PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 7.2 Pin description Table 3. Pin description of PCF8537AH and PCF8537BH Pin Symbol Type Description S31 to S0 output LCD segments RESET input active low reset input PCF8537AH 1 to 32 33 34 SDA 35 SCL PCF8537BH input/output I2C-bus serial data CE SCL 36 A0 SDIO 37, 38, 40 I2C-bus serial clock input SPI-bus serial clock input I2C-bus slave address selection input/output SPI-bus serial data input test pins; must be tied to VSS in applications CLK input/output internal oscillator output, external oscillator input 41 VSS supply ground supply 42 VDD1 supply supply voltage 1 43 VDD2 supply supply voltage 2 44 VLCD[1] supply LCD supply[2] BP0 to BP5 output LCD backplanes 51 S45/BP6 output LCD segments for 1:6 multiplex drive mode; 52 S44/BP7 output LCD backplanes for 1:8 multiplex drive mode S43 to S32 output LCD segments 53 to 64 Product data sheet SPI-bus chip enable - active LOW input 39 45 to 50 PCF8537 T1 to T3 input [1] VLCD must be equal to or greater than VDD2. [2] When the internal VLCD generation is used, this pin drives the VLCD voltage. In this case pin VLCD is an output. When the external supply is requested, then pin VLCD is an input and VLCD can be supplied on it. In this case, the internal charge pump must be disabled (see Table 8). All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 6 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8. Functional description The PCF8537 is a versatile peripheral device designed to interface any microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 352 elements. 8.1 Commands of PCF8537 The commands to control the PCF8537 are defined in Table 4. Any other combinations of operation code bits that are not mentioned in this document can lead to undesired operation modes of PCF8537. Table 4. Commands of PCF8537 The bit labeled with - is not implemented. Command name RS[1] Bits 6 5 4 3 2 1 0 0 0 0 1 1 1 0 1 0 Section 8.1.1 OTP-refresh 0 1 1 0 1 0 0 0 0 Section 8.1.2 Oscillator-ctrl 0 1 1 0 0 1 1 COE OSC Section 8.1.3 Charge-pump-ctrl 0 1 1 0 0 0 0 CPE CPC Section 8.1.4 TCE TME Section 8.1.5 Temp-msr-ctrl 0 1 1 0 0 1 0 Temp-comp 0 0 0 0 1 1 SLA[2:0] 0 0 0 1 0 0 SLB[2:0] 0 0 0 1 0 1 SLC[2:0] SLD[2:0] 0 0 0 1 1 0 0 0 1 0 0 VPR[7:4] 0 0 1 0 1 VPR[3:0] Display-enable 0 0 0 1 1 1 0 Set-MUX-mode 0 0 0 0 0 0 M[2:0] Set-bias-mode 0 1 1 0 0 0 1 Load-data-pointer 0 1 0 P[5:0] Frame-frequency 0 0 1 1 0 0 Section 8.1.6 Section 8.1.7 0 E Section 8.1.8 Section 8.1.9 B[1:0] Section 8.1.10 Section 8.1.11 F[4:0] 0 Section 8.1.12 1 0 IBS Bank-select 0 0 Write-RAM-data 1 B[7:0] Section 8.1.14 Temp-read - TD[7:0] Section 8.1.15 Invmode_ctrl 0 1 1 0 1 0 1 LF 0 Section 8.1.16 Temp-filter 0 1 1 0 1 0 0 1 TFE Section 8.1.17 [1] Product data sheet 7 Initialize Set-VPR PCF8537 Reference OBS Section 8.1.13 For further information about the register selection bit, see Table 30 on page 52. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 7 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.1 Command: Initialize This command generates a chip-wide reset which resets all command values to their default values. After this command is sent, it is possible to send additional commands without the need to re-initialize the interface. The reset takes 100 ns to complete. Table 5. Initialize - initialize command bit description For further information, see Section 8.2 on page 17. Bit Symbol Binary value Description 7 to 0 - 00111010 fixed value 8.1.2 Command: OTP-refresh During production and testing of the device, each IC is calibrated to achieve the specified accuracy of VLCD, the frame frequency, and the temperature measurement. This calibration is performed on EPROM cells called One Time Programmable (OTP) cells. The device reads these cells every time at power-on, after a reset, and every time when the initialize command or the OTP-refresh command is sent. Remark: It is recommended not to enter power-down mode during the OTP refresh cycle. Table 6. OTP-refresh - OTP-refresh command bit description Bit Symbol Binary value Description 7 to 0 - 11010000 fixed value 8.1.3 Command: Oscillator-ctrl The Oscillator-ctrl command switches between internal and external oscillator and enables or disables the pin CLK. Table 7. Oscillator-ctrl - oscillator control command bit description For further information, see Section 8.1.3.1. Bit Symbol Binary value Description 7 to 2 - 110011 fixed value 1 COE 0 [1] 8.1.3.1 control pin CLK 0[1] clock signal not available on pin CLK; pin CLK is in 3-state and may be left floating 1 clock signal available on pin CLK OSC oscillator source 0[1] internal oscillator used 1 external oscillator used; pin CLK becomes an input Default value. Oscillator The internal logic and LCD drive signals of the PCF8537 are timed either by the built-in oscillator or from an external clock. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 8 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.3.2 Internal oscillator When the internal oscillator is used, it is possible to make the clock signal available on pin CLK by using the Oscillator-ctrl command (see Table 7). If this is not intended, the pin CLK should be left open. At power-on the signal at pin CLK is disabled and pin CLK is in 3-state. If the internal charge pump is enabled, then the internal oscillator starts and is used to run the charge pump. An external oscillator can still be applied for driving the display waveforms. The duty cycle of the output clock provided on the CLK pin is not always 50 : 50. Table 17 on page 13 shows the expected duty cycle for each of the chosen frame frequencies. 8.1.3.3 External clock In applications where an external clock must be applied to the PCF8537, bit OSC (see Table 7) must be set logic 1. In this case, pin CLK becomes an input. The CLK signal is a signal that is fed into the VDD1 domain. Therefore it must have an amplitude equal to the VDD1 voltage supplied to the chip and be referenced to VSS. The clock frequency (fclk) determines the LCD frame frequency. Remark: If an external clock is used then this clock signal must always be supplied to the device. Removing the clock can freeze the LCD in a DC state. Removal of the clock is possible when following the correct procedures (see Figure 11 on page 21 and Figure 12 on page 22). 8.1.4 Command: Charge-pump-ctrl The Charge-pump-ctrl command enables or disables the internal VLCD generation and controls the charge pump voltage multiplier setting. Table 8. Charge-pump-ctrl - charge pump control command bit description For further information, see Table 11 on page 11 and Section 8.4.3 on page 26. Bit Symbol Binary value Description 7 to 2 - 110000 fixed value 1 CPE 0 [1] PCF8537 Product data sheet charge pump switch 0[1] charge pump disabled; no internal VLCD generation; external supply of VLCD 1 charge pump enabled CPC charge pump voltage multiplier setting 0[1] VLCD = 2 VDD2 1 VLCD = 3 VDD2 Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 9 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.5 Command: Temp-msr-ctrl The Temp-msr-ctrl command enables or disables the temperature measurement block and the temperature compensation of VLCD. Table 9. Temp-msr-ctrl - temperature measurement control command bit description For further information, see Section 8.4.4 on page 28. Bit Symbol Binary value Description 7 to 2 - 110010 fixed value 1 TCE 0 temperature compensation switch 0 no temperature compensation of VLCD possible 1[1] temperature compensation of VLCD possible TME temperature measurement switch 0 temperature measurement disabled: no temperature readout possible 1[1] temperature measurement enabled: temperature readout possible [1] Default value. 8.1.6 Command: Temp-comp The Temp-comp command allows setting the temperature compensation coefficients for each of the temperature regions SFA to SFD. For further information, see Section 8.4.4.2. Table 10. Temp-comp - temperature compensation coefficients command For further information, see Section 8.4.4 on page 28. Bit Symbol Binary value Description - 00011 fixed value SLA[2:0] 000[1] temperature compensation coefficient SLA, see Table 26 on page 30 - 00100 fixed value SLB[2:0] 000[1] temperature compensation coefficient SLB, see Table 26 on page 30 - 00101 fixed value SLC[2:0] 000[1] temperature compensation coefficient SLC, see Table 26 on page 30 - 00110 fixed value SLD[2:0] 000[1] temperature compensation coefficient SLD, see Table 26 on page 30 SLA 7 to 3 2 to 0 to 111 SLB 7 to 3 2 to 0 to 111 SLC 7 to 3 2 to 0 to 111 SLD 7 to 3 2 to 0 [1] PCF8537 Product data sheet to 111 Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 10 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.7 Command: Set-VPR With these two instructions, it is possible to set the target VLCD voltage for the internal charge pump. Table 11. Set-VPR - set VPR command bit description For further information, see Section 8.4.2 on page 25. Bit Symbol Binary value Description - 0100 fixed value VPR[7:4] 0000[1] Set-VPR MSB 7 to 4 3 to 0 to the four most significant bits of VPR[7:0] 1111[2] Set-VPR LSB 7 to 4 3 to 0 - 0101 VPR[3:0] 0000[1] fixed value to the four least significant bits of VPR[7:0] 1111[2] [1] [2] Default value. VPR[7:0] = 0h results in Vprog(LCD) = 3 V; VPR[7:0] = C8h results in Vprog(LCD) = 9 V. 8.1.8 Command: Display-enable This command allows switching the display on and off. The possibility to disable and enable the display allows implementation of blinking the entire display under external control. Table 12. Display-enable - display enable command bit description Bit Symbol Binary value Description 7 to 1 - 0011100 fixed value E 0[1] display disabled 0 backplane and segment outputs are internally connected to VSS 1 [1] PCF8537 Product data sheet display enabled Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 11 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.9 Command: Set-MUX-mode The multiplex drive mode is configured with the bits described in Table 13. Table 13. Set-MUX-mode - set multiplex drive mode command bit description For further information, see Section 8.4.5 on page 31. Bit Symbol Binary value Description 7 to 3 - 00000 fixed value M[2:0] 000[1] 1:8 multiplex drive mode 2 to 0 011 101 111 110 8 backplanes and 44 segments 1:6 multiplex drive mode 6 backplanes and 46 segments 100 1:4 multiplex drive mode 4 backplanes and 44 segments 010 1:2 multiplex drive mode 001 static drive mode 2 backplanes and 44 segments 1 backplane and 44 segments [1] Default value. 8.1.10 Command: Set-bias-mode The Set-bias-mode command allows setting the bias level. Table 14. Set-bias-mode - set bias mode command bit description For further information, see Section 8.4.5 on page 31. Bit Symbol Binary value Description 7 to 2 - 110001 fixed value 1 to 0 B[1:0] LCD bias configuration[1] 00[2] 01 1⁄ 4 bias 11 1⁄ 3 bias 10 1⁄ 2 bias [1] Not applicable for static drive mode. [2] Default value. 8.1.11 Command: Load-data-pointer The Load-data-pointer command defines the display RAM address where the following display data will be sent to. Table 15. Load-data-pointer - load data pointer command bit description For further information, see Section 8.8 on page 44. Bit PCF8537 Product data sheet Symbol Binary value Description 7 to 6 - 10 fixed value 5 to 0 P[5:0] 000000 to 101101 RAM address 6-bit binary value of 0 to 45 All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 12 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.12 Command: Frame-frequency With the Frame-frequency command, the frame frequency and the output clock frequency can be configured. Table 16. Bit Symbol Binary value Description 7 to 5 - 011 fixed value 4 to 0 F[4:0] see Table 17 frame frequency values, see Table 17 Table 17. PCF8537 Product data sheet Frame frequency - frame frequency and output clock frequency command bit description Frame frequency values F[4:0] Nominal frame frequency ffr (Hz)[1] Resultant output clock frequency, fclk(o) (Hz) Duty cycle (%)[2] 00000 60 2880 20 : 80 00001 70 3360 7 : 93 00010 80 3840 47 : 53 00011 91 4368 40 : 60 00100 100 4800 33 : 67 00101 109 5232 27 : 73 00110 120 5760 20 : 80 00111 129.7 6226 13 : 87 01000 141.2 6778 5 : 95 01001 150 7200 50 : 50 01010 160 7680 47 : 53 01011 171.4 8227 43 : 57 01100 177.8 8534 41 : 59 01101 192 9216 36 : 64 01110[3] 200 9600 33 : 67 01111 208.7 10018 30 : 70 10000 218.2 10474 27 : 73 10001 228.6 10973 23 : 77 10010 240 11520 20 : 80 10011 252.6 12125 16 : 84 10100, 10101 266.7 12802 10 : 90 10110, 10111 282.4 13555 5 : 95 11000 to 11111 300 14400 50 : 50 [1] Nominal frame frequency calculated for the default clock frequency of 9600 Hz. [2] Duty cycle definition: % HIGH-level time : % LOW-level time. [3] Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 13 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.12.1 Timing and frame frequency The timing of the PCF8537 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame frequency. The frame frequency is a fixed division of the internal clock or of the frequency applied to pin CLK when an external clock is used. When the internal clock is used, the clock frequency can be programmed by software such that the nominal frame frequency can be chosen in steps of 10 Hz in the range of 60 Hz to 300 Hz (see Table 17). Furthermore the nominal frame frequency is factory-calibrated with an accuracy of ±15 %. When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock may change when choosing different values for the frame frequency prescaler. Table 17 shows the different output duty ratios for each frame frequency prescaler setting. 8.1.13 Command: Bank-select For the multiplex drive modes 1:4, 1:2, and the static drive mode, it is possible to write data to one area of the RAM while displaying from another. These areas are named RAM banks. There are two banks, 0 and 1. Figure 39 on page 50 and Figure 40 on page 50 show the concept. The Bank-select command controls where data is written to and where it is displayed from. Table 18. Bank-select - bank select command bit description For further information, see Section 8.9 on page 50. Bit Symbol Binary value Description 7 to 2 - 000010 fixed value 1 IBS selects RAM bank to write to 0[1] 1 0 [1] OBS Bank 0 Bank 1 selects RAM bank to read from to the LCD 0[1] Bank 0 1 Bank 1 Default value. 8.1.14 Command: Write-RAM-data By setting the RS bit of the control byte to logic 1, all data transferred is interpreted as RAM data and placed in the RAM in accordance with the current setting of the RAM address pointer (see Section 8.1.11 on page 12). Definition of the RS can be found in Table 30 on page 52. Remark: After Power-On Reset (POR) the RAM content is random and should be brought to a defined status by clearing it (setting it to logic 0). Table 19. Write-RAM-data - write RAM data command bit description For further information, see Section 8.8 on page 44. PCF8537 Product data sheet Bit Symbol Binary value Description 7 to 0 B[7:0] 00000000 to 11111111 writing data byte-wise to the RAM All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 14 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.15 Command: Temp-read The Temp-read command allows reading out the temperature values measured by the internal temperature sensor. Table 20. Temp-read - temperature readout command bit description For further information, see Section 8.4.4 on page 28. Bit Symbol Binary value Description 7 to 0 TD[7:0] 00000000 to 11111111 digital temperature values[1] [1] For this command, bit R/W of the I2C-bus slave address byte has to be set logic 1 (see Table 31). 8.1.16 Command: Invmode_ctrl The Invmode_ctrl command allows changing the drive scheme inversion mode. The waveforms used to drive LCD displays inherently produce a DC voltage across the display cell. The PCF8537 compensates for the DC voltage by inverting the waveforms on alternate frames or alternate lines. The choice of compensation method is determined with the LF bit. Table 21. Invmode_ctrl - drive scheme inversion command bit description For further information, see Section 8.4.6 on page 34. Bit Symbol Binary value Description 7 to 2 - 110101 fixed value 1 LF 0 [1] - set inversion mode 0[1] driving scheme A: line inversion mode 1 driving scheme B: frame inversion mode 0 fixed value Default value. In frame inversion mode, the DC value is compensated across two frames and not within one frame. Changing the inversion mode to frame inversion reduces the power consumption, therefore it is useful when power consumption is a key point in the application. Frame inversion may not be suitable for all applications. The RMS voltage across a segment is better defined, however since the switching frequency is reduced there is possibility for flicker to occur. Figure 24 on page 34 to Figure 30 on page 40 are showing the waveforms in line inversion mode. Figure 31 on page 41 shows an example of frame inversion. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 15 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.1.17 Command: Temp-filter Table 22. Temp-filter - digital temperature filter command bit description For further information, see Section 8.4.4 on page 28. Bit Symbol Binary value Description 7 to 1 - 1101001 fixed value 0 TFE [1] PCF8537 Product data sheet digital temperature filter switch 0[1] digital temperature filter disabled; the unfiltered digital value of TD[7:0] is immediately available for the readout and VLCD compensation, see Section 8.4.4.1 1 digital temperature filter enabled Default value. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 16 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.2 Start-up and shut-down 8.2.1 Power-On Reset (POR) At power-on, the PCF8537 resets to starting conditions as follows: 1. All backplane and segment outputs are set to VSS. 2. Selected drive mode is: 1:8 with 1⁄4 bias. 3. Input and output bank selectors are reset. 4. The I2C-bus and SPI-bus interface are initialized. 5. The data pointer is cleared (set logic 0). 6. The internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in 3-state. 7. Temperature measurement is enabled. 8. Temperature filter is disabled. 9. The internal VLCD voltage generation is disabled. The charge pump is switched off. 10. The VLCD temperature compensation is enabled. 11. The display is disabled. The reset state is as shown in Table 23. Table 23. Reset state Reset state of configuration bits shown in the command table format for clarity. The bit labeled with - has an undefined reset state. Command name Bits 7 6 5 4 3 2 1 0 Oscillator-ctrl 1 1 0 0 1 1 COE = 0 OSC = 0 Charge-pump-ctrl 1 1 0 0 0 0 CPE = 0 CPC = 0 Temp-msr-ctrl 1 1 0 0 1 0 TCE = 1 TME = 1 Temp-comp 0 0 0 1 1 SLA[2:0] = 000 0 0 1 0 0 SLB[2:0] = 000 0 0 1 0 1 SLC[2:0] = 000 0 0 1 1 0 SLD[2:0] = 000 0 1 0 0 VPR[7:4] = 0000 0 1 0 1 VPR[3:0] = 0000 Set-VPR Display-enable 0 0 1 1 1 0 Set-MUX-mode 0 0 0 0 0 M[2:0] = 000 0 E=0 Set-bias-mode 1 1 0 0 0 1 B[1:0] = 00 Load-data-pointer 1 0 P[5:0] is undefined Frame-frequency 0 1 1 F[4:0] = 01110 Bank-select 0 0 0 0 1 0 IBS = 0 OBS = 0 Invmode_ctrl 1 1 0 1 0 1 LF = 0 - Temp-filter 1 1 0 1 0 0 1 TFE = 0 Remark: Do not transfer data on the I2C-bus or SPI-bus for at least 1 ms after a power-on reset to allow the reset action to complete. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 17 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 The first command sent to the device after the power-on event must be the Initialize command (see Section 8.1.1). After POR and before enabling the display, the RAM content should be brought to a defined status • by clearing it (setting it all to logic 0) or • by writing meaningful content (for example, a graphic) otherwise unwanted display artifacts may appear on the display. 8.2.2 RESET pin function The RESET pin of the PCF8537 resets all the registers to their default state. The reset state is given in Table 23. The RAM contents remain unchanged. After the reset signal is removed, the PCF8537 will behave in the same manner as after POR. See Section 8.2.1 for details. 8.2.3 Recommended start-up sequences This chapter describes how to proceed with the initialization of the chip in different application modes. START Power-on VDD1 and VDD2 at the same time Set VPR register to desired VLCD value Set multiplication factor for charge pump and enable it Wait minimum 1 ms Initialize command Initiate an OTP-refresh Wait till VLCD reaches programmed value(1) Write RAM content to be displayed and enable the display STOP 013aaa632 (1) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms to 15 ms is expected. Fig 5. PCF8537 Product data sheet Recommended start-up sequence when using the internal charge pump and the internal clock signal All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 18 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 If the display is enabled too soon after the charge pump is enabled, then the VLCD voltage may not have yet stabilized leading to an uneven display effect. START Initiate an OTP-refresh Power-on VDD1, VDD2 and VLCD at the same time Write RAM content to be displayed and enable the display Wait minimum 1 ms STOP Initialize command 013aaa633 Fig 6. Recommended start-up sequence when using an external supplied VLCD and the internal clock signal START Power-on VDD1 and VDD2 at the same time Apply external clock signal to pin CLK; set OSC bit logic 1(1) Wait till VLCD reaches programmed value(1) (2) Wait minimum 1 ms Set VPR register to desired VLCD value Initialize command Initiate an OTP-refresh Set multiplication factor for charge pump and enable it Write RAM content to be displayed and enable the display STOP 013aaa634 (1) The external clock signal can be applied after the generation of the VLCD voltage as well. (2) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms to 15 ms is expected. Fig 7. PCF8537 Product data sheet Recommended start-up sequence when using the internal charge pump and an external clock signal All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 19 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 START Power-on VDD1, VDD2 and VLCD at the same time Apply external clock signal to pin CLK; set OSC bit logic 1 Wait minimum 1 ms Write RAM content to be displayed and enable the display Initialize command STOP Initiate an OTP-refresh Fig 8. 013aaa635 Recommended start-up sequence when using an external supplied VLCD and an external clock signal 8.2.4 Recommended sequences to enter power-down mode With the following sequences, the PCF8537 can be set to a state of minimum power consumption, called power-down mode. START Disable display by setting bit E logic 0 Stop generation of VLCD by setting bit CPE logic 0 Disable temperature measurement by setting bit TME logic 0 STOP 013aaa636 Fig 9. PCF8537 Product data sheet Recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 20 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 START Disable display by setting bit E logic 0 Disable temperature measurement by setting bit TME logic 0 STOP 013aaa637 Fig 10. Recommended power-down sequence when using an external supplied VLCD and the internal clock signal START Disable display by setting bit E logic 0 Stop generation of VLCD by setting bit CPE logic 0 Disable temperature measurement by setting bit TME logic 0 Bring pin CLK to 3-state by setting bit OSC and bit COE logic 0 External clock may be switched off STOP 013aaa638 Fig 11. Recommended power-down sequence when using the internal charge pump and an external clock signal PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 21 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 START Disable display by setting bit E logic 0 Disable temperature measurement by setting bit TME logic 0 Bring pin CLK to 3-state by setting bit OSC and bit COE logic 0 External clock may be switched off STOP 013aaa639 Fig 12. Recommended power-down sequence for minimum power-down current when using an external supplied VLCD and an external clock signal Remark: It is necessary to run the power-down sequence before removing the supplies. Depending on the application, care must be taken that no other signals are present at the chip input or output pins when removing the supplies (see Section 10). Otherwise this may cause unwanted display artifacts. In the case of uncontrolled removal of supply voltages the PCF8537 will not be damaged. Remark: Static voltages across the liquid crystal display can build up when the external LCD supply voltage (VLCD) is on while the IC supply voltage (VDD1 or VDD2) is off, or the other way around. This may cause unwanted display artifacts. To avoid such artifacts, VLCD, VDD1, and VDD2 must be applied or removed together. Remark: A clock signal must always be supplied to the device when the display is active. Removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. It is recommended to first disable the display and afterwards to remove the clock signal. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 22 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.3 Possible display configurations The PCF8537 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 13). It can directly drive any static or multiplexed LCD containing up to eight backplanes with 44 segments. The display configurations possible with the PCF8537 depend on the number of active backplane outputs required. A selection of possible display configurations is given in Table 24. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Fig 13. Example of displays suitable for PCF8537 Table 24. Selection of display configurations Number of Digits/Characters Backplanes Segments Icons 7 segment[1] 14 segment[2] Dot matrix/ Elements 8 44 352 44 22 352 dots (8 44) 6 46 276 34 17 276 dots (6 46) 4 44 176 22 11 176 dots (4 44) 2 44 88 11 5 88 dots (2 44) 1 44 44 5 2 44 dots (1 44) [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. All of the display configurations in Table 24 can be implemented in the typical systems shown in Figure 14 (internal VLCD) and in Figure 15 (external VLCD). PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 23 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 VDD2 VDD1 R= tr 2Cb SDA HOST PROCESSOR/ MICROCONTROLLER VDD1 VLCD 44 segment drives SCL RESET VDD2 LCD PANEL (up to 352 elements) PCF8537AH 8 backplanes CLK A0 T1 T2 T3 VSS n.c. VSS 013aaa675 VDD1 from 1.8 V to 5.5 V and VDD2 from 2.5 V to 5.5 V. Fig 14. Typical I2C system configuration when using the internal VLCD generation VLCD VDD1 SDIO HOST PROCESSOR/ MICROCONTROLLER VDD1 VLCD 44 segment drives SCL LCD PANEL (up to 352 elements) PCF8537BH CE RESET VDD2 8 backplanes CLK T1 T2 T3 VSS n.c. VSS 013aaa676 VDD1 from 1.8 V to 5.5 V, VDD2 from 2.5 V to 5.5 V and VLCD from 2.5 V to 9.0 V. Fig 15. Typical SPI system configuration when using an external VLCD The host microcontroller maintains the two-line I2C-bus communication channel with the PCF8537AH or the three-line SPI-bus with the PCF8537BH. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD1, VDD2, VSS, VLCD), the external capacitors, and the LCD panel selected for the application. The recommended values for external capacitors on VDD1, VDD2, and VLCD are of nominal 100 nF value. When using bigger capacitors, especially on the VLCD, the generated ripple will be consequently smaller. However it will take longer for the internal charge pump to first reach the target VLCD voltage. If VDD1 and VDD2 are connected externally, the capacitors on VDD1 and VDD2 can be replaced by a single capacitor with a nominal value of 220 nF. Remark: In case of insufficient decoupling, ripple on VDD1 and VDD2 will create additional VLCD ripple. The ripple on the VLCD can be reduced by making the VSS connection as low-ohmic as possible. Excessive ripple on VLCD may cause flicker on the display. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 24 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4 LCD supply voltage 8.4.1 External VLCD supply VLCD can be directly supplied to the VLCD pin. In this case, the internal charge pump must not be enabled otherwise a high current may occur on pin VDD2 and pin VLCD. When VLCD is supplied externally, no internal temperature compensation occurs on this voltage even if bit TCE is set logic 1 (see Section 8.4.4.2). The VLCD voltage which is supplied externally will be available at the segments and backplanes of the device through the chosen bias system. Also programming VPR[7:0] will have no effect on the VLCD which is externally supplied. 8.4.2 Internal VLCD generation VLCD can be generated and controlled on the chip by using software commands. When the internal charge pump is used, the programmed VLCD is available on pin VLCD. The charge pump generates a VLCD of up to 3 VDD2. The charge pump can be enabled or disabled with the CPE bit (see Table 8 on page 9). With bit CPC, the charge pump multiplier setting can be configured. The final value of VLCD is a combination of the programmed Vprog(LCD) value and the output of the temperature compensation block, Voffset(LCD). (1) V LCD = V prog LCD + V offset LCD The system is shown in Figure 16. SLA SLB SLC SLD Voffset(LCD) 0 OFFSET TEMPERATURE READOUT 8 8 TD[7:0] VT[7:0] -40 0 +20 +50 +80 TEMPERATURE 0.03 VPR[7:0] 8 0.03 3 8 Vprog(LCD) VLCD 013aaa640 VPR[7:0] is the binary value of the programmed voltage. VT[7:0] is the binary value of the temperature compensated voltage. Its values come from the temperature compensation block and is a two’s complement which has the value 0h at 20 C. V prog LCD = VPR 7:0 0.03 + 3 . The equations for Voffset(LCD), see Table 27 on page 31. Fig 16. VLCD generation including temperature compensation PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 25 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Figure 17 illustrates how VLCD changes with the programmed value of VPR[7:0]. 013aaa661 V LCD (2) 9V 0.03 V (1) VDD2 3V 00 01 02 03 04 05 06 ... ... C7 C8 C9 CA ... FC FD FE FF VPR[7:0] (1) If VDD2 > 3.0 V then VPR[7:0] must be set so that VLCD VDD2. (2) Automatic limitation for VLCD > 9.0 V. Fig 17. VLCD programming of PCF8537 (assuming VT[7:0] = 0h) The programmable range of VPR[7:0] is from 0h to FFh. With the upper part of the programmable range, it is possible to achieve more than 9.0 V, but the PCF8537 has a built-in automatic limitation of VLCD at 9.0 V. If VDD2 is higher than 3.0 V, then it is important that VPR[7:0] is set to a value such that the resultant VLCD (including the temperature correction of VT[7:0]) is higher than VDD2. 8.4.3 Charge pump 8.4.3.1 Charge pump configuration To obtain the desired VLCD values, the charge pump has to be configured properly. It has to be taken into account that the maximum theoretical values cannot be reached due to internal losses (see Section 8.4.3.2). So, for example, it is not possible to get a VLCD = 6.0 V with VDD2 = 3.0 V and a charge pump configuration of 2 times VDD2. In this case, a charge pump configuration of 3 times VDD2 is needed. 8.4.3.2 Charge pump driving capability Figure 18 and Figure 19 are showing the charge pump driving capability with different settings of VDD2 and charge pump configurations. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 26 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 013aaa664 10 VLCD (V) 8 (3) 6 (2) 4 (1) 2 0 0 0.2 0.4 0.6 0.8 IDD(LCD) (mA) 1 (1) VPR[7:0] = 42h. (2) VPR[7:0] = 85h. (3) VPR[7:0] = C6h. Tamb = 30 C; VDD1 = VDD2 = 3.3 V. Remark: For driving the charge pump safely the VLCD and IDD(LCD) values have to be kept below the flat part of the respective graph. Charge pump configuration: VLCD = 3 VDD2. Fig 18. Charge pump driving capability with VDD2 = 3.3 V 013aaa662 10 VLCD (V) 8 (3) 6 (2) 4 (1) 2 0 0 0.5 1 1.5 2 2.5 3 IDD(LCD) (mA) 3.5 (1) VPR[7:0] = 42h. (2) VPR[7:0] = 85h. (3) VPR[7:0] = C6h. Tamb = 30 C; VDD1 = VDD2 = 5 V. Remark: For driving the charge pump safely the VLCD and IDD(LCD) values have to be kept below the flat part of the respective graph. a. Charge pump configuration: VLCD = 2 VDD2 PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 27 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 013aaa663 10 VLCD (V) 8 (3) 6 (2) 4 (1) 2 0 0 0.4 0.8 1.2 1.6 IDD(LCD) (mA) 2 (1) VPR[7:0] = 42h. (2) VPR[7:0] = 85h. (3) VPR[7:0] = C6h. Tamb = 30 C; VDD1 = VDD2 = 5 V. Remark: For driving the charge pump safely the VLCD and IDD(LCD) values have to be kept below the flat part of the respective graph. b. Charge pump configuration: VLCD = 3 VDD2 Fig 19. Charge pump driving capability with VDD2 = 5.0 V 8.4.4 Temperature measurement and temperature compensation of VLCD 8.4.4.1 Temperature readout The PCF8537 has a built-in temperature sensor which provides an 8 bit digital value, TD[7:0], of the ambient temperature. This value can be read through the interface (see Figure 47 on page 56 and Figure 51 on page 59). The actual temperature is determined from TD[7:0] using Equation 2: T (°C) = 0.9375 TD 7:0 – 40 (2) The measurement needs about 5 ms to complete and is repeated periodically as soon as bit TME is set logic 1 (see Table 9 on page 10). The time between measurements is linked to the system clock and hence varies with changes in the chosen frame frequency, see Table 25. Table 25. Temperature measurement update rate Selected frame frequency Temperature measurement update rate 60 Hz 3.3 s 200 Hz 1s 300 Hz 0.67 s The temperature sensor can be thought of as analog to digital converter. Like all A/D converters, jitter will exist on the LSB of the output value. This is also true of the temperature sensor in the PCF8537. Jitter of the LSB of TD[7:0] may lead to contrast PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 28 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 stepping of the display due to the VLCD voltage is periodically changing between two different target voltages. For this reason, a filter has been implemented to ensure that LSB jitter does not affect the display performance. TEMPERATURE MEASUREMENT BLOCK TD[7:0] unfiltered DIGITAL TEMPERATURE FILTER TD[7:0] filtered To the readout register via I2C-bus and to the VLCD compensation block enabled or disabled by bit TFE 013aaa642 Fig 20. Temperature measurement block with digital temperature filter Like any other filtering, the digital temperature filter (see Figure 20) introduces a certain delay in the measurement of temperature. This behavior is illustrated in Figure 21. 013aaa643 50 T (°C) 16 DT (°C)(3) 40 12 30 8 (1) (2) 20 4 (3) 10 0 -4 160 0 0 40 80 120 t (s) (1) Environment temperature, T1 (C). (2) Measured temperature, T2 (C). (3) Temperature deviation, T = T2 T1. Fig 21. Temperature measurement delay during ramping up-down of the environment temperature This delay may cause undesired effects at start-up when the environment temperature may be different than the reset value of the PCF8537 which is 20 C. In this case, it takes up to 30 s until the correct measured temperature value will be available. A control bit, TFE (see Table 22 on page 16), is implemented to enable or disable the digital temperature filter. This bit is set logic 0 by default, which means, that the filter is disabled and the unfiltered environment temperature value is available to calculate the desired VLCD. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 29 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4.4.2 Temperature adjustment of the VLCD Due to the temperature dependency of the liquid crystal viscosity the LCD controlling voltage VLCD might have to be adjusted at different temperatures to maintain optimal contrast. The temperature behavior of the liquid comes from the LCD manufacturer. The slope has to be set to compensate for the liquid behavior. Internal temperature compensation may be enabled via bit TCE (see Table 9 on page 10). The ambient temperature range is split up into four equally sized regions and a different temperature coefficient can be applied to each. Each coefficient can be selected from a choice of eight different slopes. Each one of these coefficients may be independently selected (see Table 26). Table 26. Temperature coefficients SLA to SLD register value Corresponding slope factor, SFA to SFD (mV/C) 000[1] 0 001 4 010 8 011 16 100 40 101 +4 110 +8 111 +16 [1] Default value. The slope factors imply a linear correction, however the implementation is in steps of 30 mV. TD[7:0] 0h 20h 60h 40h 7Fh VLCD with temperature compensation (V) zero offset at 20 °C SFA -40 SFB -10 SFC 20 SFD 50 79 Temperature (°C) 013aaa644 Fig 22. Example of segmented temperature coefficients PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 30 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 The offset voltage is calculated according to Table 27. Table 27. Calculation of the VLCD offset voltage Temperature range Voffset(LCD) voltage (mV) T 40 C V offset LCD = 30 SFA + 30 SFB 40 C T 10 C V offset LCD = – 10 – T SFA + 30 SFB 10 C < T 20 C V offset LCD = 20 – T SFB 20 C < T 50 C V offset LCD = T – 20 SFC 50 C < T < 80 C V offset LCD = T – 50 SFD + 30 SFC 80 C V offset LCD = 30 SFD + 30 SFC [1] T[1] No temperature compensation is possible above 80 C. Above this value, the system maintains the compensation value from 80 C. Example: Assumed that Tamb = 8 C; SFB= 16 mV/C: V offset LCD = 20 – –8 x – 16 = 28 – 16 = – 448mV Remark: Care must be taken that the ranges of VPR[7:0] and VT[7:0] do not cause clipping and hence undesired results. The device will not permit overflow or underflow and will clamp results to either end of the range. 8.4.5 LCD voltage selector The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the Set-bias-mode command (see Table 14 on page 12) and the Set-MUX-mode command (see Table 13 on page 12). Intermediate LCD biasing voltages are obtained from an internal voltage divider. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 28. Discrimination is a term which is defined as the ratio of the one and off RMS voltage across a segment. It can be thought of as a measurement of contrast. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 31 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Table 28. LCD drive modes: summary of characteristics LCD drive mode Number of: Backplanes Bias levels LCD bias configuration V off RMS ----------------------V LCD V on RMS ---------------------V LCD V on RMS [1] D = ---------------------V off RMS VLCD[2] static 1 2 static 0 1 Von(RMS) 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 2.828Voff(RMS) 1:2 multiplex 2 4 1⁄ 3 0.333 0.745 2.236 3.0Voff(RMS) 5 1⁄ 4 0.395 0.729 1.845 2.529Voff(RMS) 4 3 1⁄ 2 0.433 0.661 1.527 2.309Voff(RMS) 4 4 1⁄ 3 0.333 0.577 1.732 3.0Voff(RMS) 5 1⁄ 4 0.331 0.545 1.646 3.024Voff(RMS) 3 1⁄ 2 0.456 0.612 1.341 2.191Voff(RMS) 1:2 multiplex[3] 1:4 multiplex[3] 1:4 multiplex 1:4 multiplex[3] 1:6 multiplex[3] 2 4 6 1:6 multiplex 6 4 1⁄ 3 0.333 0.509 1.527 3.0Voff(RMS) 1:6 multiplex 6 5 1⁄ 4 0.306 0.467 1.527 3.266Voff(RMS) 1:8 multiplex[3] 8 3 1⁄ 2 0.467 0.586 1.254 2.138Voff(RMS) 4 1⁄ 3 0.333 0.471 1.414 3.0Voff(RMS) 5 1⁄ 4 0.293 0.424 1.447 3.411Voff(RMS) 1:8 multiplex[3] 1:8 multiplex 8 8 [1] Determined from Equation 5. [2] Determined from Equation 4. [3] In these examples, the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a power saving from a reduction of the LCD voltage VLCD. A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode, a suitable choice is VLCD > 3Vth. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias a = 3 for 1⁄4 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 3 V on RMS = V LCD a 2 + 2a + n -----------------------------2 n 1 + a (3) where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 4 for 1:4 multiplex n = 6 for 1:6 multiplex n = 8 for 1:8 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 4: PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 32 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 V off RMS = V LCD a 2 – 2a + n -----------------------------2 n 1 + a (4) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 5: V on RMS --------------------- = V off RMS 2 a + 1 + n – 1 -------------------------------------------2 a – 1 + n – 1 (5) It should be noted that VLCD is sometimes referred as the LCD operating voltage. 8.4.5.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 23. For a good contrast performance, the following rules should be followed: V on RMS V th on (6) V off RMS V th off (7) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a (see Equation 3), n (see Equation 5), and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation voltage Vsat. It is important to match the module properties to those of the driver in order to achieve optimum performance. 100 % Relative Transmission 90 % 10 % Vth(off) OFF SEGMENT Vth(on) GREY SEGMENT VRMS [V] ON SEGMENT 013aaa494 Fig 23. Electro-optical characteristic: relative transmission curve of the liquid PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 33 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4.6 LCD drive mode waveforms 8.4.6.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. 013aaa207 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = V(Sn + 1)(t) VBP0(t). Von(RMS)(t) = VLCD. Voff(RMS)(t) = 0 V. Fig 24. Static drive mode waveforms (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 34 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4.6.2 1:2 multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8537 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 25 and Figure 26. Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. 013aaa208 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.791VLCD. Voff(RMS)(t) = 0.354VLCD. Fig 25. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 35 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Tfr BP0 BP1 Sn Sn+1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.745VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 26. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 36 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4.6.3 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 27. Tfr BP0 VLCD 2VLCD/3 VLCD/3 VSS BP1 VLCD 2VLCD/3 VLCD/3 VSS BP2 VLCD 2VLCD/3 VLCD/3 VSS BP3 VLCD 2VLCD/3 VLCD/3 VSS Sn VLCD 2VLCD/3 VLCD/3 VSS Sn+1 VLCD 2VLCD/3 VLCD/3 VSS Sn+2 VLCD 2VLCD/3 VLCD/3 VSS Sn+3 VLCD 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD state 2 VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. 013aaa211 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 27. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 37 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4.6.4 1:6 multiplex drive mode When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The PCF8537 allows the use of 1⁄3 bias or 1⁄4 bias in this mode as shown in Figure 28 and Figure 29. Tfr BP0 VLCD 2VLCD / 3 VLCD / 3 VSS BP1 VLCD 2VLCD / 3 VLCD / 3 VSS BP2 VLCD 2VLCD / 3 VLCD / 3 VSS BP3 VLCD 2VLCD / 3 VLCD / 3 VSS BP4 VLCD 2VLCD / 3 VLCD / 3 VSS BP5 VLCD 2VLCD / 3 VLCD / 3 VSS Sn VLCD 2VLCD / 3 VLCD / 3 VSS Sn + 1 VLCD 2VLCD / 3 VLCD / 3 VSS LCD segments state 1 state 2 (a) Waveforms at driver VLCD 2VLCD / 3 state 1 VLCD / 3 VSS -VLCD / 3 -2VLCD / 3 -VLCD state 2 VLCD 2VLCD / 3 VLCD / 3 VSS -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment 001aal399 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 28. Waveforms for 1:6 multiplex drive mode with 1⁄3 bias (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 38 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Tfr LCD segments VLCD 3VLCD / 4 state 1 state 2 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 VLCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS (a) Waveforms at driver VLCD 3VLCD / 4 state 1 VLCD / 4 VSS -VLCD / 4 -3VLCD / 4 -VLCD VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS state 2 -VLCD / 4 -VLCD / 2 -3VLCD / 4 -VLCD (b) Resultant waveforms at LCD segment 001aal400 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD. Fig 29. Waveforms for 1:6 multiplex drive mode with 1⁄4 bias (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 39 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.4.6.5 VLCD 3VLCD / 4 1:8 multiplex drive mode Tfr LCD segments state 1 state 2 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 3LCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD 3VLCD / 4 BP6 VLCD / 4 VSS VLCD 3VLCD / 4 BP7 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS (a) Waveforms at driver VLCD 3VLCD / 4 state 1 VLCD / 4 VSS -VLCD / 4 -3VLCD / 4 -VLCD state 2 VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS -VLCD / 4 -VLCD / 2 -3VLCD / 4 -VLCD (b) Resultant waveforms at LCD segment 001aal398 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD. Fig 30. Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (line inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 40 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 VLCD 3/4 VLCD Tfr frame n Tfr frame n+1 LCD segments state 1 BP0 state 2 1/4 VLCD VSS VLCD 3/4 VLCD BP1 1/4 VLCD VSS VLCD 3/4 VLCD BP2 1/4 VLCD VSS VLCD 3/4 VLCD BP3 1/4 VLCD VSS VLCD 3/4 VLCD BP4 1/4 VLCD VSS VLCD 3/4 VLCD BP5 1/4 VLCD VSS VLCD 3/4 VLCD BP6 1/4 VLCD VSS VLCD 3/4 VLCD BP7 1/4 VLCD VSS VLCD Sn 1/2 VLCD VSS VLCD Sn + 1 1/2 VLCD VSS (a) Waveforms at driver state 1 VLCD 3/4 VLCD 1/2 VLCD 1/4 VLCD VSS 1/4 VLCD 1/2 VLCD 3/4 VLCD VLCD state 2 VLCD 3/4 VLCD 1/2 VLCD 1/4 VLCD VSS 1/4 VLCD 1/2 VLCD 3/4 VLCD VLCD (b) Resultant waveforms at LCD segment 001aam359 Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD. Fig 31. Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (frame inversion mode) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 41 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.5 Backplane and segment outputs 8.5.1 Backplane outputs The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane output signals are generated based on the selected LCD multiplex drive mode. Table 29 describes which outputs are active for each of the multiplex drive modes and what signal is generated. Table 29. Mapping of output pins and corresponding signals with respect to driving mode MUX mode Output pin BP0 BP1 BP2 BP3 BP4 BP5 S45/BP6 S44/BP7 Signal 1:8 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 1:6 BP0 BP1 BP2 BP3 BP4 BP5 S45 S44 1:4 BP0 BP1 BP2 BP3 BP0[1] BP1[1] BP2[1] BP3[1] 1:2 BP0 BP1 BP0[1] BP1[1] BP0[1] BP1[1] BP0[1] BP1[1] static BP0 BP0[1] BP0[1] BP0[1] BP0[1] BP0[1] BP0[1] BP0[1] [1] 8.5.1.1 These pins may optionally or alternatively be connected to the display to improve drive strength. Connect only with the corresponding output pin carrying the same signal. If not required, they can be left open circuit. 1:8 multiplex drive mode In 1:8 multiplex drive mode, BP0 to BP7 must be connected directly to the LCD. 8.5.1.2 1:6 multiplex drive mode 1:6 multiplex mode is a special case. In this mode BP0 to BP5 must be connected directly to the display as back plane signals and S44 and S45 must be connected to the display as segment signals. 8.5.1.3 1:4 multiplex drive mode In the 1:4 multiplex drive mode, BP0 to BP3 must be connected directly to the LCD. The unused BPs may be left open-circuit. Optionally they may also be connected to the display to increase drive strength. • • • • 8.5.1.4 BP0 is repeated on BP4 BP1 is repeated on BP5 BP2 is repeated on BP6 BP3 is repeated on BP7 1:2 multiplex drive mode In the 1:2 multiplex drive mode, BP0 and BP1 must be connected directly to the LCD. The unused BPs may be left open-circuit. Optionally they may also be connected to the display to increase drive strength. • BP0 is repeated on BP2, BP4, and BP6 • BP1 is repeated on BP3, BP5, and BP7 PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 42 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.5.1.5 Static drive mode In the static drive mode, BP0 must be connected directly to the LCD. In the static drive mode, the same signal is carried by all eight backplane outputs and they can be connected in parallel for very high drive requirements. • BP0 is repeated on BP1, BP2, BP3, BP4, BP5, BP6, and BP7 8.5.2 Segment outputs The LCD drive section includes up to 46 segment outputs. Segments S0 to S43 are always segment outputs. There are also two more segment outputs which become active in 1:6 multiplex mode. These are S45/BP6 and S44/BP7 and must also be connected directly to the display. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 46 segment outputs are required, the unused segment outputs must be left open-circuit. 8.5.2.1 Static, 1:8, 1:4, 1:2 multiplex drive mode In these drive modes, segments S0 to S43 must be connected to the display. 8.5.2.2 1:6 multiplex drive mode In this drive mode, segments S0 to S43, S44, and S45 must be connected to the display. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 43 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.6 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8537 and co-ordinates their effects. The controller is also responsible for loading display data into the display RAM as required by the filling order. 8.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. 8.8 Display RAM The display RAM stores LCD data. Depending on the multiplex drive mode, the arrangement of the RAM is changed. • • • • • multiplex drive mode 1:8: RAM is 44 8 bit multiplex drive mode 1:6: RAM is 46 6 bit multiplex drive mode 1:4: RAM is 44 4 bit arranged in two banks multiplex drive mode 1:2: RAM is 44 2 bit arranged in two banks static drive mode: RAM is 44 1 bit arranged in two banks A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements, • the RAM columns and the segment outputs, • the RAM rows and the backplane outputs. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 44 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Display RAM addresses (columns)/segment outputs (S) Multiplex drive mode 1:8 S0 S1 S2 S3 S4 S5 S6 S7 S38 S39 S40 S41 S42 S43 S3 S4 S5 S6 S7 S38 S39 S40 S41 S42 S43 S44 S45 S3 S4 S5 S6 S7 S38 S39 S40 S41 S42 S43 row0/BP0 row1/BP1 row2/BP2 row3/BP3 row4/BP4 row5/BP5 row6/BP6 row7/BP7 Multiplex drive mode 1:6 Display RAM bits (rows)backplane outputs (BP) S0 S1 S2 row0/BP0 row1/BP1 row2/BP2 row3/BP3 row4/BP4 row5/BP5 Multiplex drive mode 1:4 S0 S1 S2 row0/BP0 row1/BP1 row2/BP2 row3/BP3 row4/BP0 row5/BP1 row6/BP2 row7/BP3 bank 0 bank 1 Multiplex drive mode 1:2 S0 S1 S2 S3 S4 S5 S6 S7 S38 S39 S40 S41 S42 S43 row0/BP0 row1/BP1 row2 row3 row4/BP0 row5/BP1 row6 row7 bank 0 bank 1 Static drive mode S0 S1 S2 S3 S4 S5 S6 S7 S38 S39 S40 S41 S42 S43 bank 0 row0/BP0 row1 row2 row3 row4/BP1 row5 row6 row7 bank 1 013aaa645 The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs; and between the bits in a RAM row and the backplane outputs. Fig 32. Display RAM bitmap PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 45 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 The display RAM bit map, Figure 32, shows row 0 to row 7 which correspond with the backplane outputs BP0 to BP7, and column 0 to column 45 which correspond with the segment outputs S0 to S45. In multiplexed LCD applications, the data of each row of the display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1 with BP1, and so on). When display data is transmitted to the PCF8537, the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode. The data is stored as it arrives. Depending on the current multiplex drive mode, data is stored singularly, in pairs, quadruples, sextuples or bytes. 8.8.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the Load-data-pointer command (see Table 15 on page 12). Following this command, an arriving data byte is stored starting at the display RAM address indicated by the data pointer. After each byte stored, the data pointer is automatically incremented in accordance with the chosen LCD multiplex drive mode configuration: • • • • • by eight (static drive mode) by four (1:2 multiplex drive mode) by two (1:4 multiplex drive mode) by one or two (1:6 multiplex drive mode), see Figure 37 on page 49 by one (1:8 multiplex drive mode) When the address counter reaches the end of the RAM row, it stops incrementing after the last byte is transmitted. Redundant bits of the last byte transmitted are discarded. Additional bytes, sent after the end of the RAM is reached, will be discarded too. The data pointer does not wrap around to the beginning. To send new RAM data, the data pointer must be reset. If an I2C-bus or SPI-bus data access is terminated early, then the state of the data pointer is unknown. The data pointer must then be re-written before further RAM accesses. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 46 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.8.2 RAM filling in static drive mode In the static drive mode the eight transmitted data bits are placed in eight successive display RAM columns in row 0 (see Figure 33). columns display RAM columns/segment outputs (S) rows 0 1 2 3 4 5 6 7 39 40 41 42 43 display RAM rows/ 0 b7 b6 b5 b4 b3 b2 b1 b0 backplane outputs (BP) b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB transmitted data byte 013aaa646 Fig 33. Display RAM filling order in static drive mode In order to fill the whole RAM row, 6 bytes must be sent to the PCF8537, but the last 4 bits from the last byte are discarded (see Figure 34). data pointer 0 1 2 3 4 5 6 32 33 34 35 36 37 38 39 40 41 42 43 7 0 a7 a6 a5 a4 a3 a2 a1 a0 e7 e6 e5 e4 e3 e2 e1 e0 f7 f6 f5 f4 f3 f2 f1 f0 discarded display RAM 013aaa647 Fig 34. Discarded bits at the end of data transmission When bit IBS is set to bank 1 (see Table 18 on page 14), then data is stored in row 4. 8.8.3 RAM filling in 1:2 multiplex drive mode In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four successive display RAM columns (see Figure 35). In order to fill the whole two RAM rows 11 bytes need to be sent to the PCF8537. columns display RAM columns/segment outputs (S) rows 0 1 2 3 4 5 6 7 39 40 41 42 43 display RAM rows/ 0 b7 b5 b3 b1 backplane outputs 1 b6 b4 b2 b0 (BP) LSB b7 b6 b5 b4 b3 b2 b1 b0 MSB transmitted data byte 013aaa648 Fig 35. Display RAM filling order in 1:2 multiplex drive mode PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 47 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 When bit IBS is set to bank 1 (see Table 18 on page 14), then data is stored in row 4 and row 5. 8.8.4 RAM filling in 1:4 multiplex drive mode In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two successive display RAM columns of four rows (see Figure 36). In order to fill the whole four RAM rows 22 bytes need to be sent to the PCF8537. columns display RAM columns/segment outputs (S) 0 1 2 0 b7 b3 1 b6 b2 rows 3 4 5 6 7 39 40 41 42 43 2 b5 b1 display RAM rows/ backplane outputs (BP) 3 b4 b0 b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB transmitted data byte 013aaa649 Fig 36. Display RAM filling order in 1:4 multiplex drive mode When bit IBS is set to bank 1 (see Table 18 on page 14), then data is stored in rows 4 to row 7. 8.8.5 RAM filling in 1:6 multiplex drive mode In the 1:6 multiplex drive mode the RAM is organized in six rows and 46 columns. The eight transmitted data bits are placed in such a way, that a column is filled up (see Figure 37). The remaining bits are wrapped up into the next column. In order to fill the whole RAM addresses 35 bytes need to be sent to the PCF8537, however the four least significant bits of the 35th byte are discarded. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 48 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 columns display RAM columns/segment outputs (S) data pointer incrementation 0 1 2 3 4 5 6 7 41 42 43 44 45 0 a7 a1 b3 c5 rows display RAM rows/ backplane outputs (BP) h3 1 a6 a0 b2 c4 h2 2 a5 b7 b1 c3 h7 h1 3 a4 b6 b0 c2 h6 h0 4 a3 b5 c7 c1 h5 5 a2 b4 c6 c0 h4 discarded MSB LSB a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 transmitted data bytes 013aaa650 Fig 37. Display RAM filling order in 1:6 multiplex drive mode When data transfer is initiated, then the MSB of the first byte will always be placed in row 0. Data must be transferred contiguously to achieve RAM filling as described in Figure 37. 8.8.6 RAM filling in 1:8 multiplex drive mode In the 1:8 multiplex drive mode the eight transmitted data bits are placed into eight rows of one display RAM column (see Figure 38). In order to fill the whole RAM addresses 44 bytes need to be sent to the PCF8537. columns transmitted data byte display RAM columns/segment outputs (S) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 39 40 41 42 43 0 b7 1 b6 rows 2 b5 display RAM rows/ backplane outputs (BP) 3 b4 4 b3 5 b2 6 b1 7 b0 013aaa651 Fig 38. Display RAM filling order in 1:8 multiplex drive mode PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 49 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.9 Bank selection The PCF8537 includes a RAM bank switching feature in the static, 1:2, and 1:4 multiplex drive modes. A bank can be thought of as a collection of RAM rows. The RAM bank switching gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is complete. There are two banks; bank 0 and bank 1. Figure 32 on page 45 shows the location of these banks relative to the RAM map. Input and output banks can be set independently from one another with the Bank-select command (see Table 18 on page 14). Figure 39 shows the concept. IBS CONTROLS THE INPUT DATA PATH OBS CONTROLS THE OUTPUT DATA PATH BANK 0 MICROCONTROLLER RAM DISPLAY BANK 1 013aaa423 Fig 39. Bank selection In Figure 40 an example is shown for 1:4 multiplex drive mode where the displayed data is read from the first four rows of the memory (bank 0), while the transmitted data is stored in the second four rows of the memory (bank 1). columns display RAM columns/segment outputs (S) 0 1 2 3 4 5 6 7 39 40 41 42 43 output RAM bank 0 1 rows to the LCD 2 display RAM rows/ backplane outputs (BP) 3 4 5 to the RAM 6 7 input RAM bank 013aaa652 Fig 40. Example of the Bank-select command with multiplex drive mode 1:4 8.9.1 Input bank selection The IBS (input bank selection) bit of the Bank-select command (see Table 18) controls where display data is loaded into the display RAM. The input bank selection works independently of output bank selection. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 50 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 8.9.2 Output bank selection The OBS bit of the Bank-select command (see Table 18 on page 14) controls from which bank display data is taken, The output bank selection works independently of input bank selection. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 51 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 9. Bus interfaces 9.1 Control byte After initiating the communication over the bus and sending the slave address (I2C-bus, see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The purpose of this byte is to indicate both, the content for the following data bytes (RAM or command) and to indicate that more control bytes will follow. Typical sequences could be: • Slave address/subaddress - control byte - command byte - command byte - command byte - end • Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end • Slave address/subaddress - control byte - command byte - control byte - RAM byte end In this way, it is possible to send a mixture of RAM and command data in one access or alternatively, to send just one type of data in one access. Table 30. Control byte description Bit Symbol 7 CO 6 5 to 0 Binary value Description continue bit 0 last control byte 1 control bytes continue RS register selection 0 command register 1 data register - not relevant MSB 7 6 5 CO RS 4 3 2 1 LSB 0 not relevant mgl753 Fig 41. Control byte format PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 52 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 9.2 I2C-bus interface characteristics (PCF8537AH) The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.2.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 42). SDA SCL data line stable; data valid change of data allowed mba607 Fig 42. Bit transfer 9.2.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 43. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 43. Definition of START and STOP conditions 9.2.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 44. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 53 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 44. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 45. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 45. Acknowledgement on the I2C-bus 9.2.5 I2C-bus controller The PCF8537AH acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from PCF8537AH are the acknowledge signals and the temperature readout byte of the selected device. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 54 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 9.2.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 9.2.7 I2C-bus slave address The device selection depends on the I2C-bus slave address. Two different I2C-bus slave addresses can be used to address the PCF8537AH (see Table 31). Table 31. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 MSB 0 0 LSB 1 1 1 0 0 A0 R/W Bit 1 of the slave address is defined by connecting the input A0 to either VSS (logic 0) or VDD (logic 1). Therefore, two instances of PCF8537AH can be distinguished on the same I2C-bus. The least significant bit of the slave address byte is bit R/W (see Table 32). Table 32. R/W bit description Symbol Value R/W [1] Description data read or write selection 0 write data 1 read data[1] Only used for temperature readout from PCF8537AH (see Table 20 on page 15). 9.2.8 I2C-bus protocol The I2C-bus protocol is shown in Figure 46. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8537AH slave addresses available. All PCF8537AH’s with the corresponding A0 level acknowledge in parallel to the slave address, but all PCF8537AH with an alternative A0 level ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows (see Section 9.1 on page 52). PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 55 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 R/W = 0 slave address control byte S 0 1 1 1 0 0 A 0 A C R O S 0 RAM/command byte L S P B M A S B EXAMPLES a) transmit two bytes of RAM data S 0 1 1 1 0 0 A 0 A 0 1 0 A RAM DATA A A COMMAND A 0 0 A COMMAND A P COMMAND A 0 1 A RAM DATA A RAM DATA A P b) transmit two command bytes S 0 1 1 1 0 0 A 0 A 1 0 0 c) transmit one command byte and two RAM date bytes S 0 1 1 1 0 0 A 0 A 1 0 0 A RAM DATA A P 013aaa653 Fig 46. I2C-bus protocol, write mode The display bytes are stored in the display RAM at the address specified by the data pointer. The acknowledgement after each byte is made only by the addressed PCF8537AH. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access. 9.2.9 Data read If a temperature readout (byte TD[7:0]) is made, the R/W bit must be logic 1 and then the next data byte following is provided by the PCF8537AH as shown in Figure 47. R/W = 1 slave address S 0 1 1 1 0 0 temperature readout byte M A 1 A S 0 B acknowledge from PCF8537AH L S A P B acknowledge from master 013aaa677 Fig 47. I2C-bus protocol, read mode PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 56 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 9.3 SPI-bus interface (PCF8537BH) Data transfer to the device is made via a three-line SPI-bus (see Table 30). The SPI-bus is reset whenever the chip enable pin CE is inactive. Table 33. Pin Serial interface Function Description LOW[1] CE chip enable input; active SCL serial clock input when HIGH, the interface is reset; - SDIO serial data input output input data is sampled on the rising edge of SCL; data is output on the falling edge of SCL [1] The chip enable must not be wired permanently LOW. 9.3.1 Data transmission The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first. The transmission is controlled by the active LOW chip enable signal CE. The first byte transmitted is the subaddress byte. data bus SUBADDRESS DATA DATA DATA CE 013aaa464 Fig 48. Data transfer overview The subaddress byte opens the communication with a read/write bit and a subaddress. The subaddress is used to identify multiple devices on one SPI-bus. Table 34. Subaddress byte definition Bit Symbol 7 R/W Binary value Description data read or write selection 0 write data 1 read data[1] 6 to 5 SA[1:0] 01 subaddress; other codes will cause the device to ignore data transfer 4 to 0 - - unused [1] Only used for temperature readout from PCF8537BH (see Table 20 on page 15). After the subaddress byte, a control byte follows (see Section 9.1 on page 52). PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 57 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 R/W = 0 subaddress control byte RAM/command byte 0 0 1 L S B M S B C R O S EXAMPLES a) transmit two bytes of display RAM data 0 1 0 0 1 RAM DATA RAM DATA b) transmit two command bytes 0 0 1 1 0 COMMAND 0 0 COMMAND 0 1 RAM DATA c) transmit one command byte and two display RAM date bytes 0 0 1 1 0 COMMAND RAM DATA 013aaa656 Data transfers are terminated by de-asserting CE (set CE to logic 1) Fig 49. SPI-bus write example R/W b7 0 SA b6 0 unused b5 1 b4 0 b3 0 b2 0 multiplex drive mode = 1:8 M[2:0] = 111 command byte b1 0 b0 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 1 SCL SDIO CE 013aaa657 In this example, the multiplex mode is set to 1:8. The transfer is terminated by CE returning to logic 1. After the last bit is transmitted, the state of the SDIO line is not important. Fig 50. SPI-bus write example 9.3.2 Data read The temperature readout data byte TD[7:0] can be read from the PCF8537BH. A readout is initiated by sending the subaddress byte with the R/W bit set high. The transmission is controlled by the active LOW chip enable signal CE. After the last bit of the subaddress byte is transmitted, the PCF8537BH will immediately start to drive the SDIO line. It is only necessary to read the values once, however since the update of the register is asynchronous to the interface clock, it is recommended to read the register twice and check for a stable value. The readout is terminated by asserting CE. At this time, the SDIO bus is released. It is important that the bus is not left floating and that the microcontroller then takes over driving of the bus. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 58 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 R/W b7 1 unused SA b6 0 b5 1 b4 0 b3 0 b2 0 temperature data 11BCD temperature data 11BCD b1 0 b0 0 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 SCL SDIO CE microcontroller driving SDIO PCF8537BH driving SDIO 013aaa678 Fig 51. SPI-bus read example PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 59 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 10. Internal circuitry VDD1 A0, RESET, T1, T2, CLK VSS T3, VLCD, SDA, SCL, VDD1, VDD2 VLCD BP0 to BP5, S0 to S43, BP7/S44, BP6/S45 VSS (1) VSS 013aaa659 (1) Output resistance, RO, see Table 36 on page 62. Fig 52. Device protection diagram for PCF8537AH VDD1 SDIO, RESET, T1, T2, CLK VSS T3, VLCD, CE, SCL, VDD1, VDD2 VLCD BP0 to BP5, S0 to S43, BP7/S44, BP6/S45 VSS (1) VSS 013aaa660 (1) Output resistance, RO, see Table 36 on page 62. Fig 53. Device protection diagram for PCF8537BH PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 60 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 11. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD1 VDD2 supply voltage 1 digital 0.5 +6.5 V supply voltage 2 analog 0.5 +6.5 V IDD1 supply current 1 digital 50 +50 mA IDD2 supply current 2 analog 50 +50 mA VLCD LCD supply voltage 0.5 +10 V IDD(LCD) LCD supply current 50 +50 mA Vi input voltage 0.5 +6.5 V II input current 10 +10 mA VO output voltage on pins S0 to S45, BP0 to BP7 0.5 +10 V on pins SDA, SDIO, CLK 0.5 +6.5 V IO output current 10 +10 mA ISS ground supply current 50 +50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW VESD electrostatic discharge voltage HBM [1] - 4500 V CDM [2] - 1500 V latch-up current [3] - 200 mA Tstg storage temperature [4] 65 +150 C Tamb ambient temperature 40 +85 C Ilu PCF8537 Product data sheet on pins CLK, CE, SDA, SCL, A0, SDIO, T1, T2 operating device [1] Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”. [2] Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101”. [3] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)). [4] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 61 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 12. Static characteristics Table 36. Static characteristics VDD1 = 1.8 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; temperature measurement enabled; 1:8 multiplex drive mode; 1⁄4 bias; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; internal clock with maximum prescale factor; I2C-bus/SPI-bus inactive; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VDD1 supply voltage 1 logic 1.8 - 5.5 V VDD2 supply voltage 2 analog; VDD2 VDD1 2.5 - 5.5 V Supplies charge pump set to 2 VDD2 charge pump set to 3 VDD2 VLCD LCD supply voltage 2.5 - 5.5 V VLCD VDD2 [1] 2.5 - 9.0 V [2] 0.10 - +0.10 V VLCD LCD voltage variation VDD1 = VDD2 = 5.0 V; VLCD = 6.99 V IDD1 supply current 1 digital; display disabled; charge pump off - 90 200 A IDD2 supply current 2 display disabled; charge pump off; external VLCD - 0.5 - A - 30 40 A - 200 - A - 85 - A VDD2 = 5.5 V; charge pump set to 2 VDD2; internal VLCD = 7.0 V display disabled display enabled external VLCD = 7.0 V; display enabled; [3] IDD(LCD) LCD supply current IDD(pd) power-down mode supply on pin VDD1 current - 1 3 A ILCD(pd) power-down LCD current - 15 25 A Tacc temperature accuracy readout temperature error; VDD1 = 5.0 V Tamb = 40 C to +85 C 5 - +5 C Tamb = 25 C 3 - +3 C Logic VSS 0.5 - VDD + 0.5 V on pins CLK and A0 - - 0.3VDD V on pins CLK and A0 0.7VDD - - V output voltage 0.5 - VDD + 0.5 V VOH HIGH-level output voltage on pin CLK 0.8VDD - - VOL LOW-level output voltage - - 0.2VDD V IOH HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V; on pin CLK 1 - - mA VI input voltage VIL LOW-level input voltage VIH HIGH-level input voltage VO PCF8537 Product data sheet on pin CLK All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 V © NXP B.V. 2012. All rights reserved. 62 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Table 36. Static characteristics …continued VDD1 = 1.8 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; temperature measurement enabled; 1:8 multiplex drive mode; 1⁄4 bias; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; internal clock with maximum prescale factor; I2C-bus/SPI-bus inactive; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V; on pin CLK 1 - - mA VPOR power-on reset voltage - - 1.6 V IL leakage current 1 - +1 A pins SDA, SCL VSS 0.5 - 5.5 V pin SDIO VSS 0.5 - VDD + 0.5 V [4] Vi = VDD or VSS; on pins CLK and A0 I2C- and SPI-bus lines; pins SDA, SCL and SDIO input voltage VI VIL LOW-level input voltage pins SDA, SCL, and SDIO - - 0.3VDD V VIH HIGH-level input voltage pins SDA, SCL, and SDIO 0.7VDD - - V VO output voltage pins SDA and SCL 0.5 - 5.5 V SDIO 0.5 - VDD + 0.5 V VOL = 0.4 V; VDD = 5 V; on pin SDA and SDIO 3 - - mA IOL LOW-level output current IOH HIGH-level output current VOH = 4.6 V; VDD = 5 V; on pin SDIO 3 - - mA IL leakage current VI = VDD or VSS 1 - +1 A output voltage variation on pins BP0 to BP7 [5] 15 - +15 mV on pins S0 to S45 [6] 15 - +15 mV VLCD = 7 V; on pins BP0 to BP7 [7] 0.3 0.8 1.5 k VLCD = 7 V; on pins S0 to S45 [7] 0.6 1.5 3 k LCD outputs VO output resistance RO [1] When supplying external VLCD it must be VLCD VDD2. Also when using the internal charge pump to generate a certain VLCD, VPR[7:0] must be set to a value that the voltage is higher than VDD2 (see Section 8.4.2). [2] Calibrated at testing stage. VLCD temperature compensation is disabled. [3] Tested on sample basis. [4] If VDD1 < VPOR a reset occurs. [5] Variation between any 2 backplanes on a given voltage level; static measured. [6] Variation between any 2 segments on a given voltage level; static measured. [7] Outputs measured one at a time. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 63 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 013aaa687 195 ΔVLCD (mV) 130 65 0 -65 -130 -195 -60 -40 -20 0 20 40 60 80 Temperature (ºC) 100 VLCD = 5 V to 9 V. Remark: Only valid if the charge pump is driven in a safe range as described in Figure 18 and Figure 19. a. VDD = 5 V 013aaa688 195 ΔVLCD (mV) 130 65 0 -65 -130 -195 -60 -40 -20 0 20 40 60 80 Temperature (ºC) 100 VLCD = 5 V to 9 V. Remark: Only valid if the charge pump is driven in a safe range as described in Figure 18 and Figure 19. b. VDD = 3 V Fig 54. LCD voltage variation with respect to temperature PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 64 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 013aaa668 160 IDD1 (μA) 150 140 (1) (2) 130 120 110 100 -60 -40 -20 0 20 40 60 80 Temperature (ºC) 100 VDD2 = 5.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; LCD outputs are open circuit; RAM all logic 1; inputs at VSS or VDD; internal clock with max prescale factor; bus active. (1) Charge pump on; VDD1 = 5.5 V; charge pump configuration: VLCD = 2 VDD2; VPR[7:0] set to 7.0 V; display enabled. (2) Charge pump off; VDD1 = 5.0 V; display disabled. Fig 55. Typical IDD1 with respect to temperature 013aaa669 160 IDD2 (μA) 150 140 130 120 110 100 -60 -40 -20 0 20 40 60 80 Temperature (ºC) 100 VDD1 = VDD2 = 5.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; flat temperature compensation; LCD outputs are open circuit; RAM all logic 1; inputs at VSS or VDD; internal clock with max prescale factor; bus inactive; charge pump on; charge pump configuration: VLCD = 2 VDD2; VPR[7:0] set to 7.0 V; display enabled. Fig 56. Typical IDD2 with respect to temperature PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 65 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 013aaa670 140 IDD(LCD) ( (μA) 130 120 110 100 90 80 -60 -40 -20 0 20 40 60 80 Temperature (ºC) 100 VDD1 = VDD2 = 5.0 V; 1:8 multiplex drive mode; 1⁄4 bias; temperature measurement enabled; flat temperature compensation; LCD outputs are open circuit; RAM all logic 1; inputs at VSS or VDD; internal clock with max prescale factor; bus inactive; charge pump on; charge pump configuration: VLCD = 7.0 V, external supplied; display enabled. Fig 57. Typical IDD(LCD) with respect to temperature PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 66 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 13. Dynamic characteristics Table 37. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions fclk(ext) external clock frequency tclk(H) clock HIGH time tclk(L) clock LOW time external clock source used fclk clock frequency tw(rst)L LOW-level reset time [1] [1] on pin CLK; see Table 17 Min Typ Max Unit 450 - 14500 Hz 33 - - s 33 - - s 7800 9600 11040 Hz 400 - - ns Frequency present on OSCCLK with default display frequency division factor. 1/fclk tclk(H) tclk(L) 0.7 VDD CLK 0.3 VDD 013aaa296 Fig 58. Driver timing waveforms tw(rst)L RESET 0.3 VDD 013aaa665 Fig 59. RESET timing PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 67 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Table 38. Timing characteristics: I2C-bus VDD1 = 1.8 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter fSCL tBUF Conditions Min Typ Max Unit SCL clock frequency - - 400 kHz bus free time between a STOP and START condition 1.3 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tVD;DAT data valid time [4] - - 0.9 s tVD;ACK data valid acknowledge time [5] - - 0.9 s tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock 0.6 - - s tf fall time of both SDA and SCL signals - - 0.3 s tr rise time of both SDA and SCL signals - - 0.3 s Cb capacitive load for each bus line - - 400 pF tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 0.6 - - s tw(spike) spike pulse width - - 50 ns [1] Internal calibration made with OTP so that the maximum variation is 15 % over whole temperature and voltage range. The typical fclk frequency generates a typical frame frequency of 200 Hz when the default frequency division factor is used. [2] The typical value is defined at VDD1 = VDD2 = 5.0 V and 30 C. [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. [4] tVD;DAT = minimum time for valid SDA output following SCL LOW. [5] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW. protocol bit 7 MSB (A7) START condition (S) tSU;STA tLOW bit 6 (A6) tHIGH 1/f bit 0 (R/W) acknowledge (A) STOP condition (P) SCL SCL tBUF tr tf SDA tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 013aaa417 Fig 60. I2C-bus timing waveforms PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 68 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Table 39. Timing characteristics: SPI-bus VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Symbol Parameter Conditions VDD < 2.7 V VDD 2.7 V Min Max Min Max Unit Timing characteristics (see Figure 61) fclk(SCL) SCL clock frequency - 2 - 5 MHz tSCL SCL time 500 - 200 - ns tclk(H) clock HIGH time 200 - 80 - ns tclk(L) clock LOW time 200 - 80 - ns tr rise time for SCL signal - 100 - 100 ns for SCL signal tf fall time - 100 - 100 ns tsu(CE) CE set-up time 150 - 80 - ns th(CE) CE hold time 0 - 0 - ns trec(CE) CE recovery time 100 - 100 - ns tsu set-up time set-up time for SDI data 35 - 10 - ns th hold time hold time for SDI data 25 - 15 - ns CE tsu(CE) tSCL tclk(H) tr tf trec(CE) th(CE) 70 % SCL 30 % tclk(L) tsu th SDIO b7 b6 b0 Write example tdis(SDIO) tt(SDIO-SDIO) SDIO b7 b6 b0 b7 b6 b0 Read example td(R)SDIO Microcontroller driving SDIO bus PCF8537BH driving SDIO bus 013aaa679 Fig 61. SPI-bus timing PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 69 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 14. Package outline TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1 c y X A 48 33 49 32 ZE e E HE A (A 3) A2 A 1 wM pin 1 index θ bp 64 Lp L 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.1 Z D(1) Z E(1) 1.45 1.05 1.45 1.05 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT357-1 137E10 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 02-03-14 Fig 62. Package outline SOT357-1 (TQFP64) PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 70 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • PCF8537 Product data sheet Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 71 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 63) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 40 and 41 Table 40. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 41. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 63. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 72 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 63. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 73 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 17. Abbreviations Table 42. PCF8537 Product data sheet Abbreviations Acronym Description AEC Automotive Electronics Council CMOS Complementary Metal Oxide Semiconductor DC Direct Current EPROM Erasable Programmable Read-Only Memory HBM Human Body Model I2C Inter-Integrated Circuit bus IC Integrated Circuit LCD Liquid Crystal Display LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer OTP One Time Programmable PCB Printed-Circuit Board POR Power-On Reset RC Resistance-Capacitance RAM Random Access Memory RMS Root Mean Square SCL Serial Clock Line SDA Serial DAta line SMD Surface Mount Device SPI Serial Peripheral Interface All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 74 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 18. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — ESD and EMC sensitivity of IC [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [7] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [8] JESD78 — IC Latch-Up Test [9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] NX3-00092 — NXP store and transport requirements [11] SNV-FA-01-02 — Marking Formats Integrated Circuits [12] UM10204 — I2C-bus specification and user manual PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 75 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 19. Revision history Table 43. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8537 v.1 20120531 Product data sheet - - PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 76 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCF8537 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 77 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 78 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 22. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description of PCF8537AH and PCF8537BH . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Commands of PCF8537 . . . . . . . . . . . . . . . . . .7 Initialize - initialize command bit description . . .8 OTP-refresh - OTP-refresh command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Oscillator-ctrl - oscillator control command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Charge-pump-ctrl - charge pump control command bit description . . . . . . . . . . . . . . . . . .9 Temp-msr-ctrl - temperature measurement control command bit description . . . . . . . . . . . . . . . . .10 Temp-comp - temperature compensation coefficients command . . . . . . . . . . . . . . . . . . .10 Set-VPR - set VPR command bit description . 11 Display-enable - display enable command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Set-MUX-mode - set multiplex drive mode command bit description . . . . . . . . . . . . . . . . .12 Set-bias-mode - set bias mode command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Load-data-pointer - load data pointer command bit description . . . . . . . . . . . . . . . . . . . . . . . . .12 Frame frequency - frame frequency and output clock frequency command bit description . . . .13 Frame frequency values . . . . . . . . . . . . . . . . .13 Bank-select - bank select command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Write-RAM-data - write RAM data command bit description . . . . . . . . . . . . . . . . . . . . . . . . .14 Temp-read - temperature readout command bit description . . . . . . . . . . . . . . . . . . . . . . . . .15 Invmode_ctrl - drive scheme inversion command bit description . . . . . . . . . . . . . . . . .15 Temp-filter - digital temperature filter command bit description . . . . . . . . . . . . . . . . . . . . . . . . .16 Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Selection of display configurations . . . . . . . . . .23 Temperature measurement update rate . . . . . .28 Temperature coefficients. . . . . . . . . . . . . . . . . .30 Calculation of the VLCD offset voltage. . . . . . . .31 LCD drive modes: summary of characteristics .32 Mapping of output pins and corresponding signals with respect to driving mode. . . . . . . . .42 Control byte description . . . . . . . . . . . . . . . . . .52 I2C slave address byte . . . . . . . . . . . . . . . . . . .55 R/W bit description . . . . . . . . . . . . . . . . . . . . . .55 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . .57 Subaddress byte definition . . . . . . . . . . . . . . . .57 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .61 Static characteristics . . . . . . . . . . . . . . . . . . . .62 Dynamic characteristics . . . . . . . . . . . . . . . . . .67 Timing characteristics: I2C-bus . . . . . . . . . . . .68 Timing characteristics: SPI-bus . . . . . . . . . . . .69 PCF8537 Product data sheet Table 40. Table 41. Table 42. Table 43. SnPb eutectic process (from J-STD-020C) . . . 72 Lead-free process (from J-STD-020C) . . . . . . 72 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 74 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 76 All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 79 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 23. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Block diagram of PCF8537AH . . . . . . . . . . . . . . . .3 Block diagram of PCF8537BH . . . . . . . . . . . . . . . .4 Pin configuration for TQFP64 (PCF8537AH). . . . .5 Pin configuration for TQFP64 (PCF8537BH). . . . .5 Recommended start-up sequence when using the internal charge pump and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Recommended start-up sequence when using an external supplied VLCD and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Recommended start-up sequence when using the internal charge pump and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Recommended start-up sequence when using an external supplied VLCD and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Recommended power-down sequence when using an external supplied VLCD and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Recommended power-down sequence when using the internal charge pump and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Recommended power-down sequence for minimum power-down current when using an external supplied VLCD and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Example of displays suitable for PCF8537 . . . . .23 Typical I2C system configuration when using the internal VLCD generation . . . . . . . . . . . . . . . .24 Typical SPI system configuration when using an external VLCD . . . . . . . . . . . . . . . . . . . . . . . . .24 VLCD generation including temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .25 VLCD programming of PCF8537 (assuming VT[7:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Charge pump driving capability with VDD2 = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Charge pump driving capability with VDD2 = 5.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Temperature measurement block with digital temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .29 Temperature measurement delay during ramping up-down of the environment temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Example of segmented temperature coefficients.30 Electro-optical characteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .33 Static drive mode waveforms (line inversion mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias (line inversion mode) . . . . . . . . . . . .35 Waveforms for the 1:2 multiplex drive mode PCF8537 Product data sheet Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Fig 43. Fig 44. Fig 45. Fig 46. Fig 47. Fig 48. Fig 49. Fig 50. Fig 51. Fig 52. Fig 53. Fig 54. Fig 55. Fig 56. Fig 57. Fig 58. Fig 59. Fig 60. Fig 61. Fig 62. Fig 63. with 1⁄3 bias (line inversion mode) . . . . . . . . . . . . 36 Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias (line inversion mode) . . . . . . . . . . . . 37 Waveforms for 1:6 multiplex drive mode with 1⁄3 bias (line inversion mode) . . . . . . . . . . . . 38 Waveforms for 1:6 multiplex drive mode with 1⁄4 bias (line inversion mode) . . . . . . . . . . . . 39 Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (line inversion mode) . . . . . . . . . . . . 40 Waveforms for 1:8 multiplex drive mode with 1⁄4 bias (frame inversion mode) . . . . . . . . . . 41 Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . 45 Display RAM filling order in static drive mode . . . 47 Discarded bits at the end of data transmission . . 47 Display RAM filling order in 1:2 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Display RAM filling order in 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Display RAM filling order in 1:6 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Display RAM filling order in 1:8 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Bank selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Example of the Bank-select command with multiplex drive mode 1:4 . . . . . . . . . . . . . . . . . . . 50 Control byte format . . . . . . . . . . . . . . . . . . . . . . . 52 Bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Definition of START and STOP conditions . . . . . 53 System configuration. . . . . . . . . . . . . . . . . . . . . . 54 Acknowledgement on the I2C-bus. . . . . . . . . . . . 54 I2C-bus protocol, write mode. . . . . . . . . . . . . . . . 56 I2C-bus protocol, read mode . . . . . . . . . . . . . . . . 56 Data transfer overview . . . . . . . . . . . . . . . . . . . . 57 SPI-bus write example . . . . . . . . . . . . . . . . . . . . 58 SPI-bus write example . . . . . . . . . . . . . . . . . . . . 58 SPI-bus read example. . . . . . . . . . . . . . . . . . . . . 59 Device protection diagram for PCF8537AH . . . . 60 Device protection diagram for PCF8537BH . . . . 60 LCD voltage variation with respect to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typical IDD1 with respect to temperature . . . . . . . 65 Typical IDD2 with respect to temperature . . . . . . . 65 Typical IDD(LCD) with respect to temperature . . . . 66 Driver timing waveforms . . . . . . . . . . . . . . . . . . . 67 RESET timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 I2C-bus timing waveforms . . . . . . . . . . . . . . . . . . 68 SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Package outline SOT357-1 (TQFP64) . . . . . . . . 70 Temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 80 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Commands of PCF8537 . . . . . . . . . . . . . . . . . . 7 8.1.1 Command: Initialize . . . . . . . . . . . . . . . . . . . . . 8 8.1.2 Command: OTP-refresh . . . . . . . . . . . . . . . . . . 8 8.1.3 Command: Oscillator-ctrl . . . . . . . . . . . . . . . . . 8 8.1.3.1 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.3.2 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . 9 8.1.3.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1.4 Command: Charge-pump-ctrl . . . . . . . . . . . . . . 9 8.1.5 Command: Temp-msr-ctrl . . . . . . . . . . . . . . . . 10 8.1.6 Command: Temp-comp . . . . . . . . . . . . . . . . . 10 8.1.7 Command: Set-VPR . . . . . . . . . . . . . . . . . . . . 11 8.1.8 Command: Display-enable . . . . . . . . . . . . . . . 11 8.1.9 Command: Set-MUX-mode . . . . . . . . . . . . . . 12 8.1.10 Command: Set-bias-mode . . . . . . . . . . . . . . . 12 8.1.11 Command: Load-data-pointer. . . . . . . . . . . . . 12 8.1.12 Command: Frame-frequency . . . . . . . . . . . . . 13 8.1.12.1 Timing and frame frequency . . . . . . . . . . . . . . 14 8.1.13 Command: Bank-select . . . . . . . . . . . . . . . . . 14 8.1.14 Command: Write-RAM-data . . . . . . . . . . . . . . 14 8.1.15 Command: Temp-read . . . . . . . . . . . . . . . . . . 15 8.1.16 Command: Invmode_ctrl . . . . . . . . . . . . . . . . 15 8.1.17 Command: Temp-filter . . . . . . . . . . . . . . . . . . 16 8.2 Start-up and shut-down. . . . . . . . . . . . . . . . . . 17 8.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 17 8.2.2 RESET pin function . . . . . . . . . . . . . . . . . . . . 18 8.2.3 Recommended start-up sequences . . . . . . . . 18 8.2.4 Recommended sequences to enter power-down mode . . . . . . . . . . . . . . . . . . . . . 20 8.3 Possible display configurations . . . . . . . . . . . 23 8.4 LCD supply voltage. . . . . . . . . . . . . . . . . . . . . 25 8.4.1 External VLCD supply . . . . . . . . . . . . . . . . . . . 25 8.4.2 Internal VLCD generation . . . . . . . . . . . . . . . . . 25 8.4.3 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4.3.1 Charge pump configuration . . . . . . . . . . . . . . 26 8.4.3.2 Charge pump driving capability . . . . . . . . . . . 26 8.4.4 Temperature measurement and temperature compensation of VLCD . . . . . . . . . . . . . . . . . . 28 8.4.4.1 Temperature readout . . . . . . . . . . . . . . . . . . . 8.4.4.2 Temperature adjustment of the VLCD . . . . . . . 8.4.5 LCD voltage selector . . . . . . . . . . . . . . . . . . . 8.4.5.1 Electro-optical performance . . . . . . . . . . . . . . 8.4.6 LCD drive mode waveforms. . . . . . . . . . . . . . 8.4.6.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 8.4.6.2 1:2 multiplex drive mode . . . . . . . . . . . . . . . . 8.4.6.3 1:4 multiplex drive mode . . . . . . . . . . . . . . . . 8.4.6.4 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 8.4.6.5 1:8 multiplex drive mode . . . . . . . . . . . . . . . . 8.5 Backplane and segment outputs . . . . . . . . . . 8.5.1 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 8.5.1.1 1:8 multiplex drive mode . . . . . . . . . . . . . . . . 8.5.1.2 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 8.5.1.3 1:4 multiplex drive mode . . . . . . . . . . . . . . . . 8.5.1.4 1:2 multiplex drive mode . . . . . . . . . . . . . . . . 8.5.1.5 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Segment outputs . . . . . . . . . . . . . . . . . . . . . . 8.5.2.1 Static, 1:8, 1:4, 1:2 multiplex drive mode . . . . 8.5.2.2 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 8.6 Display controller . . . . . . . . . . . . . . . . . . . . . . 8.7 Display register . . . . . . . . . . . . . . . . . . . . . . . 8.8 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.2 RAM filling in static drive mode . . . . . . . . . . . 8.8.3 RAM filling in 1:2 multiplex drive mode . . . . . 8.8.4 RAM filling in 1:4 multiplex drive mode . . . . . 8.8.5 RAM filling in 1:6 multiplex drive mode . . . . . 8.8.6 RAM filling in 1:8 multiplex drive mode . . . . . 8.9 Bank selection . . . . . . . . . . . . . . . . . . . . . . . . 8.9.1 Input bank selection . . . . . . . . . . . . . . . . . . . . 8.9.2 Output bank selection . . . . . . . . . . . . . . . . . . 9 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Control byte . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 I2C-bus interface characteristics (PCF8537AH) . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 START and STOP conditions. . . . . . . . . . . . . 9.2.3 System configuration . . . . . . . . . . . . . . . . . . . 9.2.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 9.2.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.7 I2C-bus slave address . . . . . . . . . . . . . . . . . . 9.2.8 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 9.2.9 Data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 SPI-bus interface (PCF8537BH) . . . . . . . . . . 9.3.1 Data transmission . . . . . . . . . . . . . . . . . . . . . 9.3.2 Data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 30 31 33 34 34 35 37 38 40 42 42 42 42 42 42 43 43 43 43 44 44 44 46 47 47 48 48 49 50 50 51 52 52 53 53 53 53 54 54 55 55 55 56 57 57 58 continued >> PCF8537 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 May 2012 © NXP B.V. 2012. All rights reserved. 81 of 82 PCF8537 NXP Semiconductors Industrial LCD driver for multiplex rates up to 1:8 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 22 23 24 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information. . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 61 62 67 70 71 71 71 71 72 72 74 75 76 77 77 77 77 78 78 79 80 81 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 31 May 2012 Document identifier: PCF8537