HYNIX HC2509C

HC2509C
March 1999
HC2509C
General Description
Features
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Phase-Locked Loop Clock Distribution for
Synchronous DRAM Applications
Supports PC-100 and Meets “PC100 SDRAM
registered DIMM Specification Rev. 1.2”
Distributes One Clock Input to One Bank of Five
and One Bank of Four Outputs
No External RC Network Required
External Feedback (FBIN) Pin is Used to
Synchronize the Outputs to the Clock Input
Separate Output Enable for Each Output Bank
Operates at 3.3 V Vcc
125 MHz Maximum Frequency
On-chip Series Damping Resistors
Support Spread Spectrum Clock(SSC)
Synthesizers
ESD Protection Exceeds 3000 V per MIL-STD883, Method 3015 ; Exceeds 350 V Using
Machine
Model ( C = 200 pF, R = 0 )
Latch-Up Performance Exceeds 400 mA per
JESD 17
Packaged in Plastic 24-Pin Thin Shrink SmallOutline Package
Pin Configuration
TSSOP 24 PACKAGE
(TOP VIEW)
AGND
1
24
CLK
Vcc
2
23
AVcc
1Y0
3
22
Vcc
2Y0
The HC2509C is a low-skew, low jitter, phase-locked
loop(PLL) clock driver, distributing high frequency
clock signals for SDRAM.
The HC2509C operates at 3.3V Vcc and provides
integrated series-damping resistors that make it ideal
for driving point-to-point loads. The propagation delay
from the CLK input to any clock output is nearly zero.
One bank of five outputs and one bank of four outputs
provide nine low-skew and low-jitter clocks. Each
bank of outputs can be enabled or disabled
separately via the control inputs (1G and 2G). Output
signal duty cycles are adjusted to 50 percent,
independent of the duty cycle at CLK.
The HC2509C is specially designed to interface with
high speed SDRAM applications in the range of
25MHz to 125MHz and includes an internal RC
network which provides excellent jitter characteristics
and eliminates the needs for external components.
For the test purpose, the PLL can be bypassed by
strapping AVcc to ground.
The HC2509C is characterized for operation from 0°C
to 85°C.
Function Table
1Y1
4
21
1Y2
5
20
2Y1
GND
6
19
GND
GND
7
18
GND
1Y3
8
17
2Y2
X
X
1Y4
9
16
2Y3
L
L
Vcc
10
15
Vcc
L
H
1G
11
14
2G
H
L
FBOUT
12
13
FBIN
H
H
INPUTS
1G
1
2G
OUTPUTS
1Y
2Y
(0:4)
(0:3)
L
L
L
L
H
L
L
H
H
L
H
H
H
H
L
H
H
H
H
H
CLK
FBOUT
HC2509C
March 1999
Functional Block Diagram
1G
11
3
4
5
8
9
2G
20
17
AVcc
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
24
16
PLL
FBIN
1Y1
14
21
CLK
1Y0
2Y3
13
12
23
2
FBOUT
HC2509C
March 1999
Table 1. Pin Description
Pin
Name
Pin No.
Type
CLK
24
I
Clock Input. CLK provides the reference signal to the internal PLL.
FBIN
13
I
Feedback Input. FBIN provides the feedback signal to the internal PLL.
IG
11
I
Output Bank Enable. When 1G is high, all outputs 1Y(0:4) are enabled.
When 1G is low, Outputs 1Y(0:4) are disabled to a logic-low state.
2G
14
I
Output Bank Enable. When 2G is high, all outputs 2Y(0:3) are enabled.
When 2G is low, Outputs 2Y(0:3) are disabled to a logic-low state.
FBOUT
12
O
Feedback Output. FBOUT completes the feedback loop of the PLL by being
wired to FBIN.
1Y(0:4)
3,4,5,8,9
O
Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output
has an embedded series-damping resistor.
2Y(0:3)
16,17,
20,21
O
Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output
has an embedded series-damping resistor.
Functional Description
23
Power
Analog Power Supply. AVcc provides the power reference for the analog
circuitry. AVcc can be also used to bypass the PLL for the test purpose.
When AVcc is strapped to ground, PLL is bypassed and CLK is buffered directly
to the device outputs.
AGND
1
Ground
Analog Ground. AGND provides the ground reference for the analog circuitry.
Vcc
2,10,15,22
Power
Power Supply
GND
6,7,18,19
Ground
Ground
AVcc
Table 2. Absolute Maximum Ratings Over Operating Free-air Temperature
Range
Symbols
Parameter
Value
Unit
Vcc
Supply Voltage Range
-0.5 to 4.6
V
VI
Input Voltage Range
-0.5 to 6.5
V
Vo
Voltage Range applied to any input in the high or
low state
-0.5 to
Vcc+0.5
V
IIK
Input Clamp Current
±50
mA
IOK
Output Clamp Current
±50
mA
Io
Continuous Output Current
±50
mA
PMAX
Maximum Power Dissipaiton
0.7
W
Tstg
Storage Temperature Range
-65 to 150
°C
3
Conditions
VI <0 or VI >0
Vo<0 or Vo>
Vcc
Vo=0 to Vcc
HC2509C
March 1999
Table 3. Recommended Operating Conditions
Value
Min
Max
Symbol
Parameter
AVcc
Supply Voltage
High-level Input Voltage
Low-level Input Voltage
Input Voltage
High-level Output Current
Low-level Output Current
Operating Free-air Temperature
VIH
VIL
VI
IOH
IOL
TA
3
2
0
0
Unit
3.6
Condition
V
V
V
V
mA
mA
°C
0.8
Vcc
-12
12
85
Table 4. Electrical Characteristics Over Recommended Operating
Free-air Temperature Range
Symbol
Min
Value
Typ
VIK
Max
Vcc (V)
Test Conditions
V
II = -18mA
IOH = -100µA
IOH = -12 mA
IOH = -6 mA
IOL = 100µA
IOL = 12 mA
IOL = 6 mA
VI =Vcc or GND
VI =Vcc or GND, Io = 0
Ouputs: low or high
One input at Vcc - 0.6V, Other
Inputs at Vcc or GND
VI = Vcc or GND
Vo = Vcc or GND
II
0.2
0.8
0.55
±5
µA
3
Min to Max
3
3
Min to Max
3
3
3.6
ICC
10
µA
3.6
C
500
µA
3.3 to 3.6
pF
pF
3.3
3.3
VOH
-1.2
Unit
Vcc - 0.2
2.1
2.4
V
VOL
Ci
Co
V
4
6
Table 5.Timing Requirements Over Recommended Ranges of Supply Voltage
and Operating Free-air Temperature
Symbol
Parameter
fclock
Clock Frequency
Input Clock Duty Cycle
Stabilization Time♣
Value
Min
Max
25
40
125
60
1
♣ Time to obtain phase lock of its feedback signal to its reference signal.
4
Unit
MHz
%
ms
HC2509C
March 1999
Table 6. Switching Characteristics Over Recommended Ranges of Supply
Voltage and Operating Free-air Temperature.(CL=30pF) (see Figure1 and 2) =
Parameter
From(Input)
tphase error ♣
66MHz < CLKIN↑<
100MHz
CLKIN↑ = 100MHz
(normalized)
tsk
Any Y of FBOUT
Jitter(pk-pk)
CLKIN > 66MHz
Duty Cycle
TO(Output)
CLKIN > 66MHz
tr
tf
Vcc = 3.3V
±0.165V
Min Typ Max
Vcc =
3.3V±0.3V
Unit
Min Typ Max
FBIN↑
-150
-150
ps
FBIN↑
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
-50
50
ps
200
ps
-100
100
ps
45
55
%
ns
1.3
1.9
0.8
2.1
1.7
2.5
1.2
2.7
ns
=These parameters are not production tested.
♣ Phase error does not include jitter.
Figure 1. Load Circuit and Voltage Waveforms
3V
From Output Under Test
50% Vcc
Input
30pF
0V
tpd
500§Ù
VOH
2V
2V
50% Vcc
0.4V
0.4V
VOL
Output
tr
Load Circuit For Outputs
tf
Voltage Waveforms
Propagation Delay Times
Notes: 1. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 100MHz, Zo
=50Ω, tr =1.2ns, tf=1.2ns
2.The outputs are measured one at a time with one
transition per measurement.
5
HC2509C
March 1999
Figure 2. Phase Error and Skew Calculations
CLKIN
FBIN
t phase error
Any Y
Any Y
tSK
FBOUT
Any Y
tSK
6