DATA SHEET MOS INTEGRATED CIRCUIT µPD43257B 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT Description The µPD43257B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM. Battery backup is available. And the µPD43257B has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD43257B is packed in 28-pin plastic DIP and 28-pin plastic SOP. Features • 32,768 words by 8 bits organization • Fast access time: 70, 85 ns (MAX.) • Low VCC data retention: 2.0 V (MIN.) • Two Chip Enable inputs: /CE1, CE2 Part number Access time ns (MAX.) µPD43257B-xxL 70, 85 Operating supply Operating ambient Supply current voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) Note 4.5 to 5.5 0 to 70 45 50 3 45 15 2 µPD43257B-xxLL Note TA ≤ 40 °C, VCC = 3.0 V Version X This Data sheet can be applied to the version X. This version is identified with its lot number. Letter X in the fifth character position in a lot number signifies version X. JAPAN D43257B X Lot number The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M10693EJ7V0DS00 (7th edition) Date Published June 2000 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 1992 µPD43257B Ordering Information Part number Package Access time At data retention Remark Note ns (MAX.) At standby 50 3 L version 15 2 LL version 50 3 L version 15 2 LL version µPD43257BCZ-70L 28-PIN PLASTIC DIP 70 µPD43257BCZ-85L (15.24 mm (600)) 85 µPD43257BCZ-70LL 70 µPD43257BCZ-85LL 85 µPD43257BGU-70L 28-PIN PLASTIC SOP 70 µPD43257BGU-85L (11.43 mm (450)) 85 µPD43257BGU-70LL 70 µPD43257BGU-85LL 85 Note TA ≤ 40 °C, VCC = 3.0 V 2 Supply current µA (MAX.) Data Sheet M10693EJ7V0DS00 µPD43257B Pin Configurations (Marking Side) /xxx indicates active low signal. 28-PIN PLASTIC DIP (15.24 mm (600)) [ µPD43257BCZ-xxL ] [ µPD43257BCZ-xxLL ] A14 1 28 VCC A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 CE2 A2 8 21 A10 A1 9 20 /CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1 : Chip Enable 1 CE2 : Chip Enable 2 /WE : Write Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin marking. Data Sheet M10693EJ7V0DS00 3 µPD43257B 28-PIN PLASTIC SOP (11.43 mm (450)) [ µPD43257BGU-xxL ] [ µPD43257BGU-xxLL ] A14 1 28 VCC A12 2 27 /WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 CE2 A2 8 21 A10 A1 9 20 /CE1 A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 GND 14 15 I/O4 A0 - A14 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1 : Chip Enable 1 CE2 : Chip Enable 2 /WE : Write Enable VCC : Power supply GND : Ground Remark Refer to Package Drawings for the 1-pin marking. 4 Data Sheet M10693EJ7V0DS00 µPD43257B Block Diagram A0 Address buffer A14 Row decoder I/O1 Input data controller I/O8 Memory cell array 262,144 bits Sense amplifier / Switching circuit Output data controller Column decoder Address buffer /CE1 CE2 /WE VCC GND Truth Table /CE1 CE2 /WE Mode I/O Supply current H × × Not selected High impedance ISB × L × L H H Read DOUT ICCA L H L Write DIN Remark × : VIH or VIL Data Sheet M10693EJ7V0DS00 5 µPD43257B Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Symbol Condition Rating VCC –0.5 –0.5 Note Note Unit to +7.0 V to VCC + 0.5 V Input / Output voltage VT Operating ambient temperature TA 0 to 70 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 50 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit 5.0 5.5 V VCC+0.5 V +0.8 V 70 °C MAX. Unit Supply voltage VCC 4.5 High level input voltage VIH 2.2 Low level input voltage VIL –0.3 Operating ambient temperature TA 0 Note Note –3.0 V (MIN.) (Pulse width: 50 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test conditions MIN. TYP. Input capacitance CIN VIN = 0 V 5 pF Input / Output capacitance CI/O VI/O = 0 V 8 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 6 Data Sheet M10693EJ7V0DS00 µPD43257B DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol µPD43257B-xxL Test condition MIN. Input leakage TYP. µPD43257B-xxLL MAX. MIN. TYP. Unit MAX. ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 µA ILO VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 –1.0 +1.0 µA mA current I/O leakage current CE2 = VIL or /WE = VIL Operating ICCA1 supply current /CE1 = VIL, CE2 = VIH, µPD43257B-70 45 45 Minimum cycle time, II/O = 0 mA µPD43257B-85 45 45 ICCA2 /CE1 = VIL, CE2 = VIH, II/O = 0 mA 10 10 ICCA3 /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, 10 10 3 3 mA µA II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V Standby ISB /CE1 = VIH or CE2 = VIL, supply current ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 1.0 50 0.5 15 ISB2 CE2 ≤ 0.2 V 1.0 50 0.5 15 High level VOH1 IOH = –1.0 mA 2.4 2.4 output voltage VOH2 IOH = –0.1 mA VCC–0.5 VCC–0.5 Low level VOL IOL = 2.1 mA 0.4 V 0.4 V output voltage Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time. Data Sheet M10693EJ7V0DS00 7 µPD43257B AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD43257B-70L, µPD43257B-85L, µPD43257B-70LL, µPD43257B-85LL ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.2 V 1.5 V Test points 1.5 V 0.8 V Output Waveform 1.5 V Test points 1.5 V Output Load AC characteristics with notes should be measured with the output load shown in Figure 1 and Figure 2. Figure 1 Figure 2 (tAA, tCO1, tCO2, tOH) (tLZ1, tLZ2, tHZ1, tHZ2, tWHZ, tOW) +5 V +5 V 1.8 kΩ 1.8 kΩ I/O (Output) I/O (Output) 990 Ω 100 pF CL 990 Ω Remark CL includes capacitance of the probe and jig, and stray capacitance. 8 Data Sheet M10693EJ7V0DS00 5 pF CL µPD43257B Read Cycle Parameter µPD43257B-70 Symbol MIN. MAX. 70 µPD43257B-85 MIN. Unit Condition MAX. Read cycle time tRC 85 ns Address access time tAA 70 85 ns /CE1 access time tCO1 70 85 ns CE2 access time tCO2 70 85 ns Output hold from address change tOH 10 10 ns /CE1 to output in low impedance tLZ1 10 10 ns CE2 to output in low impedance tLZ2 10 10 ns /CE1 to output in high impedance tHZ1 30 30 ns CE2 to output in high impedance tHZ2 30 30 ns Note 1 Note 2 Notes 1. See the output load shown in Figure 1. 2. See the output load shown in Figure 2. Remark These AC characteristics are in common regardless of package types and L, LL versions. Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 I/O (Output) Remark High impedance Data out In read cycle, /WE should be fixed to high level. Data Sheet M10693EJ7V0DS00 9 µPD43257B Write Cycle Parameter µPD43257B-70 Symbol MIN. MAX. µPD43257B-85 MIN. Unit MAX. Write cycle time tWC 70 85 ns /CE1 to end of write tCW1 50 70 ns CE2 to end of write tCW2 50 70 ns Address valid to end of write tAW 50 70 ns Address setup time tAS 0 0 ns Write pulse width tWP 55 65 ns Write recovery time tWR 0 0 ns Data valid to end of write tDW 30 35 ns Data hold time tDH 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 30 10 30 10 Note See the output load shown in Figure 2. Remark These AC characteristics are in common regardless of package types and L, LL versions. 10 Data Sheet M10693EJ7V0DS00 Condition ns ns Note µPD43257B Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance Data in tDH High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. ★ 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M10693EJ7V0DS00 11 µPD43257B Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. ★ 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark 12 Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M10693EJ7V0DS00 µPD43257B Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. ★ 2. When I/O pins are in the output state, therefore the input signals must not be applied to the output. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M10693EJ7V0DS00 13 µPD43257B Low VCC Data Retention Characteristics (TA = 0 to 70 °C) Parameter Symbol µPD43257B-xxL Test Condition MIN. Data retention supply voltage Data retention supply current MAX. MIN. TYP. /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 2.0 5.5 2.0 5.5 VCCDR2 CE2 ≤ 0.2 V 2.0 5.5 2.0 5.5 ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V ICCDR2 VCC = 3.0 V, CE2 ≤ 0.2 V Operation recovery time Unit MAX. VCCDR1 Chip deselection to data retention mode 0.5 20 Note1 0.5 7 Note2 0.5 20 Note1 0.5 7 Note2 V µA tCDR 0 0 ns tR 5 5 ms Notes 1. 3 µA (TA ≤ 40 °C) 2. 2 µA (TA ≤ 40 °C), 1 µA (TA ≤ 25 °C) 14 TYP. µPD43257B-xxLL Data Sheet M10693EJ7V0DS00 µPD43257B Data Retention Timing Chart (1) /CE1 Controlled tCDR ★ Data retention mode tR VCC 4.5 V /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE) can be in high impedance state. (2) CE2 Controlled tCDR ★ Data retention mode tR VCC 4.5 V VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE) can be in high impedance state. Data Sheet M10693EJ7V0DS00 15 µPD43257B ★ Package Drawings 28-PIN PLASTIC DIP (15.24 mm (600)) 28 15 1 14 A J K I L F D C N B R M M H G NOTES 1. Each lead centerline is located within 0.25 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS A 38.10 MAX. B 2.54 MAX. C 2.54 (T.P.) D 0.50±0.10 F 1.2 MIN. G 3.6±0.3 H 0.51 MIN. I 4.31 MAX. J 5.72 MAX. K L 15.24 (T.P.) 13.2 M 0.25 +0.10 −0.05 N 0.25 R 0 ∼ 15° P28C-100-600A1-2 16 Data Sheet M10693EJ7V0DS00 µPD43257B 28-PIN PLASTIC SOP (11.43 mm (450)) 28 15 detail of lead end P 1 14 A F H G I J S C D M N M L S B K E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 18.0 +0.6 −0.05 B 1.27 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.2±0.1 F 2.95 MAX. G 2.55±0.1 H 11.8±0.3 I 8.4±0.1 J 1.7±0.2 K 0.22±0.05 L M 0.7±0.2 0.12 N 0.10 P 3° +7° −3° P28GU-50-450A-4 Data Sheet M10693EJ7V0DS00 17 µPD43257B Recommended Soldering Conditions The following conditions must be met when soldering µPD43257B. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Types of Surface Mount Device µPD43257BGU-xxL : 28-PIN PLASTIC SOP (11.43 mm (450)) µPD43257BGU-xxLL : 28-PIN PLASTIC SOP (11.43 mm (450)) Please consult with our sales offices. Types of Through Hole Mount Device µPD43257BCZ-xxL : 28-PIN PLASTIC DIP (15.24 mm (600)) µPD43257BCZ-xxLL : 28-PIN PLASTIC DIP (15.24 mm (600)) Soldering process Wave soldering (only to leads) Soldering conditions Solder temperature : 260 °C or below, Flow time : 10 seconds or below Partial heating method Terminal temperature : 300 °C or below, Time : 3 seconds or below (Per one lead) Caution Do not jet molten solder on the surface of package. 18 Data Sheet M10693EJ7V0DS00 µPD43257B NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M10693EJ7V0DS00 19 µPD43257B • The information in this document is current as of June, 2000. The information is subject to change without notice. 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