LT1964 200mA, Low Noise, Low Dropout Negative Micropower Regulator FEATURES DESCRIPTION n The LT®1964 is a micropower low noise, low dropout negative regulator. The device is capable of supplying 200mA of output current with a dropout voltage of 340mV. Low quiescent current (30μA operating and 3μA shutdown) makes the LT1964 an excellent choice for battery-powered applications. Quiescent current is well controlled in dropout. n n n n n n n n n n n Low Noise: 30μVRMS (10Hz to 100kHz) Low Quiescent Current: 30μA Low Dropout Voltage: 340mV Output Current: 200mA Fixed Output Voltage: –5V Adjustable Output from –1.22V to – 20V Positive or Negative Shutdown Logic 3μA Quiescent Current in Shutdown Stable with 1μF Output Capacitor Stable with Aluminum, Tantalum, or Ceramic Capacitors Thermal Limiting Low Profile (1mm) ThinSOT™ and (0.75mm) 8-Pin 3mm × 3mm DFN Packages APPLICATIONS n n n Battery-Powered Instruments Low Noise Regulator for Noise-Sensitive Instrumentation Negative Complement to LT1761 Family of Positive LDOs Other features of the LT1964 include low output noise. With the addition of an external 0.01μF bypass capacitor, output noise is reduced to 30μVRMS over a 10Hz to 100kHz bandwidth. The LT1964 is capable of operating with small capacitors and is stable with output capacitors as low as 1μF. Small ceramic capacitors can be used without the necessary addition of ESR as is common with other regulators. Internal protection circuitry includes reverse output protection, current limiting, and thermal limiting. The device is available with a fixed output voltage of –5V and as an adjustable device with a –1.22V reference voltage. The LT1964 regulators are available in a low profile (1mm) ThinSOT and the low profile (0.75mm) 8-pin (3mm × 3mm) DFN packages. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 10Hz to 100kHz Output Noise –5V Low Noise Regulator 1μF VIN –5.4V TO –20V 10μF GND SHDN LT1964-5 IN VOUT 100μV/DIV BYP 30μVRMS 0.01μF OUT –5V AT 200mA 30μVRMS NOISE 1964 TA01a 1ms/DIV 1964 TA01b 1964fb 1 LT1964 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage ........................................................ ±20V OUT Pin Voltage (Note 11) ......................................±20V OUT to IN Differential Voltage (Note 11) ........ –0.5V, 20V ADJ Pin Voltage (with Respect to IN Pin) (Note 11)............. –0.5V, 20V BYP Pin Voltage (with Respect to IN Pin)..................................... ±20V SHDN Pin Voltage (with Respect to IN Pin) (Note 11)............. –0.5V, 35V SHDN Pin Voltage (with Respect to GND Pin) ..........................–20V, 15V Output Short-Circuit Duration .......................... Indefinite Operating Junction Temperature (E, I Grade) Range (Note 10) ............................... – 40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) SOT-23 Package................................................ 300°C PIN CONFIGURATION LT1964 LT1964-SD TOP VIEW TOP VIEW OUT 1 OUT 2 ADJ 3 SHDN 4 8 IN 9 5 OUT GND 1 7 IN IN 2 6 GND SHDN 3 4 ADJ 5 BYP S5 PACKAGE 5-LEAD PLASTIC SOT-23 TJMAX = 150°C, θJA ≈125°C/W to 250°C/W (NOTE 13) SEE THE APPLICATIONS INFORMATION SECTION DD PACKAGE 8-LEAD (3mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 40°C/W, θJC = 16°C/W (NOTE 13) EXPOSED PAD (PIN 9) IS IN, MUST BE SOLDERED TO PCB LT1964-BYP LT1964-5 TOP VIEW GND 1 TOP VIEW 5 OUT GND 1 IN 2 BYP 3 5 OUT IN 2 BYP 3 4 ADJ S5 PACKAGE 5-LEAD PLASTIC SOT-23 TJMAX = 150°C, θJA ≈125°C/W to 250°C/W (NOTE 13) SEE THE APPLICATIONS INFORMATION SECTION 4 SHDN S5 PACKAGE 5-LEAD PLASTIC SOT-23 TJMAX = 150°C, θJA ≈125°C/W to 250°C/W (NOTE 13) SEE THE APPLICATIONS INFORMATION SECTION ORDER INFORMATION LEAD FREE FINISH LT1964ES5-SD#PBF LT1964ES5-BYP#PBF LT1964ES5-5#PBF LT1964EDD#PBF TAPE AND REEL LT1964ES5-SD#TRPBF LT1964ES5-BYP#TRPBF LT1964ES5-5#TRPBF LT1964EDD#TRPBF PART MARKING* LTVX LTVY LTVZ LDVM LT1964IS5-SD#PBF LT1964IS5-BYP#PBF LT1964IS5-5#PBF LT1964IDD#PBF LT1964IS5-SD#TRPBF LT1964IS5-BYP#TRPBF LT1964IS5-5#TRPBF LT1964IDD#TRPBF LTVX LTVY LTVZ LDVM PACKAGE DESCRIPTION 5-Lead Plastic SOT-23 5-Lead Plastic SOT-23 5-Lead Plastic SOT-23 8-Lead (3mm × 3mm) Plastic DFN 5-Lead Plastic SOT-23 5-Lead Plastic SOT-23 5-Lead Plastic SOT-23 8-Lead (3mm × 3mm) Plastic DFN TEMPERATURE RANGE –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C –40°C to 125°C 1964fb 2 LT1964 ORDER INFORMATION LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1964ES5-SD LT1964ES5-SD#TR LTVX 5-Lead Plastic SOT-23 –40°C to 125°C LT1964ES5-BYP LT1964ES5-BYP#TR LTVY 5-Lead Plastic SOT-23 –40°C to 125°C LT1964ES5-5 LT1964ES5-5#TR LTVZ 5-Lead Plastic SOT-23 –40°C to 125°C LT1964EDD LT1964EDD#TR LDVM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT1964IS5-SD LT1964IS5-SD#TR LTVX 5-Lead Plastic SOT-23 –40°C to 125°C LT1964IS5-BYP LT1964IS5-BYP#TR LTVY 5-Lead Plastic SOT-23 –40°C to 125°C LT1964IS5-5 LT1964IS5-5#TR LTVZ 5-Lead Plastic SOT-23 –40°C to 125°C LT1964IDD LT1964IDD#TR LDVM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS Regulated Output Voltage (Notes 3, 9) LT1964-5 VIN = –5.5V, ILOAD = –1mA –20V < VIN < –6V, –200mA < ILOAD < –1mA ADJ Pin Voltage (Notes 2, 3, 9) LT1964 Line Regulation Load Regulation Dropout Voltage VIN = VOUT(NOMINAL) (Notes 4, 5) GND Pin Current VIN = VOUT(NOMINAL) (Notes 4, 6) MIN TYP MAX l –4.925 –4.850 –5 –5 –5.075 –5.150 V V VIN = –2V, ILOAD = –1mA –20V < VIN < –2.8V, –200mA < ILOAD < –1mA l –1.202 –1.184 –1.22 –1.22 –1.238 –1.256 V V LT1964-5 LT1964 (Note 2) ΔVIN = –5.5V to –20V, ILOAD = –1mA ΔVIN = –2.8V to –20V, ILOAD = –1mA l l 15 1 50 12 mV mV LT1964-5 VIN = –6V, ΔILOAD = –1mA to –200mA VIN = –6V, ΔILOAD = –1mA to –200mA l 15 35 50 mV mV LT1964 VIN = –2.8V, ΔILOAD = –1mA to –200mA VIN = –2.8V, ΔILOAD = –1mA to –200mA l 2 7 15 mV mV 0.1 0.15 0.19 V V 0.15 0.20 0.25 V V 0.26 0.33 0.39 V V 0.34 0.42 0.49 V V 30 85 300 1.3 2.5 70 180 600 3 6 μA μA μA mA mA ILOAD = –1mA ILOAD = –1mA l ILOAD = –10mA ILOAD = –10mA l ILOAD = –100mA ILOAD = –100mA l ILOAD = –200mA ILOAD = –200mA l ILOAD = 0mA ILOAD = –1mA ILOAD = –10mA ILOAD = –100mA ILOAD = –200mA l l l l l UNITS 1964fb 3 LT1964 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Output Voltage Noise COUT = 10μF, CBYP = 0.01μF, ILOAD = –200mA, BW = 10Hz to 100kHz 30 ADJ Pin Bias Current (Notes 2, 7) 30 100 nA Minimum Input Voltage (Note 12) ILOAD = –200mA LT1964-BYP LT1964-SD l l –1.9 –1.6 –2.8 –2.2 V V Shutdown Threshold VOUT = Off to On (Positive) VOUT = Off to On (Negative) VOUT = On to Off (Positive) VOUT = On to Off (Negative) l l l l 1.6 –1.9 0.8 –0.8 2.1 –2.8 V V V V –1 ±0.1 6 –3 1 15 –9 μA μA μA 3 10 μA 46 54 dB 350 mA mA SHDN Pin Current (Note 8) VSHDN = 0V VSHDN = 15V VSHDN = –15V l Quiescent Current in Shutdown VIN = –6V, VSHDN = 0V Ripple Rejection VIN – VOUT = –1.5V(Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = –200mA Current Limit VIN = –6V, VOUT = 0V VIN = VOUT(NOMINAL) –1.5V, ΔVOUT = 0.1V l VIN = 20V, VOUT, VADJ, VSHDN = Open Circuit l Input Reverse Leakage Current Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime Note 2: The LT1964 (adjustable version) is tested and specified for these conditions with the ADJ pin connected to the OUT pin. Note 3: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification will not apply for all possible combinations of input voltage and output current. When operating at maximum input voltage, the output current range must be limited. When operating at maximum output current, the input voltage range must be limited. Note 4: To satisfy requirements for minimum input voltage, the LT1964 (adjustable version) is tested and specified for these conditions with an external resistor divider (two 249k resistors) for an output voltage of –2.44V. The external resistor divider will add a 5μA DC load on the output. Note 5: Dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. In dropout, the output voltage will be equal to: (VIN + VDROPOUT). Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current source load. This means the device is tested while operating in its dropout region. This is the worst-case GND pin current. The GND pin current will decrease slightly at higher input voltages. 0.25 –0.25 μVRMS 220 1 mA Note 7: ADJ pin bias current flows out of the ADJ pin. Note 8: Positive SHDN pin current flows into the SHDN pin. SHDN pin current is included in the GND pin current specification. Note 9: For input-to-output differential voltages greater than 7V, a 50μA load is needed to maintain regulation. Note 10: The LT1964 is tested and specified under pulse load conditions such that TJ ≅ TA. The LT1964E is tested at TA = 25°C. Performance at –40°C to 125°C is assured by design, characterization and correlation with statistical process controls. The LT1964I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 11: A parasitic diode exists internally on the LT1964 between the OUT, ADJ and SHDN pins and the IN pin. The OUT, ADJ and SHDN pins cannot be pulled more than 0.5V more negative than the IN pin during fault conditions, and must remain at a voltage more positive than the IN pin during operation. Note 12: For the LT1964-BYP, this specification accounts for the operating threshold of the SHDN pin, which is tied to the IN pin internally. For the LT1964-SD, the SHDN threshold must be met to ensure device operation. Note 13: Actual thermal resistance (θJA) junction to ambient will be a function of board layout. See the Thermal Considerations section in the Applications Information. 1964fb 4 LT1964 TYPICAL PERFORMANCE CHARACTERISTICS Guaranteed Dropout Voltage 450 450 400 TJ = 125°C 350 300 250 TJ = 25°C 200 150 Dropout Voltage 500 = TEST POINT 450 400 TJ ≤ 125°C DROPOUT VOLTAGE (mV) 500 DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) Typical Dropout Voltage 500 350 300 250 TJ ≤ 25°C 200 150 350 250 IL = –100mA 200 IL = –50mA 150 100 100 50 50 50 0 0 –40 –80 –120 –160 OUTPUT CURRENT (mA) –200 0 –40 –80 –120 –160 OUTPUT CURRENT (mA) –50 VIN = –6V RL = 250k (∞ FOR LT1964-5) IL = –5μA (0 FOR LT1964-5) –20 –15 –10 VSHDN = 0V –5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) IL = –1mA 100 125 125 –5.06 –5.03 –5.00 –4.97 –1.230 –1.225 –1.220 –1.215 –4.94 –1.210 –4.91 –1.205 –4.88 –50 –25 IL = –1mA –1.235 ADJ PIN VOLTAGE (V) OUTPUT VOLTAGE (V) –25 100 –1.240 –5.09 VSHDN = VIN 0 25 50 75 TEMPERATURE (°C) LT1964 ADJ Pin Voltage –5.12 –30 –25 1964 G03 LT1964-5 Output Voltage –35 IL = –1mA 1964 G02 Quiescent Current –40 IL = –10mA 0 –50 –200 1964 G01 –45 IL = –200mA 300 100 0 QUIESCENT CURRENT (μA) 400 0 25 50 75 TEMPERATURE (°C) 100 125 –1.200 –50 –25 0 25 50 75 TEMPERATURE (°C) 1964 G05 100 125 1964 G06 1964 G04 LT1964-5 Quiescent Current –40 QUIESCENT CURRENT (μA) –35 VSHDN = VIN –30 –25 –20 –15 –10 VSHDN = 0V –5 0 –3.0 TJ = 25°C RL = 250k IL = –5μA –35 QUIESCENT CURRENT (μA) TJ = 25°C RL = ∞ –30 –25 –20 –15 –10 –0 0 TJ = 25°C VSHDN = VIN *FOR VOUT = –5V –2.5 –2.0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 INPUT VOLTAGE (V) –1.5 RL = 100 IL = –50mA* –1.0 1964 G08 0 RL = 25 IL = –200mA* RL = 50 IL = –100mA* RL = 500 IL = –10mA* –0.5 VSHDN = 0V –5 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 INPUT VOLTAGE (V) VSHDN = VIN GND PIN CURRENT (mA) –40 –0 LT1964-5 GND Pin Current LT1964 Quiescent Current 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 INPUT VOLTAGE (V) 1964 G09 1964 G07 1964fb 5 LT1964 TYPICAL PERFORMANCE CHARACTERISTICS LT1964 GND Pin Current TJ = 25°C; VSHDN = VIN; *FOR VOUT = –1.22V VIN = VOUT(NOMINAL) – 1V 2.0 –2.0 RL = 12.2Ω IL = –100mA* –1.5 –1.0 RL = 24.4Ω IL = –50mA* –0.5 RL = 122Ω IL = –10mA* 0 –2.5 TJ = 25°C –2.0 TJ = 125°C –1.5 –1.0 0 SHDN Pin Input Current 0 –40 –80 –120 –160 OUTPUT CURRENT (mA) SHDN PIN INPUT CURRENT (μA) SHDN PIN INPUT CURRENT (μA) –1.0 4 2 0 –2 –4 –6 –8 8 10 1964 G13 ON –25 0 25 50 75 TEMPERATURE (°C) 125 ADJ Pin Bias Current –70 VIN = –15V POSITIVE CURRENT FLOWS INTO THE PIN 9 –60 6 VSHDN = 15V 3 0 VSHDN = –15V –3 –6 –9 –50 100 1964 G12 SHDN Pin Input Current TJ = 25°C POSITIVE CURRENT FLOWS INTO THE PIN OFF –0.5 –2.5 –50 –200 12 –10 –10 –8 –6 –4 –2 0 2 4 6 SHDN PIN VOLTAGE (V) 0 1964 G11 10 6 0.5 –2.0 1964 G10 8 1.0 –1.5 –0.5 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 INPUT VOLTAGE (V) ON 1.5 TJ = –50°C –3.0 SHDN PIN VOLTAGE (V) RL = 6.1Ω IL = –200mA* ADJ PIN BIAS CURRENT (nA) GND PIN CURRENT (mA) 2.5 –3.5 –2.5 0 SHDN Pin Thresholds GND Pin Current vs ILOAD –4.0 GND PIN CURRENT (mA) –3.0 –50 –40 –30 –20 –10 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1964 G14 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1964 G15 1964fb 6 LT1964 TYPICAL PERFORMANCE CHARACTERISTICS Current Limit Current Limit –600 ΔVOUT = 100mV VIN = –7V VOUT = 0V –400 –300 –200 –100 –400 –300 –200 –100 –4 –8 –12 –16 INPUT/OUTPUT DIFFERENTIAL (V) 0 –50 –20 –25 0 25 50 75 TEMPERATURE (°C) 1964 G16 MINIMUM INPUT VOLTAGE (V) RIPPLE REJECTION (dB) VIN = VOUT(NOMINAL) – 1V + 0.5VP-P RIPPLE AT f = 120Hz IL = –200mA 54 52 50 48 46 44 –50 –25 0 25 50 75 TEMPERATURE (°C) 40 100 125 1964 G19 COUT = 10μF 30 20 100 0 125 LT1964-BYP Minimum Input Voltage 60 56 50 COUT = 1μF 10 100 1k 10k FREQUENCY (Hz) 100k LT1964, LT1964-SD Minimum Input Voltage –3.0 –3.0 –2.5 –2.5 –2.0 IL = –200mA –1.5 IL = –1mA –1.0 –0.5 0 –50 NOTE: THE MINIMUM INPUT VOLTAGE ACCOUNTS FOR THE OPERATING THRESHOLD OF THE SHDN PIN WHICH IS TIED TO THE IN PIN INTERNALLY –25 1M 1964 G18 1964 G17 Input Ripple Rejection 58 60 10 0 25 50 75 TEMPERATURE (°C) 100 125 1964 G20 MINIMUM INPUT VOLTAGE (V) 0 IL = –200mA VIN = VOUT(NOMINAL) – 1V + 50mVRMS RIPPLE CBYP = 0 70 RIPPLE REJECTION (dB) –500 CURRENT LIMIT (mA) CURRENT LIMIT (mA) –500 0 Input Ripple Rejection 80 –600 –2.0 IL = –200mA –1.5 IL = –1mA –1.0 –0.5 0 –50 NOTE: THE SHDN PIN THRESHOLD MUST BE MET TO ENSURE DEVICE OPERATION –25 0 25 50 75 TEMPERATURE (°C) 100 125 1964 G21 1964fb 7 LT1964 TYPICAL PERFORMANCE CHARACTERISTICS Load Regulation IL = –1mA TO –200mA LOAD REGULATION (mV) 25 LT1964-5 15 10 5 LT1964 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 140 10 120 CBYP = 1000pF CBYP = 100pF 1 CBYP = 0 0.1 CBYP = 0.01μF OUTPUT NOISE (μVRMS) OUTPUT NOISE SPECTRAL DENSITY (μV/√Hz) 30 20 RMS Output Noise vs Bypass Capacitor Output Noise Spectral Density LT1964-5 COUT = 10μF IL = –200mA f = 10Hz TO 100kHz 100 80 60 40 LT1964 COUT = 10μF IL = 200mA LT1964-5 LT1964 0 0.01 10 100 1k 10k FREQUENCY (Hz) 1964 G22 RMS Output Noise vs Load Current 20 10 100k 100 1k 10k CBYP (pF) 1964 G23 1964 G24 LT1964-5, 10Hz to 100kHz Output Noise, CBYP = 0 LT1964-5, 10Hz to 100kHz Output Noise, CBYP = 100pF 140 COUT = 10μF LT1964-5 OUTPUT NOISE (μVRMS) 120 100 VOUT 200μV/DIV 80 CBYP = 0 VOUT 100μV/DIV LT1964 60 40 LT1964-5 20 0 –0.01 LT1964 COUT = 10μF ILOAD = –200mA CBYP = 0.01μF –0.1 –1 –10 –100 LOAD CURRENT (mA) 1ms/DIV 1964 G26 COUT = 10μF ILOAD = –200mA 1ms/DIV 1964 G27 –1k 1964 G25 1964fb 8 LT1964 LT1964-5, 10Hz to 100kHz Output Noise, CBYP = 1000pF LT1964-5, 10Hz to 100kHz Output Noise, CBYP = 0.01μF VOUT 100μV/DIV VOUT 100μV/DIV COUT = 10μF ILOAD = –200mA 1964 G28 1ms/DIV COUT = 10μF ILOAD = –200mA LT1964-5, Transient Response, CBYP = 0.01μF 0.1 OUTPUT VOLTAGE DEVIATION (V) VIN = –6V CIN = 10μF COUT = 10μF 0.2 0 –0.1 –0.2 LOAD CURRENT (mA) LOAD CURRENT (mA) OUTPUT VOLTAGE DEVIATION (V) LT1964-5, Transient Response, CBYP = 0 0 –100 –200 0 400 800 1200 TIME (μs) 1600 1964 G29 1ms/DIV 2000 1964 G30 VIN = –6V CIN = 10μF COUT = 10μF 0.04 0.02 0 –0.02 –0.04 0 –100 –200 0 20 40 60 80 100 120 140 160 180 200 TIME (μs) 1964 G31 1964fb 9 LT1964 PIN FUNCTIONS ADJ (Adjustable Devices only): For the Adjustable LT1964, this is the Input to the Error Amplifier. The ADJ pin has a bias current of 30nA that flows out of the pin. The ADJ pin voltage is –1.22V referenced to ground, and the output voltage range is –1.22V to –20V. A parasitic diode exists between the ADJ pin and the input of the LT1964. The ADJ pin cannot be pulled more negative than the input during normal operation, or more than 0.5V more negative than the input during a fault condition. BYP: The BYP Pin is used to Bypass the Reference of the LT1964 to Achieve Low Noise Performance from the Regulator. A small capacitor from the output to this pin will bypass the reference to lower the output voltage noise. A maximum value of 0.01μF can be used for reducing output voltage noise to a typical 30μVRMS over a 10Hz to 100kHz bandwidth. If not used, this pin must be left unconnected. Exposed Pad (DFN Package Only): IN. Connect to IN (Pins 7, 8) at the PCB. GND: Ground. IN: Power is Supplied to the Device Through the Input Pin. A bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. In general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. A bypass capacitor in the range of 1μF to 10μF is sufficient. OUT: The Output Supplies Power to the Load. A minimum output capacitor of 1μF is required to prevent oscillations. Larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. A parasitic diode exists between the output and the input. The output cannot be pulled more negative than the input during normal operation, or more than 0.5V below the input during a fault condition. See the Applications Information section for more information on output capacitance and reverse output characteristics. SHDN: The SHDN Pin is used to put the LT1964 into a Low Power Shutdown State. The SHDN pin is referenced to the GND pin for regulator control, allowing the LT1964 to be driven by either positive or negative logic. The output of the LT1964 will be off when the SHDN pin is pulled within ±0.8V of GND. Pulling the SHDN pin more than –1.9V or +1.6V will turn the LT1964 on. The SHDN pin can be driven by 5V logic or open collector logic with a pull-up resistor. The pull-up resistor is required to supply the pull-up current of the open collector gate, normally several microamperes, and the SHDN pin current, typically 3μA out of the pin (for negative logic) or 6μA into the pin (for positive logic). If unused, the SHDN pin must be connected to VIN. The device will be shut down if the SHDN pin is open circuit. For the LT1964-BYP, the SHDN pin is internally connected to VIN. A parasitic diode exists between the SHDN pin and the input of the LT1964. The SHDN pin cannot be pulled more negative than the input during normal operation, or more than 0.5V below the input during a fault condition. 1964fb 10 LT1964 APPLICATIONS INFORMATION The LT1964 is a 200mA negative low dropout regulator with micropower quiescent current and shutdown. The device is capable of supplying 200mA at a dropout voltage of 340mV. Output voltage noise can be lowered to 30μVRMS over a 10Hz to 100kHz bandwidth with the addition of a 0.01μF reference bypass capacitor. Additionally, the reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. The low operating quiescent current (30μA) drops to 3μA in shutdown. In addition to the low quiescent current, the LT1964 incorporates several protection features which make it ideal for use in battery-powered systems. In dual supply applications where the regulator load is returned to a positive supply, the output can be pulled above ground by as much as 20V and still allow the device to start and operate. the formula in Figure 1. The value of R1 should be less than 250k to minimize errors in the output voltage caused by the ADJ pin bias current. Note that in shutdown the output is turned off and the divider current will be zero. Curves of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current vs Temperature appear in the Typical Performance Characteristics section. The adjustable device is tested and specified with the ADJ pin tied to the OUT pin and a 5μA DC load (unless otherwise specified) for an output voltage of –1.22V. Specifications for output voltages greater than –1.22V will be proportional to the ratio of the desired output voltage to –1.22V; (VOUT/–1.22V). For example, load regulation for an output current change of 1mA to 200mA is 2mV typical at VOUT = –1.22V. At VOUT = –12V, load regulation is: (–12V/–1.22V) • (2mV) = 19.6mV Adjustable Operation The adjustable version of the LT1964 has an output voltage range of –1.22V to –20V. The output voltage is set by the ratio of two external resistors as shown in Figure 1. The device servos the output to maintain the voltage at the ADJ pin at –1.22V referenced to ground. The current in R1 is then equal to –1.22V/R1 and the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 30nA at 25°C, flows through R2 out of the ADJ pin. The output voltage can be calculated using R1 GND + ADJ VIN LT1964 IN R2 OUT VOUT 1964 F01 VOUT = –1.22V(1 + R2 ) – (IADJ)(R2) R1 VADJ = –1.22V IADJ = 30nA AT 25°C OUTPUT RANGE = –1.22V TO –20V Figure 1. Adjustable Operation Bypass Capacitance and Low Noise Performance The LT1964 may be used with the addition of a bypass capacitor from VOUT to the BYP pin to lower output voltage noise. A good quality low leakage capacitor is recommended. This capacitor will bypass the reference of the LT1964, providing a low frequency noise pole. The noise pole provided by this bypass capacitor will lower the output voltage noise to as low as 30μVRMS with the addition of a 0.01μF bypass capacitor. Using a bypass capacitor has the added benefit of improving transient response. With no bypass capacitor and a 10μF output capacitor, a –10mA to –200mA load step will settle to within 1% of its final value in less than 100μs. With the addition of a 0.01μF bypass capacitor, the output will stay within 1% for the same –10mA to –200mA load step (see LT1964-5 Transient Response in the Typical Characteristics section). However, regulator start-up time is proportional to the size of the bypass capacitor. Higher values of output voltage noise may be measured if care is not exercised with regard to circuit layout and testing. Crosstalk from nearby traces can induce unwanted noise onto the output of the LT1964-X. 1964fb 11 LT1964 APPLICATIONS INFORMATION Extra consideration must be given to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients as shown in Figures 2 and 3. When used with a 5V regulator, a 16V 10μF Y5V capacitor can exhibit an effective value as low as 1μF to 2μF for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. 20 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF 0 CHANGE IN VALUE (%) The LT1964 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. A minimum output capacitor of 1μF with an ESR of 3Ω or less is recommended to prevent oscillations. The LT1964 is a micropower device and output transient response will be a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT1964, will increase the effective output capacitor value. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. The resulting voltages produced can cause appreciable X5R –20 –40 –60 Y5V –80 –100 0 2 4 14 8 6 10 12 DC BIAS VOLTAGE (V) 16 1964 F02 Figure 2. Ceramic Capacitor DC Bias Characteristics 40 20 CHANGE IN VALUE (%) Output Capacitance and Transient Response X5R 0 –20 –40 Y5V –60 –80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10μF –100 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1964 F03 Figure 3. Ceramic Capacitor Temperature Characteristics 1964fb 12 LT1964 APPLICATIONS INFORMATION amounts of noise, especially when a ceramic capacitor is used for noise bypassing. A ceramic capacitor produced Figure 4’s trace in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by power devices. The following tables list thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with one ounce copper. VOUT 1mV/DIV Table 1. SOT-23 Thermal Resistance COPPER AREA LT1964-5 COUT = 10μF CBYP = 0.01μF ILOAD = –200mA 100ms/DIV 1964 F04 Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor Thermal Considerations The power handling capability of the device will be limited by the maximum rated junction temperature (125°C). The power dissipated by the device will be made up of two components: 1. Output current multiplied by the input/output voltage differential: IOUT • (VIN – VOUT), and 2. Ground pin current multiplied by the input voltage: IGND • VIN The GND pin current can be found by examining the GND Pin Current curves in the Typical Performance Characteristics. Power dissipation will be equal to the sum of the two components listed above. The LT1964 series regulators have internal thermal limiting designed to protect the device during overload conditions. For continuous normal conditions the maximum junction temperature rating of 125°C must not be exceeded. It is important to give careful consideration to all sources of thermal resistance from junction to ambient. Additional heat sources mounted nearby must also be considered. TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 125°C/W 1000mm2 2500mm2 2500mm2 125°C/W 225mm2 2500mm2 2500mm2 130°C/W 100mm2 2500mm2 2500mm2 135°C/W 50mm2 2500mm2 2500mm2 150°C/W *Device is mounted on topside. Table 2. DFN Thermal Resistance COPPER AREA TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 40°C/W 1000mm2 2500mm2 2500mm2 45°C/W 225mm2 2500mm2 2500mm2 50°C/W 100mm2 2500mm2 2500mm2 62°C/W *Device is mounted on topside. The thermal resistance junction-to-case (θJC), measured at Pin 2, is 60°C/W. for the SOT-23 package and is 16°C/W measured at the backside of the exposed pad on the DFN package Calculating Junction Temperature Example: Given an output voltage of –5V, an input voltage range of –6V to –8V, an output current range of 0mA to –100mA, and a maximum ambient temperature of 50°C, what will the maximum junction temperature be? The power dissipated by the device will be equal to: 1964fb 13 LT1964 APPLICATIONS INFORMATION IOUT(MAX) • (VIN(MAX) – VOUT) + (IGND • VIN(MAX)) where, IOUT(MAX) = –100mA VIN(MAX) = –8V IGND at (IOUT = –100mA, VIN = –8V) = –2mA so, P = –100mA • (–8V + 5V) + (–2mA • –8V) = 0.32W The thermal resistance (junction to ambient) will be in the range of 125°C/W to 150°C/W for the SOT-23 package depending on the copper area. So the junction temperature rise above ambient will be approximately equal to: 0.32W • 140°C/W = 44.2°C The maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: TJMAX = 50°C + 44.2°C = 94.2°C Protection Features The LT1964 incorporates several protection features which make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device is protected against reverse input voltages and reverse output voltages. Current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. For normal operation, the junction temperature should not exceed 125°C. The output of the LT1964 can be pulled above ground without damaging the device. If the input is left open circuit or grounded, the output can be pulled above ground by 20V. For fixed voltage versions, the output will act like a large resistor, typically 500k or higher, limiting current flow to less than 40μA. For adjustable versions, the output will act like an open circuit, no current will flow into the pin. If the input is powered by a voltage source, the output will sink the short-circuit current of the device and will protect itself by thermal limiting. In this case, grounding the SHDN pin will turn off the device and stop the output from sinking the short-circuit current. Like many IC power regulators, the LT1964 series have safe operating area protection. The safe area protection activates at input-to-output differential voltages greater than –7V. The safe area protection decreases the current limit as the input-to-output differential voltage increases and keeps the power transistor inside a safe operating region for all values of forward input to-output voltage. The protection is designed to provide some output current at all values of input-to-output voltage up to the device breakdown. A 50μA load is required at input-to-output differential voltages greater than –7V. When power is first turned on, as the input voltage rises, the output follows the input, allowing the regulator to start up into very heavy loads. During start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. With a high input voltage, a problem can occur wherein removal of an output short will not allow the output voltage to fully recover. Other regulators, such as the LT1175, also exhibit this phenomenon, so it is not unique to the LT1964 series. The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations are immediately after the removal of a short-circuit or when the SHDN pin is pulled high after the input voltage has already been turned on. The load line for such a load may intersect the output current curve at two points. If this happens, there are two stable operating points for the regulator. With this double intersection, the input supply may need to be cycled down to zero and brought up again to make the output recover. 1964fb 14 LT1964 PACKAGE DESCRIPTION S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635) 0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 TYP 5 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.90 BSC 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 S5 TSOT-23 0302 REV B DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD) DFN 1203 0.200 REF 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ±0.05 4 0.25 ± 0.05 1 0.50 BSC 0.00 – 0.05 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 1964fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT1964 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1120 125mA Micropower Low Dropout Regulator with Comparator and Shutdown Includes 2.5V Reference and Comparator, VIN: 3.5V to 36V, IQ = 40μA, N8 Package LT1121 150mA Micropower Low Dropout Regulator VIN: 4.2V to 30V, IQ = 30μA; ThinSOT, S8 and MS8 Packages LT1129 700mA Micropower Low Dropout Regulator VIN: 4.5V to 30V, IQ = 50μA; DD and S8 Packages LT1175 800mA Negative Low Dropout Micropower Regulator VIN: 4.5V to 20V, IQ = 45μA, 0.26V Dropout Voltage, S8 and ThinSOT Packages LT1611 Inverting 1.4MHz Switching Regulator –5V at 150mA from 5V Input, ThinSOT Package LT1761 Series 100mA, Low Noise, Low Dropout Micropower Regulators VIN: 1.5V to 20V, IQ = 20μA, 20μVRMS Noise, ThinSOT Package LT1762 Series 150mA, Low Noise, LDO Micropower Regulators VIN: 1.5V to 20V, IQ = 25μA, 20μVRMS Noise, MS8 Package LT1763 Series 500mA, Low Noise, LDO Micropower Regulators VIN: 1.5V to 20V, IQ = 30μA, 20μVRMS Noise, S8 Package LT1764A 3A, Low Noise, Fast Transient Response LDO VIN: 1.5V to 20V, 40μVRMS Noise; DD and T5 Packages LT1931/LT1931A Inverting 1.2MHz/2.2MHz Switching Regulators –5V at 350mA from 5V Input, ThinSOT Package LT1962 300mA, Low Noise, LDO Micropower Regulator VIN: 1.5V to 20V, IQ = 30μA, 20μVRMS Noise, MS8 Package LT1963A 1.5A, Low Noise, Fast Transient Response LDO VIN: 1.5V to 20V, 40μVRMS Noise; DD, T5, S8 and ThinSOT Packages 1964fb 16 Linear Technology Corporation LT 0708 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001