LT1952/LT1952-1 - Single Switch Synchronous Forward Controller

LT1952/LT1952-1
Single Switch Synchronous
Forward Controller
DESCRIPTION
FEATURES
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Synchronous Rectifier Control for High Efficiency
Programmable Volt-Second Clamp
Output Power Levels from 25W to 500W
Low Current Start-Up
(LT1952: 460µA; VIN On/Off = 14.25V/8.75V)
(LT1952-1: 400µA; VIN On/Off = 7.75V/6.5V)
True PWM Soft-Start
Low Stress Short-Circuit Protection
Precision 107mV Current Limit Threshold
Adjustable Delay for Synchronous Timing
Accurate Shutdown Threshold with Programmable
Hysteresis
Programmable Slope Compensation
Programmable Leading Edge Blanking
Programmable Frequency (100kHz to 500kHz)
Synchronizable to an External Clock up to 1.5 • fOSC
Internal 1.23V Reference
2.5V External Reference
Current Mode Control
Small 16-Pin SSOP Package
The LT®1952/LT1952-1 are current mode PWM controllers
optimized to control the forward converter topology, using
one primary MOSFET. The LT1952/LT1952-1 provide
synchronous rectifier control, resulting in extremely
high efficiency. A programmable Volt-Second clamp
provides a safeguard for transformer reset that prevents
saturation. This allows a single MOSFET on the primary
side to reliably run at greater than 50% duty cycle for high
MOSFET, transformer and rectifier utilization. The devices
include soft-start for controlled exit from shutdown and
undervoltage lockout. A precision 107mV current limit
threshold, independent of duty cycle, combines with softstart to provide hiccup short-circuit protection. The LT1952
is optimized for micropower bootstrap start-up from high
input voltages. The LT1952-1 allows start-up from lower
input voltages. Programmable slope compensation and
leading edge blanking allow optimization of loop bandwidth
with a wide range of inductors and MOSFETs. Each device
can be programmed over a 100kHz to 500kHz frequency
range and the part can be synchronized to an external
clock. The error amplifier is a true op amp, allowing a wide
range of compensation networks. The LT1952/LT1952-1
are available in a small 16-pin SSOP package.
APPLICATIONS
Telecommunications Power Supplies
Industrial and Distributed Power
n Isolated and Non Isolated DC/DC Converters
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L, LT, LTC and LTM are registered trademarks and ThinSOT is a trademark of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
36V to 72V Input, 12V at 20A Semi-Regulated Bus Converter
40k
SUPPLY FROM BIAS
WINDING OF T1
16V
VREF
52.3k
10µF
Si7370
×2
100k
0.005Ω
SD_VSEC
13k
PH4840
×2
OC
ISENSE
LTC3900
FB
SYNC
SOUT
GND
ROSC
FG
T2
220pF
VOUT
12V
20A
16
14
VOUT (V)
Si7450
OUT
LT1952/
LT1952-1
12V Bus Converter
VOUT vs VIN
47µF
16V
X5R
×2
VIN
SS_MAXDC
340k
0.1µF
L1
PA1494.242
T1
PA0905
COMP
VIN
0.1µF
VIN
12
10
CG
SYNC
8
560Ω
PGND BLANK DELAY
36
42
48
54
VIN (V)
60
66
72
1952 TA01b
40k
40k
178k
1952 TA01
19521fe
1
LT1952/LT1952-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VIN (Note 8)................................................ –0.3V to 25V
SYNC, SS_MAXDC, SD_VSEC, ISENSE, OC.....– 0.3V to 6V
COMP, BLANK, DELAY................................ –0.3V to 3.5V
FB.................................................................– 0.3V to 3V
ROSC...................................................................... –50µA
VREF .....................................................................–10mA
Operating Junction Temperature Range (Notes 2, 5)
E-, I-Grades........................................–40°C to 125°C
MP-Grade........................................... –55°C to 125°C
Storage Temperature Range....................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
COMP
1
16 SOUT
FB
2
15 VIN
ROSC
3
14 OUT
SYNC
4
13 PGND
SS_MAXDC
5
12 DELAY
VREF
6
11 OC
SD_VSEC
7
10 ISENSE
GND
8
9
BLANK
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, qJA = 110°C/W, qJC = 40°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1952EGN#PBF
LT1952EGN#TRPBF
1952
16-Lead Plastic SSOP
–40°C to 125°C
LT1952IGN#PBF
LT1952IGN#TRPBF
1952I
16-Lead Plastic SSOP
–40°C to 125°C
LT1952MPGN#PBF
LT1952MPGN#TRPBF
1952
16-Lead Plastic SSOP
–55°C to 125°C
LT1952EGN-1#PBF
LT1952EGN-1#TRPBF
19521
16-Lead Plastic SSOP
–40°C to 125°C
LT1952IGN-1#PBF
LT1952IGN-1#TRPBF
1952I1
16-Lead Plastic SSOP
–40°C to 125°C
LT1952MPGN-1#PBF
LT1952MPGN-1#TRPBF
19521
16-Lead Plastic SSOP
–55°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT1952EGN
LT1952EGN#TR
1952
16-Lead Plastic SSOP
–40°C to 125°C
LT1952IGN
LT1952IGN#TR
1952I
16-Lead Plastic SSOP
–40°C to 125°C
LT1952MPGN
LT1952MPGN#TR
1952
16-Lead Plastic SSOP
–55°C to 125°C
LT1952EGN-1
LT1952EGN-1#TR
19521
16-Lead Plastic SSOP
–40°C to 125°C
LT1952IGN-1
LT1952IGN-1#TR
1952I1
16-Lead Plastic SSOP
–40°C to 125°C
LT1952MPGN-1
LT1952MPGN-1#TR
19521
16-Lead Plastic SSOP
–55°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
19521fe
2
LT1952/LT1952-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V,
SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 121k, DELAY = 121k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT = open,
unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Operational Input Voltage
I(VREF) = 0µA
VIN Quiescent Current
I(VREF) = 0µA, ISENSE = OC = Open
l
VIN OFF
25
V
5.2
6.5
mA
VIN Start-up Current (LT1952)
FB = 0V, SS_MAXDC = 0V (Notes 4, 9)
l
460
700
µA
VIN Start-up Current (LT1952-1)
FB = 0V, SS_MAXDC = 0V (Notes 4, 9)
l
400
575
µA
VIN Shutdown Current
SD_VSEC = 0V
240
350
µA
SD_VSEC Threshold
10V < VIN < 25V
1.261
1.32
1.379
V
SD_VSEC (ON) Current
SD_VSEC = SD_VSEC Threshold + 100mV
SD_VSEC (OFF) Current
SD_VSEC = SD_VSEC Threshold – 100mV
8.3
10
11.7
µA
l
0
µA
VIN ON (LT1952)
l
14.25
15.75
V
VIN OFF (LT1952)
l
8.75
9.25
V
VIN HYSTERESIS (LT1952)
VIN ON (LT1952-1)
l
E-, I-Grades
MP-Grade
3.75
l
l
5.5
6.75
V
7.75
7.75
6.5
8.13
8.3
6.82
V
V
V
VIN OFF (LT1952-1)
l
VIN HYSTERESIS (LT1952-1)
l
0.95
1.25
l
2.425
V
VREF
Output Voltage
I(VREF) = 0µA
2.5
2.575
Line Regulation
I(VREF) = 0µA, 10V < VIN < 25V
1
10
mV
V
Load Regulation
0µA < I(VREF) < 2.5mA
1
10
mV
165
200
240
kHz
80
440
100
500
18
120
560
kHz
kHz
kΩ
1.5
2.2
V
OSCILLATOR
Frequency: fOSC
ROSC = 178k, FB = 1V, SS_MAXDC = 1.84V
Minimum Programmable fOSC
Maximum Programmable fOSC
SYNC Input Resistance
ROSC = 365k, FB = 1V
ROSC = 64.9k, COMP = 2.5V, SD_VSEC = 2.64V
SYNC Switching Threshold
FB = 1V
SYNC Frequency/fOSC
FB = 1V (Note 7)
1.25
1.5
fOSC Line Reg
FB = 1V, ROSC = 178k; 10V < VIN < 25V,
SS_MAXDC = 1.84V
ROSC Pin voltage
0.05
0.33
VROSC
l
1
%/V
V
ERROR AMPLIFIER
FB Reference Voltage
10V < VIN < 25V, VOL + 0.2V < COMP < VOH – 0.2
FB Input Bias Current
FB = FB Reference Voltage
Open Loop Voltage Gain
VOL + 0.2V < COMP < VOH – 0.2
Unity Gain Bandwidth
(Note 6)
COMP Source Current
FB = 1V, COMP = 1.6V
COMP Sink Current
COMP Current (Disabled)
l
1.201
65
1.226
1.250
–75
–200
V
nA
85
dB
3
MHz
–4
–9
mA
COMP = 1.6V
4
10
FB = VREF , COMP = 1.6V
18
23
COMP High Level: VOH
FB = 1V, I(COMP) = –250µA
2.7
3.2
V
COMP Active Threshold
FB = 1V, SOUT Duty Cycle > 0 %
0.7
0.8
V
mA
28
µA
19521fe
3
LT1952/LT1952-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V,
SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 121k, DELAY = 121k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT =
open, unless otherwise specified.
PARAMETER
CONDITIONS
COMP Low Level: VOL
I(COMP) = 250µA
MIN
TYP
MAX
0.15
0.4
UNITS
V
197
220
243
mV
98
–8
–35
107
116
µA
µA
mV
–100
nA
CURRENT SENSE
ISENSE Maximum Threshold
COMP = 2.5V, FB = 1V
ISENSE Input Current (Duty Cycle = 0%)
ISENSE Input Current (Duty Cycle = 80%)
OC Threshold
COMP = 2.5V, FB = 1V (Note 4)
COMP = 2.5V, FB = 1V (Note 4)
COMP = 2.5V, FB = 1V
OC Input Current
(OC = 100mV)
–50
Default Blanking Time
COMP = 2.5V, FB = 1V, RBLANK = 40k (Note 10)
180
ns
Adjustable Blanking Time
COMP = 2.5V, FB = 1V, RBLANK = 120k
540
ns
1
V
VBLANK
SOUT DRIVER
SOUT Clamp Voltage
I(GATE) = 0µA, COMP = 2.5V, FB = 1V
SOUT Low Level
I(GATE) = 25mA
SOUT High Level
I(GATE) = –25mA, VIN = 12V, COMP = 2.5V,
FB = 1V
VIN = 5V, SD_VSEC = 0V, SOUT = 1V
SOUT Active Pull-Off in Shutdown
SOUT to OUT (Rise) DELAY (tDELAY)
10.5
12
13.5
V
0.5
0.75
V
10
V
1
mA
COMP = 2.5V, FB = 1V (Note 10)
RDELAY = 120k
40
120
0.9
ns
ns
V
OUT Rise Time
FB = 1V, CL = 1nF (Notes 3, 6)
50
ns
OUT Fall Time
FB = 1V, CL = 1nF (Notes 3, 6)
30
ns
OUT Clamp Voltage
I(GATE) = 0µA, COMP = 2.5V, FB = 1V
OUT Low Level
I(GATE) = 20mA
I(GATE) = 200mA
I(GATE) = –20mA, VIN = 12V, COMP = 2.5V,
FB = 1V
I(GATE) = –200mA, VIN = 12V, COMP = 2.5V,
FB = 1V
VIN = 5V, SD_VSEC = 0V, OUT = 1V
VDELAY
OUT DRIVER
OUT High Level
OUT Active Pull-Off in Shutdown
OUT Max Duty Cycle
OUT Max Duty Cycle Clamp
COMP = 2.5V, FB = 1V, RDELAY = 10k
(fOSC = 200kHz), VIN = 10V
SD_VSEC = 1.4V, SS_MAXDC = VREF
COMP = 2.5V, FB = 1V, RDELAY = 10k
(fOSC = 200kHz), VIN = 10V
SD_VSEC = 1.32V, SS_MAXDC = 1.84V
SD_VSEC = 2.64V, SS_MAXDC = 1.84V
11.5
13
14.5
V
0.45
1.25
0.75
1.8
9.9
V
V
V
9.75
V
20
mA
83
90
63.5
25
72
33
%
80.5
41
%
%
19521fe
4
LT1952/LT1952-1
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). COMP = open, FB = 1.4V, ROSC = 178k, SYNC = 0V,
SS_MAXDC = VREF, VREF = 0.1µF, SD_VSEC = 2V, BLANK = 121k, DELAY = 121k, ISENSE = 0V, OC = 0V, OUT = 1nF, VIN = 15V, SOUT =
open, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
SS_MAXDC Low Level: VOL
I(SS_MAXDC) = 150µA, OC = 1V
0.2
V
SS_MAXDC Soft-Start Reset Threshold
Measured on SS_MAXDC
0.45
V
SS_MAXDC Active Threshold
FB = 1V, DC > 0%
0.8
V
SS_MAXDC Input Current (Soft-Start Pull-Down: Idis)
SS_MAXDC = 1V, SD_VSEC = 1.4V, OC = 1V
800
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1952/LT1952-1 are tested under pulsed load conditions
such that TJ ≈ TA. The LT1952EGN/LT1952EGN-1 are guaranteed to meet
performance specifications from 0°C to 125°C junction temperature.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LT1952IGN/LT1952IGN-1 are guaranteed
over the –40°C to 125°C operating junction temperature range and the
LT1952MPGN/LT1952MPGN-1 are tested and guaranteed over the full
–55°C to 125°C operating junction temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: Rise and Fall times are measured at 10% and 90% levels.
Note 4: Guaranteed by correlation to static test.
Note 5: Each IC includes over-temperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when over-temperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 6: Guaranteed but not tested.
Note 7: Maximum recommended SYNC frequency = 500kHz.
Note 8: In applications where the VIN pin is supplied via an external RC
network from a SYSTEM VIN > 25V, an external zener with clamp voltage
VIN ON(MAX) < VZ < 25V should be connected from the VIN pin to ground.
Note 9: VIN start-up current is measured at VIN = VIN ON – 0.25V and
scaled by x 1.18 (to correlate to worst case VIN start-up current at VIN ON).
Note 10: Timing for R = 40k derived from measurement with R = 240k.
19521fe
5
LT1952/LT1952-1
TYPICAL PERFORMANCE CHARACTERISTICS
1.25
500
245
1.23
1.22
1.21
1.20
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
VIN = 15V
450 SD_VSEC = 0V
230
VIN SHUTDOWN CURRENT (µA)
SWITCHING FREQUENCY (kHz)
1.24
FB VOLTAGE (V)
VIN Shutdown Current
vs Temperature
Switching Frequency
vs Temperature
FB Voltage vs Temperature
215
200
185
170
–25
50
25
0
75
TEMPERATURE (°C)
100
1952 G01
5.0
4.5
LT1952-1
300
4.0
250
50
25
0
75
TEMPERATURE (°C)
100
3.5
–50
125
–25
50
25
0
75
TEMPERATURE (°C)
100
1952 G04
1.6
LT1952 VIN TURN ON VOLTAGE
100
COMP (V)
12
LT1952-1 VIN ON
125
1952 G07
6
–50
125
RISENSE = 0k
1.2
LT1952 VIN TURN OFF VOLTAGE
50
25
0
75
TEMPERATURE (°C)
100
1.4
–25
0.8
0.6
0.2
LT1952-1 VIN OFF
50
25
0
75
TEMPERATURE (°C)
1.0
0.4
8
0mA PIN CURRENT AFTER
PART TURN ON
50
25
0
75
TEMPERATURE (°C)
COMP Active Threshold
vs Temperature
10
5
–25
1952 G06
14
VIN (V)
SD_VSEC PIN CURRENT (µA)
16
10
–25
1.27
1.22
–50
125
18
PIN CURRENT BEFORE
PART TURN ON
0
–50
1.32
VIN Turn ON/OFF Voltage
vs Temperature
15
125
1.37
1952 G05
SD_VSEC Pin Current
vs Temperature
100
1.42
5.5
VIN IQ (mA)
VIN STARTUP CURRENT (µA)
LT1952
–25
50
25
0
75
TEMPERATURE (°C)
1952 G03
OC = OPEN
6.0
400
–25
SD_VSEC Turn ON Threshold
vs Temperature
500
200
–50
200
100
–50
125
SD_VSEC TURN ON THRESHOLD (V)
6.5
550
350
250
VIN IQ vs Temperature
SD_VSEC = 1.4V
450
300
1952 G02
VIN Start-up Current
vs Temperature
600
350
150
155
–50
125
400
100
125
1952 G08
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1952 G09
19521fe
6
LT1952/LT1952-1
TYPICAL PERFORMANCE CHARACTERISTICS
12.5
FB = 1V
COMP = 1.6V
COMP SINK CURRENT (mA)
COMP SOURCE CURRENT (mA) • (–1)
12.5
COMP Sink Current
vs Temperature
10.0
7.5
CURRENT OUT OF PIN
5.0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
10.0
7.5
–25
50
25
0
75
TEMPERATURE (°C)
1952 G10
OC THRESHOLD
80
40
0
0
0.5
1.0
2.0
1.5
COMP (V)
210
0
–25
50
25
0
75
TEMPERATURE (°C)
100
100
125
TA = 25°C
20
10
0
125
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
1952 G15
Blank Duration vs Temperature
800
PRECISION OVERCURRENT THRESHOLD
INDEPENDENT OF DUTY CYCLE
110
BLANK DURATION (ns)
OC THRESHOLD (mV)
ISENSE MAX THRESHOLD (mV)
RSLOPE = 0W
RSLOPE = 470W
50
0
75
25
TEMPERATURE (°C)
1952 G14
120
195
–25
30
OC (Overcurrent) Threshold
vs Temperature
205
175
40
220
200
–50
3.0
2.5
225
TA = 25°C
COMP = 2.5V
10
1952 G12
COMP = 2.5V
RISENSE = 0k
1952 G13
185
20
ISENSE Pin Current (Out of Pin)
vs Duty Cycle
230
ISENSE Maximum Threshold
vs Duty Cycle (Programming
Slope Compensation)
215
30
0
–50
125
ISENSE PIN CURRENT (µA)
160
ISENSE MAX THRESHOLD (mV)
ISENSE MAX THRESHOLD (mV)
240
120
40
ISENSE Maximum Threshold
vs Temperature
TA = 25°C
RISENSE = 0k
200
100
FB = VREF
COMP = 1.6V
1952 G11
ISENSE Maximum Threshold
vs COMP
240
50
FB = 1.4V
COMP = 1.6V
5.0
–50
125
(Disabled) COMP Pin Current
vs Temperature
COMP PIN CURRENT (µA)
COMP Source Current
vs Temperature
100
90
RBLANK = 120k
600
400
200
RBLANK = 40k
RSLOPE = 1k
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
1952 G16
80
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1952 G17
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1952 G18
19521fe
7
LT1952/LT1952-1
TYPICAL PERFORMANCE CHARACTERISTICS
200
TA = 25°C
TA = 25°C
150
160
RDELAY = 120k
600
tDELAY (ns)
BLANK (ns)
800
240
tDELAY: SOUT Rise to OUT Rise
vs RDELAY
400
tDELAY (ns)
1000
tDELAY: SOUT Rise to OUT Rise
vs Temperature
BLANK Duration vs RBLANK
100
80
50
200
RDELAY = 40k
0
0
20
0
–50
60 80 100 120 140 160
RBLANK (k)
40
–25
50
25
0
75
TEMPERATURE (°C)
100
1952 G26
90
OUT MAX DUTY CYCLE CLAMP (%)
75
tf
50
90
80
25
0
TA = 25°C
SS_MAXDC = 2.5V
SD_VSEC = 1.4V
0
2000
1000
3000
4000
OUT LOAD CAPACITANCE (pF)
70
100
5000
200
300
fOSC (kHz)
400
1952 G20
2.32
SD_VSEC = 1.98V
40
30
20
1.60
SD_VSEC = 2.64V
1.84
SS_MAXDC (V)
SS_MAXDC Setting
vs fOSC (for OUT DC = 72%)
1952 G23
80
70
60
50
40
30
20
10
TA = 25°C
SS_MAXDC = 1.84V
fOSC = 200kHz
RDELAY = 10k
1.65
1.98
SD_VSEC (V)
2.64
2.31
SS_MAXDC Reset and Active
Thresholds vs Temperature
1.2
1.0
2.08
1.96
1.84
1.72
1.60
100
2.08
240
200
1952 G22
SS_MAXDC (mV)
SD_VSEC = 1.32V
70
50
160
120
RDELAY (k)
OUT: Max Duty Cycle CLAMP
vs SD_VSEC
0
1.32
500
TA = 25°C
SD_VSEC = 1.32V
2.20 RDELAY = 10k
SS_MAXDC (V)
OUT MAX DUTY CYCLE CLAMP (%)
90
60
80
1952 G21
OUT: Max Duty Cycle CLAMP
vs SS_MAXDC
TA = 25°C
fOSC = 200kHz
80 R
DELAY = 10k
40
1952 G27
OUT: Max Duty Cycle vs fOSC
100
OUT DUTY CYCLE (%)
OUT RISE/FALL TIME (ns)
100
TA = 25°C
tr
0
1952 G19
OUT Rise/Fall Time
vs OUT Load Capacitance
125
0
125
ACTIVE THRESHOLD
0.8
0.6
0.4
RESET THRESHOLD
0.2
200
300
fOSC (kHz)
400
500
1952 G24
0
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
1952 G25
19521fe
8
LT1952/LT1952-1
PIN FUNCTIONS
COMP (Pin 1): Output Pin of the Error Amplifier. The error
amplifier is an op amp, allowing various compensation
networks to be connected between the COMP pin and
FB pin for optimum transient response. The voltage on
this pin corresponds to the peak current of the external
FET. Full operating voltage range is between 0.8V and
2.5V corresponding to 0mV to 220mV at the ISENSE pin.
For applications using the 100mV OC pin for overcurrent
detection, typical operating range for the COMP pin is
0.8V to 1.6V. For isolated applications where COMP is
controlled by an opto-coupler, the COMP pin output drive
can be disabled with FB = VREF, reducing the COMP pin
current to (COMP – 0.7)/40k.
FB (Pin 2): Monitors the output voltage via an external
resistor divider and is compared with an internal 1.23V
reference by the error amplifier. FB connected to VREF
disables error amplifier output.
ROSC (Pin 3): A resistor to ground programs the operating
frequency of the IC between 100kHz and 500kHz. Nominal
voltage on the ROSC pin is 1.0V.
SYNC (Pin 4): Used to Synchronize the Internal Oscillator
to an External Signal. It is directly logic compatible and
can be driven with any signal between 10% and 90% duty
cycle. If unused, the pin can be left open or connected to
ground.
SS_MAXDC (Pin 5): External resistor divider from VREF
sets maximum duty cycle clamp (SS_MAXDC = 1.84V,
SD_VSEC = 1.32V gives 72% duty cycle). Capacitor on
SS_MAXDC pin in combination with external resistor
divider sets soft-start timing.
VREF (Pin 6): The output of an internal 2.5V reference which
supplies control circuitry in the IC. Capable of sourcing up
to 2.5mA drive for external use. Bypass to ground with a
0.1µF ceramic capacitor.
SD_VSEC (Pin 7): The SD_VSEC pin, when pulled below
its accurate 1.32V threshold, is used to turn off the IC
and reduce current drain from VIN. The SD_VSEC pin is
connected to system input voltage through a resistor
divider to define undervoltage lockout (UVLO) and to
provide a Volt-Second clamp on the OUT pin. A 10µA pin
current hysteresis allows external programming of UVLO
hysteresis.
GND (Pin 8): Analog Ground.
BLANK (Pin 9): A resistor to ground adjusts the extended
blanking period of the overcurrent and current sense
amplifier outputs during FET turn on—to prevent false
current limit trip. Increasing the resistor value increases
the blanking period.
ISENSE (Pin 10): The Current Sense Input for the Control
Loop. Connect this pin to the sense resistor in the source
of the external power MOSFET. A resistor in series with
the ISENSE pin programs slope compensation.
OC (Pin 11): An accurate 107mV threshold, independent
of duty cycle, for overcurrent detection and trigger of
soft-start. Connect this pin directly to the sense resistor
in the source of the external power MOSFET.
DELAY (Pin 12): A resistor to ground adjusts the delay
period between SOUT rising edge and OUT rising edge.
Used to maximize efficiency in forward converter applications by adjusting the control timing of secondary side
synchronous rectifier MOSFETs. Increasing the resistor
value increases the delay period.
PGND (Pin 13): Power Ground.
OUT (Pin 14): Drives the Gate of an N-channel MOSFET
between 0V and VIN with a maximum limit of 13V on
OUT pin set by an internal clamp. Active pull-off exists in
shutdown (see electrical specification).
VIN (Pin 15): Input Supply for the Part. It must be closely
decoupled to ground. An internal undervoltage lockout
threshold exists for VIN at approximately 14.25V on
and 8.75V off for the LT1952. The LT1952-1 has lower
undervoltage lockout thresholds set at 7.75V on and
6.5V off.
SOUT (Pin 16): Switched Output in Phase with OUT Pin.
Provides sync signal for control of secondary side FETs
in forward converter applications requiring highly efficient
synchronous rectification. SOUT is actively clamped to
12V. Active pull-off exists in shutdown (see electrical
specification).
19521fe
9
LT1952/LT1952-1
TIMING DIAGRAM
tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY
SOUT
OUT
SS_MAXDC
FAULTS TRIGGERING SOFT-START
VIN < 8.75V
OR
SD_VSEC < 1.32V (UVLO)
OR
OC > 107mV (OVERCURRENT)
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
0.2V
SOFT-START LATCH RESET:
SOFT-START
LATCH SET
VIN > 14.25V (> 8.75V IF LATCH SET BY OC)
AND
SD_VSEC > 1.32V
AND
OC < 107mV
AND
SS_MAXDC < 0.45V
1952 F01
Figure 1. Timing Diagram
BLOCK DIAGRAM
VIN
15
VINON
VINOFF
–
VREF
SS_MAXDC
6
5
0.45V
+
2.5V
LT1952-1
ISTART = 400µA
VIN ON = 7.75V
VIN OFF = 6.5V
+
VREF
>90%
SOFT-START CONTROL
–
R
SOURCE
2.5mA
Q
–
S
+
±50mA
1.23V
–
IHYST
10µA SD_VSEC = 1.32V
0µA SD_VSEC > 1.32V
–
ADAPTIVE
MAXIMUM
DUTY CYCLE
CLAMP
16 SOUT
12V
+
+
(TYPICAL 200kHz)
SD_VSEC 7
OSC
1.32V
ROSC 3
(100 TO 500)kHz
S
(LINEAR)
SLOPE COMP
8µA 0% DC
35µA 80% DC
RAMP
Q
ON
DELAY
DRIVER
±1A
R
13 PGND
SYNC 4
+
BLANK
(VOLTAGE)
ERROR AMPLIFIER
OVER
CURRENT
SENSE
–CURRENT+
–
13V
+
1.23V
14 OUT
0mV TO 220mV
107mV
–
LT1952
ISTART = 460µA
VIN ON = 14.25V
VIN OFF = 8.75V
START-UP
INPUT CURRENT (ISTART)
11 OC
10 ISENSE
2
1
8
FB
COMP
GND
9
12
DELAY BLANK
1952 BD
Figure 2. Block Diagram
19521fe
10
LT1952/LT1952-1
OPERATION
Introduction
The LT1952/LT1952-1 are current mode synchronous
PWM controllers optimized for control of the simplest
forward converter topology—using only one primary
MOSFET. The LT1952/LT1952-1 are ideal for 25W to 500W
power systems where very high efficiency and reliability,
low complexity and cost are required in a small space.
Key features of the LT1952/LT1952-1 include an adaptive
maximum duty cycle clamp for the single primary MOSFET.
An additional output signal is included for synchronous
rectifier control. A precision 107mV threshold senses
overcurrent conditions and triggers Soft-Start for low
stress short-circuit protection and control. The key
functions of the LT1952/LT1952-1 are shown in the Block
Diagram in Figure 2.
Part Start-up
In normal operation the SD_VSEC pin must exceed 1.32V
and the VIN pin must exceed 14.25V (7.75V LT1952-1) to
allow the part to turn on. This combination of pin voltages
allows the 2.5V VREF pin to become active, supplying the
LT1952/LT1952-1 control circuitry and providing up to
2.5mA external drive. SD_VSEC threshold can be used for
externally programming an undervoltage lockout (UVLO)
threshold on the system input voltage. Hysteresis on
the UVLO threshold can also be programmed since the
SD_VSEC pin draws 11µA just before part turn on and 0µA
after part turn on.
With the LT1952/LT1952-1 turned on, the VIN pin can drop
as low as 8.75V (6.5V LT1952-1) before part shutdown
occurs. This VIN pin hysteresis (5.5V LT1952; 1.25V
LT1952-1) combined with low 460µA (400µA LT1952-1)
start-up input current allows low power start-up using
a resistor/capacitor network from system VIN to supply
the VIN pin (Figure 3). The VIN capacitor value is chosen
to prevent VIN falling below its turn off threshold before
an auxiliary winding in the converter takes over supply
to the VIN pin.
Output Drivers
The LT1952/LT1952-1 have two outputs, SOUT and OUT.
The OUT pin provides a ±1A peak MOSFET gate drive
clamped to 13V. The SOUT pin has a ±50mA peak drive
clamped to 12V and provides sync signal timing for synchronous rectification control.
For SOUT and OUT turn on, a PWM latch is set at the start
of each main oscillator cycle. OUT turn on is delayed from
SOUT turn on by a time tDELAY (Figure 2). tDELAY is programmed using a resistor from the DELAY pin to ground
and is used to set the timing control of the secondary
synchronous rectifiers for optimum efficiency.
SOUT and OUT turn off at the same time each cycle by
one of three methods:
(1)MOSFET peak current sense at ISENSE pin
(2)Adaptive maximum duty cycle clamp reached during
load/line transients
(3)Maximum duty cycle reset of the PWM latch
During any of the following conditions—low VIN , low
SD_VSEC or overcurrent detection at the OC pin—a softstart event is latched and both SOUT and OUT turn off
immediately (Figure 1).
Leading Edge Blanking
To prevent MOSFET switching noise causing premature turn
off of SOUT or OUT, programmable leading edge blanking
exists. This means both the current sense comparator
and overcurrent comparator outputs are ignored during
MOSFET turn on and for an extended period after the OUT
leading edge (Figure 6). The extended blanking period is
programmable by adjusting a resistor from the BLANK
pin to ground.
Adaptive Maximum Duty Cycle Clamp
(Volt-Second Clamp)
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switch duty cycle clamp which adapts to transformer input
voltage is necessary for reliable control of the MOSFET. This
volt-second clamp provides a safeguard for transformer
reset that prevents transformer saturation. Instantaneous
load changes can cause the converter loop to demand
maximum duty cycle. If the maximum duty cycle of the
switch is too great, the transformer reset voltage can
exceed the voltage rating of the primary-side MOSFET with
19521fe
11
LT1952/LT1952-1
OPERATION
catastrophic damage. Many converters solve this problem
by limiting the operational duty cycle of the MOSFET to
50% or less—or by using a fixed (non-adaptive) maximum
duty cycle clamp with very large voltage rated MOSFETs.
The LT1952/LT1952-1 provide a volt-second clamp to
allow MOSFET duty cycles well above 50%. This gives
greater power utilization for the MOSFET, rectifiers and
transformer resulting in less space for a given power
output. In addition, the volt-second clamp allows a reduced
voltage rating on the MOSFET resulting in lower RDSON
for greater efficiency. The volt-second clamp defines a
maximum duty cycle ‘guard rail’ which falls when system
input voltage increases.
A soft-start event is triggered whenever VIN is too low,
SD_VSEC is too low (UVLO), or a 107mV overcurrent
threshold at OC pin is exceeded. Whenever a soft-start
event is triggered, switching at SOUT and OUT is stopped
immediately.
The LT1952/LT1952-1 SD_VSEC and SS_MAXDC pins
provide a capacitorless, programmable volt-second clamp
solution. Some controllers with volt-second clamps control
switch maximum duty cycle by using an external capacitor
to program maximum switch ON time. Such techniques
have a volt-second clamp inaccuracy directly related to
the error of the external capacitor/pin capacitance and the
error/drift of the internal oscillator. The LT1952/LT19521 use simple resistor ratios to implement a volt-second
clamp without the need for an accurate external capacitor
and with an order of magnitude less dependency on
oscillator error.
Current Mode Topology (ISENSE Pin)
An increase of voltage at the SD_VSEC pin causes the
maximum duty cycle clamp to decrease. If SD_VSEC is
resistively divided down from transformer input voltage,
a volt-second clamp is realised. To adjust the initial
maximum duty cycle clamp, the SS_MAXDC pin voltage
is programmed by a resistor divider from the 2.5V VREF
pin to ground. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
Soft-Start
The LT1952/LT1952-1 provide true PWM soft-start by
using the SS_MAXDC pin to control soft-start timing. The
proportional relationship between SS_MAXDC voltage and
switch maximum duty cycle clamp allows the SS_MAXDC
pin to slowly ramp output voltage by ramping the maximum
switch duty cycle clamp—until switch duty cycle clamp
seamlessly meets the natural duty cycle of the converter.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below it’s reset threshold
of 0.45V and all faults have been removed. Increasing
voltage on the SS_MAXDC pin above 0.8V will increase
switch maximum duty cycle. A capacitor to ground on
the SS_MAXDC pin in combination with a resistor divider
from VREF , defines the soft-start timing.
The LT1952/LT1952-1 current mode topology eases frequency compensation requirements because the output
inductor does not contribute to phase delay in the regulator
loop. This current mode technique means that the error
amplifier (nonisolated applications) or the optocoupler
(isolated applications) commands current (rather than
voltage) to be delivered to the output. This makes frequency
compensation easier and provides faster loop response
to output load transients.
A resistor divider from the application’s output voltage
generates a voltage at the inverting FB input of the LT1952/
LT1952-1 error amplifier (or to the input of an external
optocoupler) and is compared to an accurate reference
(1.23V for LT1952/LT1952-1). The error amplifier output
(COMP) defines the input threshold (ISENSE) of the current
sense comparator. COMP voltages between 0.8V (active
threshold) and 2.5V define a maximum ISENSE threshold
from 0mV to 220mV. By connecting ISENSE to a sense
resistor in series with the source of an external power
MOSFET, the MOSFET peak current trip point (turn off)
can be controlled by COMP level and hence by the output
voltage. An increase in output load current causing the
output voltage to fall, will cause COMP to rise, increasing
ISENSE threshold, increasing the current delivered to the
output. For isolated applications, the error amplifier COMP
output can be disabled to allow the optocoupler to take
control. Setting FB = VREF disables the error amplifier COMP
output, reducing pin current to (COMP – 0.7)/40k.
19521fe
12
LT1952/LT1952-1
OPERATION
Slope Compensation
The current mode architecture requires slope compensation to be added to the current sensing loop to prevent
subharmonic oscillations which can occur for duty cycles
above 50%. Unlike most current mode converters which
have a slope compensation ramp that is fixed internally,
placing a constraint on inductor value and operating
frequency, the LT1952/LT1952-1 have externally adjustable slope compensation. Slope compensation can be
programmed by inserting an external resistor (RSLOPE)
in series with the ISENSE pin. The LT1952/LT1952-1 have
a linear slope compensation ramp which sources current
out of the ISENSE pin of approximately 8µA at 0% duty
cycle to 35µA at 80% duty cycle.
Overcurrent Detection and Soft-Start (OC Pin)
An added feature to the LT1952/LT1952-1 is a precise
100mV sense threshold at the OC pin used to detect
overcurrent conditions in the converter and set a soft-start
latch. The OC pin is connected directly to the source of
the primary side MOSFET to monitor peak current in the
MOSFET (Figure 7). The 107mV threshold is constant
over the entire duty cycle range of the converter because
it is unaffected by the slope compensation added to the
ISENSE pin.
Synchronizing
A SYNC pin allows the LT1952/LT1952-1 oscillator to be
synchronized to an external clock. The SYNC pin can be
driven from a logic level output, requiring less than 0.8V
for a logic level low and greater than 2.2V for a logic level
high. Duty cycle should run between 10% and 90%. To
avoid loss of slope compensation during synchronization, the free running oscillator frequency (fOSC) should
be programmed to 80% of the external clock frequency
(fSYNC). The RSLOPE resistor chosen for non-synchronized
operation should be increased by 1.25x (= fSYNC/fOSC).
APPLICATIONS INFORMATION
Shutdown and Programming Undervoltage Lockout
The LT1952/LT1952-1 have an accurate 1.32V shutdown
threshold at the SD_VSEC pin. This threshold can be
used in conjunction with a resistor divider to define the
undervoltage lockout threshold (UVLO) of the system
input voltage (VS) to the power converter (Figure 3). A pin
current hysteresis (10µA before part turn on, 0µA after
part turn on) allows UVLO hysteresis to be programmed.
Calculation of the ON/OFF thresholds for the supply (SVIN)
to the power converter can be made as follows:
VS OFF Threshold = 1.32[1 + (R1/R2)]
VS ON Threshold = SVIN OFF + (10µA • R1)
A simple open drain transistor can be added to the resistor
divider network at the SD_VSEC pin to control the turn off
of the LT1952/LT1952-1 (Figure 3).
The SD_VSEC pin must not be left open since there must
be an external source current >10µA to lift the pin past its
1.32V threshold for part turn on.
SYSTEM
INPUT (VS)
R1
OPTIONAL
SHUTDOWN
TRANSISTOR
SD_VSEC
–
11µA
R2
1.32V
+
ON OFF
LT1952/LT1952-1
1952 F03
Figure 3. Programming Undervoltage Lockout (UVLO)
Micropower Start-Up: Selection of Start-Up Resistor
and Capacitor for VIN
The LT1952/LT1952-1 use turn-on voltage hysteresis at
the VIN pin and low start-up current to allow micro-power
start-up (Figure 4). The LT1952/LT1952-1 monitor VIN pin
voltage to allow part turn on at 14.25V (7.75V LT1952-1)
and part turn off at 8.75V (6.5V LT1952-1). Low start-up
19521fe
13
LT1952/LT1952-1
APPLICATIONS INFORMATION
current (460µA LT1952; 400µA LT1952-1) allows a large
resistor to be connected between system input supply and
VIN . Once the part is turned on, input current increases to
drive the IC (4.5mA) and the output drivers (IDRIVE). A large
enough capacitor is chosen at the VIN pin to prevent VIN
falling below its turn off threshold before an auxiliary winding
in the converter takes over supply to VIN . This technique
allows a simple resistor/capacitor for start-up which draws
low power from the system supply to the converter. The
values for RSTART and CSTART are given by:
RSTART(MAX) = (VS(MIN) – VIN ON(max))/ISTART(MAX)
CSTART(MIN) = (IQ(MAX) + IDRIVE(MAX)) • tSTART/
VIN HYST(MIN)
Example: (LT1952)
For VS(MIN) = 36V, VIN ON(MAX) = 15.75V,
ISTART(MAX) = 700µA, IQ(MAX) = 5.5mA,
IDRIVE(MAX) = 5mA, VIN HYST(MIN) = 3.75V
and tSTART = 100µs,
possibly exceeding the rating for the VIN pin. The zener
voltage should obey VIN ON(MAX) < VZ < 25V.
Programming Oscillator Frequency
The oscillator frequency (fOSC) of the LT1952/LT1952-1 is
programmed using an external resistor (ROSC) connected
between the ROSC pin and ground. Figure 5 shows typical
fOSC vs ROSC resistor values. The LT1952/LT1952-1 freerunning oscillator frequency is programmable in the range
of 100kHz to 500kHz.
Stray capacitance and potential noise pickup on the ROSC
pin should be minimized by placing the ROSC resistor as
close as possible to the ROSC pin and keeping the area of
the ROSC node as small as possible. The ground side of
the ROSC resistor should be returned directly to the (analog
ground) GND pin. ROSC can be calculated by:
ROSC = 9.125k [(4100k/fOSC) – 1]
500
RSTART = (36 – 15.75)/700µA = 28.9k (choose 28.7k)
For system input voltages exceeding the absolute maximum
rating of the LT1952/LT1952-1 VIN pin, an external zener
should be connected from the VIN pin to ground. This
covers the condition where VIN charges past VIN ON but
the part does not turn on because SD_VSEC < 1.32V. In this
condition VIN will continue to charge towards system VIN ,
SYSTEM
INPUT (VS)
350
300
250
200
150
100
50
100
150
200 250
ROSC (kΩ)
300
350
400
1952 F05
FROM AUXILIARY WINDING
RSTART
400
FREQUENCY (kHz)
CSTART = (5.5mA + 5mA) • 100µs/3.75V = 0.28µF
(typically choose ≥ 1µF)
450
VIN
(14.25V ON, 8.75V OFF) LT1952
(7.75V ON, 6.5V OFF) LT1952-1
D1*
–
1.32V
+
CSTART
*FOR VS > 25V, ZENER D1 RECOMMENDED
(VIN ON(MAX) < VZ < 25V)
1952 F04
Figure 4. Low Power Start-Up
Figure 5. Oscillator Frequency (fOSC) vs ROSC
Programming Leading Edge Blank Time
For PWM controllers driving external MOSFETs, noise
can be generated at the source of the MOSFET during
gate rise time and some time thereafter. This noise can
potentially exceed the OC and ISENSE pin thresholds of the
LT1952/LT1952-1 to cause premature turn off of SOUT and
OUT in addition to false trigger of soft-start. The LT1952/
LT1952-1 provide programmable leading edge blanking
of the OC and ISENSE comparator outputs to avoid false
current sensing during MOSFET switching.
19521fe
14
LT1952/LT1952-1
APPLICATIONS INFORMATION
Blanking is provided in 2 phases (Figure 6): The first phase
automatically blanks during gate rise time. Gate rise times
can vary depending on MOSFET type. For this reason the
LT1952/LT1952-1 perform true ‘leading edge blanking’ by
automatically blanking OC and ISENSE comparator outputs
until OUT rises to within 0.5V of VIN or reaches its clamp
level of 13V. The second phase of blanking starts after
the leading edge of OUT has been completed. This phase
is programmable by the user with a resistor connected
from the BLANK pin to ground. Typical durations for this
portion of the blanking period are from 45ns at RBLANK
= 10k to 540ns at RBLANK = 120k. Blanking duration can
be approximated as:
Blanking (extended) = [45(RBLANK/10k)]ns
(see graph in Typical Performance Characteristics)
(AUTOMATIC)
LEADING
EDGE
BLANKING
OUT
(PROGRAMMABLE)
RBLANK
(MIN)
= 10k
EXTENDED
BLANKING
CURRENT
SENSE
DELAY
10k < RBLANK ≤ 240k
100ns
BLANKING
0
Xns
X + 45ns
[X + 45(RBLANK/10k)]ns
1952 F06
Figure 6. Leading Edge Blank Timing
Programming Current Limit (OC Pin)
The LT1952/LT1952-1 use a precise 107mV sense threshold
at the OC pin to detect overcurrent conditions in the
converter and set a soft-start latch. It is independent of
duty cycle because it is not affected by slope compensation
programmed at the ISENSE pin. The OC pin monitors the
peak current in the primary MOSFET by sensing the
voltage across a sense resistor (RS) in the source of
the MOSFET. The current limit for the converter can be
programmed by:
Current limit = (107mV/RS)(NP/NS) – (1/2)(IRIPPLE)
where:
RS = sense resistor in source of primary MOSFET
IRIPPLE = p-p ripple current in the output inductor L1
NS = number of transformer secondary turns
NP = number of transformer primary turns
Programming Slope Compensation
The LT1952/LT1952-1 use a current mode architecture
to provide fast response to load transients and to ease
frequency compensation requirements. Current mode
switching regulators which operate with duty cycles above
50% and have continuous inductor current must add slope
compensation to their current sensing loop to prevent
subharmonic oscillations. (For more information on slope
compensation, see Application Note 19.) The LT1952/
LT1952-1 have programmable slope compensation to allow
a wide range of inductor values, to reduce susceptibility
to PCB generated noise and to optimize loop bandwidth.
The LT1952/LT1952-1 program slope compensation by
inserting a resistor RSLOPE in series with the ISENSE pin
(Figure 7). The LT1952/LT1952-1 generate a current at
the ISENSE pin which is linear from 0% duty cycle to the
maximum duty cycle of the OUT pin. A simple calculation
of I(ISENSE) • RSLOPE gives an added ramp to the voltage
at the ISENSE pin for programmable slope compensation.
(See both graphs ‘ISENSE Pin Current vs. Duty Cycle’ and
‘ISENSE Maximum Threshold vs Duty Cycle’ in the Typical
Performance Characteristics section.)
CURRENT SLOPE = 35µA • DC
LT1952/
LT1952-1
OUT
OC
ISENSE
1952 F07
VS
RSLOPE
RS
V(ISENSE) = VS + (ISENSE • RSLOPE)
ISENSE = 8µA + 35DC µA
DC = DUTY CYCLE
FOR SYNC OPERATION
ISENSE(SYNC) = 8µA + (k • 35DC)µA
k = fOSC/fSYNC
Figure 7. Programming Slope Compensation
19521fe
15
LT1952/LT1952-1
APPLICATIONS INFORMATION
Programming Synchronous Rectifier Timing:
SOUT to OUT delay (‘tDELAY’)
The LT1952/LT1952-1 have an additional output SOUT
which provides a ±50mA peak drive clamped to 12V. In
applications requiring synchronous rectification for high
efficiency, the LT1952/LT1952-1 SOUT provides a sync
signal for secondary side control of the synchronous
rectifier MOSFETs (Figure 11). Timing delays through the
converter can cause non-optimum control timing for the
synchronous rectifier MOSFETs. The LT1952/LT1952-1
provide a programmable delay (tDELAY , Figure 8) between
SOUT rising edge and OUT rising edge to optimize timing
control for the synchronous rectifier MOSFETs to achieve
maximum efficiency gains. A resistor RDELAY connected
from the DELAY pin to ground sets the value of tDELAY.
Typical values for tDELAY range from 10ns with RDELAY =
10k to 160ns with RDELAY = 160k. (see graph in Typical
Performance Characteristics)
OUT
To program the volt-second clamp, the following steps
should be taken:
(1)The maximum operational duty cycle of the converter
should be calculated for the given application.
(2)An initial value for the maximum duty cycle clamp
should be calculated using the equation below with a
first pass guess for SS_MAXDC.
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
SD_VSEC pin = 1.32V.
Max Duty Cycle Clamp (OUT pin)
= k • 0.522(SS_MAXDC(DC)/SD_VSEC) –
(tDELAY • fOSC)
where,
tDELAY
SOUT
SS_MAXDC pin using a resistor divider from VREF . An
increase of voltage at the SS_MAXDC pin causes the
maximum duty cycle clamp to increase.
SS_MAXDC(DC) = VREF(RB /(RT + RB)
LT1952/
LT1952-1
SD_VSEC = 1.32V at minimum system input voltage
DELAY
1952 F08
RDELAY
Figure 8. Programming SOUT to OUT Delay: tDELAY
Programming Maximum Duty Cycle Clamp
For forward converter applications using the simplest
topology of a single MOSFET on the primary, a maximum
switch duty cycle clamp which adapts to transformer
input voltage is necessary for reliable control of the
MOSFET. This volt-second clamp provides a safeguard for
transformer reset that prevents transformer saturation. The
LT1952/LT1952-1 SD_VSEC and SS_MAXDC pins provide a
capacitor-less, programmable volt-second clamp solution
using simple resistor ratios (Figure 9).
An increase of voltage at the SD_VSEC pin causes the
maximum duty cycle clamp to decrease. Deriving SD_VSEC
from a resistor divider connected to system input voltage
creates the volt-second clamp. The maximum duty cycle
clamp can be adjusted by programming voltage on the
tDELAY = programmed delay between SOUT and OUT
k = 1.11 – 5.5e–7 • (fOSC)
(3) The maximum duty cycle clamp calculated in (2) should
be programmed to be 10% greater than the maximum
operational duty cycle calculated in (1). Simple adjustment of maximum duty cycle can be achieved by adjusting
SS_MAXDC.
SYSTEM
INPUT VOLTAGE
LT1952/
LT1952-1
R1
ADAPTIVE
DUTY CYCLE
CLAMP INPUT
SD_VSEC
R2
RT*
SS_MAXDC
VREF
RB
1952 F09
MAX DUTY CYCLE
CLAMP ADJUST INPUT
*MINIMUM ALLOWABLE RT IS 10k TO
GUARANTEE SOFT-START PULL-OFF
Figure 9. Programming Maximum Duty Cycle Clamp
19521fe
16
LT1952/LT1952-1
APPLICATIONS INFORMATION
Example calculation for (2)
For RT = 35.7k, RB = 100k, VREF = 2.5V,
RDELAY = 40k, fOSC = 200kHz and SD_VSEC = 1.32V,
this gives SS_MAXDC(DC) = 1.84V, tDELAY = 40ns
and k = 1
Maximum Duty Cycle Clamp
= 1 • 0.522(1.84/1.32) – (40ns • 200kHz)
= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)
Note 1: To achieve the same maximum duty cycle clamp at
100kHz as calculated for 200kHz, the SS_MAXDC voltage
should be reprogrammed by:
SS_MAXDC(DC) (100kHz)
= SS_MAXDC(DC) (200kHz) • k (200kHz)/k (100kHz)
= 1.84 • 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)
Note 2 : To achieve the same maximum duty cycle clamp
while synchronizing to an external clock at the SYNC pin,
the SS_MAXDC voltage should be re-programmed as:
SS_MAXDC (DC) (fsync)
= SS_MAXDC (DC) (200kHz) • [(fosc/fsync) +
0.09(fosc/200kHz)0.6]
For SS_MAXDC (DC) (200kHz) = 1.84V for 72%
duty cycle
maximum switch duty cycle clamp, determine soft-start
timing (Figure 11).
A soft-start event is triggered for the following faults:
(1) VIN < 8.75V, or
(2) SD_VSEC < 1.32V (UVLO), or
(3) OC > 107mV (overcurrent condition)
When a soft-start event is triggered, switching at SOUT
and OUT is stopped immediately. A soft-start latch is set
and SS_MAXDC pin is discharged. The SS_MAXDC pin can
only recharge when the soft-start latch has been reset.
Note: A soft-start event caused by (1) or (2) above, also
causes VREF to be disabled and to fall to ground.
Soft-start latch reset requires all of the following:
SS_MAXDC
SOFT-START
SOFT-START
EVENT TRIGGERED
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
TIMING (A): SOFT START
START FAULT
FAULTREMOVED
REMOVED
BEFORE SS_MAXDC FALLS TO 0.45V
SS_MAXDC
SS_MAXDC (DC) (fsync = 250kHz) for 72%
duty cycle
= 1.84 • [(200kHz/250kHz) + 0.09(1)0.6]
= 1.638V
0.8V (ACTIVE THRESHOLD)
0.45V (RESET THRESHOLD)
0.2V
TIMING (B): SOFT-START
SOFT-STARTFAULT
FAULTREMOVED
REMOVED
AFTER SS_MAXDC FALLS PAST
PAST 0.45V
0.45V
Figure 10. Soft-Start Timing
Programming Soft-Start Timing
The LT1952/LT1952-1 have built-in soft-start capability to
provide low stress controlled start-up from a list of fault
conditions that can occur in the application (see Figure 1
and Figure 10). The LT1952/LT1952-1 provide true PWM
soft-start by using the SS_MAXDC pin to control soft-start
timing. The proportional relationship between SS_MAXDC
voltage and switch maximum duty cycle clamp allows
the SS_MAXDC pin to slowly ramp output voltage by
ramping the maximum switch duty cycle clamp—until
switch duty cycle clamp seamlessly meets the natural duty
cycle of the converter. A capacitor CSS on the SS_MAXDC
pin and the resistor divider from VREF used to program
1952 F10
LT1952/
LT1952-1
SS_MAXDC
RT
CSS
SS_MAXDC(DC)
LT1952/
LT1952-1
RCHARGE
VREF
SS_MAXDC
CSS
RB
1952 F11
SS_MAXDC CHARGING MODEL
SS_MAXDC(DC) = VREF [RB/(RT + RB)]
RCHARGE = [RT • RB/(RT + RB)]
Figure 11. Programming Soft-Start Timing
19521fe
17
LT1952/LT1952-1
APPLICATIONS INFORMATION
(A) VIN > 14.25* (7.75V LT1952-1), and
Example:
(B) SD_VSEC > 1.32V, and
For an overcurrent fault (OC > 100mV), VREF = 2.5V,
RT = 35.7k, RB = 100k, CSS = 0.1µF and assume
VSS(MIN) = 0.45V,
IDIS ~ 8e–4 + (2.5 – 0.45)[(1/2 • 100k) – (1/35.7k)]
= 8e–4 + (2.05)(–0.23e–4) = 7.5e–4
(C) OC < 107mV, and
(D) SS_MAXDC < 0.45V (SS_MAXDC reset threshold)
*VIN > 8.75V (6.5V LT1952-1) is ok for latch reset if the latch
was only set by overcurrent condition in (3) above.
SS_MAXDC Discharge Timing
It can be seen in Figure 10 that two types of discharge
can occur for the SS_MAXDC pin. In timing (A) the fault
that caused the soft-start event has been removed before
SS_MAXDC falls to 0.45V. This means the soft-start
latch will be reset when SS_MAXDC falls to 0.45V and
SS_MAXDC will begin charging. In timing (B), the fault that
caused the soft-start event is not removed until some time
after SS_MAXDC has fallen past 0.45V. The SS_MAXDC
pin continues to discharge to 0.2V and remains low until
all faults are removed.
The time for SS_MAXDC to fall to a given voltage can be
approximated as:
SS_MAXDC (tFALL) =
(CSS/IDIS) • [SS_MAXDC(DC) – VSS(MIN)]
where:
IDIS = net discharge current on CSS
CSS = capacitor value at SS_MAXDC pin
SS_MAXDC(DC) = programmed DC voltage
VSS(MIN) = minimum SS_MAXDC voltage before
recharge
IDIS ~ 8e–4 + (VREF – VSS(MIN))[(1/2RB) – (1/RT)]
For faults arising from (1) and (2),
VREF = 100mV.
For a fault arising from (3),
VREF = 2.5V.
SS_MAXDC(DC) = VREF[RB/(RT + RB)]
SS_MAXDC(DC) = 1.84V
SS_MAXDC (tFALL) = (1e – 7/7.5e–4) • (1.84 – 0.45)
= 1.85e–4 s
If the OC fault is not removed before 185µs then SS_MAXDC
will continue to fall past 0.45V towards a new VSS(MIN).
The typical VOL for SS_MAXDC at 150µA is 0.2V.
SS_MAXDC Charge Timing
When all faults are removed and the SS_MAXDC pin
has fallen to its reset threshold of 0.45V or lower, the
SS_MAXDC pin will be released and allowed to charge.
SS_MAXDC will rise until it settles at its programmed DC
voltage—setting the maximum switch duty cycle clamp.
The calculation of charging time for the SS_MAXDC pin
between any two voltage levels can be approximated as
an RC charging waveform using the model shown in
Figure 11.
The ability to predict SS_MAXDC rise time between any two
voltages allows prediction of several key timing periods:
(1)No Switching Period
(time from SS_MAXDC(DC) to VSS(MIN) + time from
VSS(MIN) to VSS(ACTIVE))
(2)Converter Output Rise Time
(time from VSS(ACTIVE) to VSS(REG); VSS(REG) is the
level of SS_MAXDC where maximum duty cycle
clamp equals the natural duty cycle of the switch)
(3)Time For Maximum Duty Cycle Clamp within X% of
Target Value
The time for SS_MAXDC to charge to a given voltage VSS
is found by re-arranging:
VSS(MIN) = SS_MAXDC reset threshold = 0.45V
(if fault removed before tFALL)
19521fe
18
LT1952/LT1952-1
APPLICATIONS INFORMATION
VSS(t) = SS_MAXDC(DC) (1 – e(–t/RC))
Step 3:
to give:
t(VSS = 0.8V) is calculated from:
t = RC • (–1) • ln(1 – VSS/SS_MAXDC(DC))
t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))
= 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84)
= 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s
where:
VSS = SS_MAXDC voltage at time t
SS_MAXDC(DC) = programmed DC voltage setting
maximum duty cycle clamp =
VREF(RB /(RT + RB)
R = RCHARGE (Figure 11) = RT • RB /(RT + RB)
C = CSS (Figure 11)
Example (1) No Switching Period
The period of no switching for the converter, when a soft-start
event has occurred, depends on how far SS_MAXDC can
fall before recharging occurs and how long a fault exists. It
will be assumed that a fault triggering soft-start is removed
before SS_MAXDC can reach its reset threshold (0.45V).
No Switching Period = tDISCHARGE + tCHARGE
tDISCHARGE = discharge time from SS_MAXDC(DC) to
0.45V
tCHARGE = charge time from 0.45V to VSS(ACTIVE)
tDISCHARGE was already calculated earlier as 185µs.
tCHARGE is calculated by assuming the following:
VREF = 2.5V, RT = 35.7k, RB = 100k, CSS = 0.1µF and
VSS(MIN) = 0.45V.
tCHARGE = t(VSS = 0.8V) – t(VSS = 0.45V)
Step 1:
SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V
RCHARGE = (35.7k • 100k/135.7k) = 26.3k
Step 2:
t(VSS = 0.45V) is calculated from,
t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))
= 2.63e4 • 1e–7 • (–1) • ln(1 – 0.45/1.84)
= 2.63e–3 • (–1) • ln(0.755) = 7.3e–4 s
From Step 1 and Step 2:
tCHARGE = (1.5 – 0.73)e–3 s = 7.7e–4 s
The total time of no switching for the converter due to a
soft-start event:
= tDISCHARGE + tCHARGE = 1.85e–4 + 7.7e–4 = 9.55e–4 s
Example (2) Converter Output Rise Time
The rise time for the converter output to reach regulation
can be closely approximated as the time between the start
of switching (SS_MAXDC = VSS(ACTIVE)) and the time where
converter duty cycle is in regulation (DC(REG)) and no
longer controlled by SS_MAXDC (SS_MAXDC = VSS(REG)).
Converter output rise time can be expressed as:
Output Rise Time = t(VSS(REG)) – t(VSS(ACTIVE))
Step 1: Determine converter duty cycle DC(REG) for
output in regulation.
The natural duty cycle DC(REG) of the converter depends on
several factors. For this example it is assumed that DC(REG)
= 60% for system input voltage near the undervoltage
lockout threshold (UVLO). This gives SD_VSEC = 1.32V.
Also assume that the maximum duty cycle clamp
programmed for this condition is 72% for SS_MAXDC(DC)
= 1.84V, fOSC = 200kHz and RDELAY = 40k.
Step 2: Calculate VSS(REG)
To calculate the level of SS_MAXDC (VSS(REG)) that no longer
clamps the natural duty cycle of the converter, the equation
for maximum duty cycle clamp must be used (see previous
section ‘Programming Maximum Duty Cycle Clamp’).
The point where the maximum duty cycle clamp meets
DC(REG) during soft-start is given by:
DC(REG) = Max Duty Cycle clamp
0.6 = k • 0.522(SS_MAXDC(DC)/SD_VSEC) –
(tDELAY • fOSC)
19521fe
19
LT1952/LT1952-1
APPLICATIONS INFORMATION
For SD_VSEC = 1.32V, fOSC = 200kHz and RDELAY = 40k
This gives k = 1 and tDELAY = 40ns.
Re-arranging the above equation to solve for SS_MAXDC
= VSS(REG)
= [0.6 + (tDELAY • fOSC)(SD_VSEC)]/(k • 0.522)
= [0.6 + (40ns • 200kHz)(1.32V)]/(1 • 0.522)
= (0.608)(1.32)/0.522 = 1.537V
t(1.803) = 2.63e–4 • 1e–7 • (–1) • ln(1 – 1.803/1.84)
= 2.63e–3 • (–1) • ln(0.02) = 1.03e–2 s
Hence the time for SS_MAXDC to charge from its minimum
reset threshold of 0.45V to within 2% of its target value
is given by:
t(1.803) – t(0.45) =
1.03e–2 – 7.3e–4 = 9.57e–3
Step 3: Calculate t(VSS(REG)) – t(VSS(ACTIVE))
Forward Converter Applications
Recall the time for SS_MAXDC to charge to a given voltage
VSS is given by:
The following section covers applications where the
LT1952/LT1952-1 are used in conjunction with other LTC
parts to provide highly efficient power converters using
the single switch forward converter topology.
t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))
(Figure 11 gives the model for SS_MAXDC charging)
For RT = 35.7k, RB = 100k, RCHARGE = 26.3k
For CSS = 0.1µF, this gives t(VSS(ACTIVE))
= t(VSS(0.8V)) = 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84)
= 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s
t(VSS(REG)) = t(VSS(1.537V)) = 26.3k • 0.1µF • –1 •
ln(1 – 1.66/1.84) = 2.63e–3 • (–1) • ln(0.146)
= 5e–3 s
The rise time for the converter output
= t(VSS(REG)) – t(VSS(ACTIVE)) = (5 – 1.5)e–3 s
= 3.5e–3 s
Example (3) Time For Maximum Duty Cycle Clamp to
Reach Within X% of Target Value
A maximum duty cycle clamp of 72% was calculated
previously in the section ‘Programming Maximum
Duty Cycle Clamp’. The programmed value used for
SS_MAXDC(DC) was 1.84V.
The time for SS_MAXDC to charge from its minimum value
VSS(MIN) to within X% of SS_MAXDC(DC) is given by:
t(SS_MAXDC charge time within X% of target)
= t[(1 – (X/100) • SS_MAXDC(DC)] – t(VSS(MIN))
For X = 2 and VSS(MIN) = 0.45V, t(0.98 • 1.84) –
t(0.45) = t(1.803) – t(0.45)
From previous calculations, t(0.45) = 7.3e – 4 s.
95% Efficient, 5V, Synchronous Forward Converter
The circuit in Figure 14 is based on the LT1952-1 to provide
the simplest forward power converter circuit—using only
one primary MOSFET. The SOUT pin of the LT1952-1
provides a synchronous control signal for the LTC1698
located on the secondary. The LTC1698 drives secondary
side synchronous rectifier MOSFETs to achieve high
efficiency. The LTC1698 also serves as an error amplifier
and optocoupler driver.
Efficiency and transient response are shown in Figures 12
and 13. Peak efficiencies of 95% and ultra-fast transient
response are superior to presently available power
modules. Integrated soft-start, overcurrent detection and
short-circuit hiccup mode provide low stress, reliable
protection. In addition, the circuit in Figure 14 is an allceramic capacitor solution providing low output ripple
voltage and improved reliability. The LT1952-based
converter can be used to replace power module converters
at a much lower cost. The LT1952 solution benefits from
thermal conduction of the system board resulting in higher
efficiencies and lower rise in component temperatures. The
7mm height allows dense packaging and the circuit can
easily be adjusted to provide an output voltage from 1.23V
to 26V. Higher currents are achievable by simple scaling
of power components. The LT1952-1-based solution in
Figure 14 is a powerful topology for replacement of a wide
range of power modules.
Using previous values for RT , RB, and CSS,
19521fe
20
LT1952/LT1952-1
APPLICATIONS INFORMATION
98
EFFICIENCY (%)
96
94
IOUT
(5A/DIV)
92
0A
90
VOUT
(200mV/DIV)
88
86
VIN = 48V
VOUT = 5V
fOSC = 300kHz
5
0
15
10
LOAD CURRENT (A)
20
Figure 13. Output Voltage Transient Response
(6A to 12A Load Step at 6A/µs)
1952 F12
Figure 12. LT1952-Based Synchronous Forward Converter
Efficiency vs Load Current (For Circuit in Figure 14)
+VIN
36V TO 72V
SOUT
16
5
100k
22k
6
2
0.1µF
0.1µF
3
115k
4
15
VIN
BLANK DELAY
1
COMP
9
12
40k
33k
1k
18.2k
8
GND
SYNC
Q1
13
LT1952-1 PGND
ROSC
Q2
PH3830
C01
100µF
X5R
2×
Q3
PH3830
10
ISENSE
FB
+V0UT
5V
20A
11
OC
VREF
L1
PA1393.152
T1
PA0491
475k
14
OUT
SS_MAXDC
CIN
2.2µF
100V
X5R
7
SD_VSEC
SOUT
1952 F13
20µs/DIV
25
7VBIAS
10VBIAS
1
10VBIAS
Q1: PHM15NQ20 PHILIPS
0.1µF
2
1µF
X5R
9.53k
T2
SOUT
1µF
0.015Ω
4.75k
220pF
R13
270Ω
SYNC
560Ω
3
C9, 6.8nF
R14
1.2k
HCPL-M453
6
1
5
2
4
3
+V0UT
R15
38.3k
4
5
6
8
LTC1698
VDD
CG
FG
SYNC
PGND
VAUX
GND
ICOMP
OPTO
+ISNS
VCOMP
–ISNS
VFB
OVP
16
15
SYNC
14
0.1µF
13
12
11
9
R16
12.4k
1952 F14
Figure 14. 36V to 72V Input to 5V at 20A Synchronous Forward Converter
19521fe
21
LT1952/LT1952-1
APPLICATIONS INFORMATION
48V to Isolated 12V, 20A (No Opto-Coupler)
‘Bus Converter’
achieves a high 94% at 20A (Figure 15). The solution is
only slightly larger than 1/4 “brick” size and uses only
ceramic capacitors for high reliability.
The wide programmable range and accuracy of the
LT1952/LT1952-1 Volt-Second clamp makes the LT1952/
LT1952‑1 an ideal choice for ‘Bus Converter’ applications
where the Volt-Second clamp provides line regulation for
the converter output. The 48V to 12V 20A ‘Bus Converter’
application in Figure16 shows a semi-regulated isolated
output without the need for an optocoupler, optocoupler
driver, reference or feedback network. Some ‘Bus Converter’
solutions run with a fixed 50% duty cycle resulting in an
output variation of 2-to-1 for applications with a 72V to
36V input range. The LT1952/LT1952-1 use an accurate
wide programmable range Volt-Second clamp to initially
program and then control power supply output voltage
to typically ±10% for the same 36V to 72V input range.
Efficiency for the LT1952 based bus converter in Figure 16
EFFICIENCY (%)
95.5
95.0
94.5
94.0
93.5
93.0
VIN = 48V
VOUT = 12V
4
6
8
10 12 14 16
LOAD CURRENT (A)
Figure 15. LT1952-Based Synchronous ‘Bus Converter’
Efficiency vs Load Current (For Circuit in Figure 16)
T1
PA0815.002
2.4µH
• •
BAS516
BCX55
0.1µF
18V
Si7370
2x
12V
2.2µF, 100V
2x
7
115k
3
27k
0.47µF
0.1µF
9
5
59k
10k
6
1
2
SD_VSEC
OUT
ROSC
VIN
BLANK
GND
SS_MAXDC
LT1952
VREF
COMP
FB
PGND
DELAY
OC
ISENSE
SOUT
5
14
VU1
6
1µF
4
15
8
BAT760
1µF
13
12
8V
BIAS
39k
9mΩ
11
10
16
470Ω
8
FG
10k
COUT
33µF, 16V
X5R, TDK
3x
T2
Q4470-B
3
+ 1
10k
2
10k
CS
VCC
CS–
SYNC TIMER
7
RT
15k
CT
1nF
8V
BIAS
560W
220pF
CG
GND
1nF
• •
13.2k
PH4840
2x
VOUT
12V, 20A
LTC3900
•
PH21NQ15
2x
370k
20
1952 F15
VU1
82k
18
•
VIN
36V TO 72V
47k
96.0
L1: PA1494.242 PULSE ENGINEERING
T1: PULSE ENGINEERING
T2: COILCRAFT
1952 F16
Figure 16. 36V to 72V Input to 12V at 20A No ‘Optocoupler’ Synchronous ‘Bus Converter’
19521fe
22
LT1952/LT1952-1
APPLICATIONS INFORMATION
An LT1952-based synchronous forward converter provides
the ideal solution for power supplies requiring high efficiency
at low output voltages and high load currents. The 3.3V 40A
solution in Figure 18 achieves peak efficiencies of 92.5%
(Figure 17) by minimizing power loss due to rectification
at the output. Synchronous rectifier control output SOUT,
with programmable delay, optimizes timing control for a
secondary side synchronous MOSFET controller (LTC3900)
which results in high efficiency synchronous rectification.
The LT1952/LT1952-1 use a precision current limit threshold
at the OC pin combined with a soft-start hiccup mode to
provide low stress output short-circuit protection. The
maximum output current will vary only 10% over the full VIN
range. During short-circuit the average power dissipation
of the circuit will be lower than 15% of maximum rated
power thanks to a soft-start controlled hiccup mode.
47k
VU1
94
93
92
91
90
89
88
86
82k
BCX55
L1
Q2
PH3230
2x
5
5
10k
6
0.1µF
33k
1
2
2.2k
LT1952
SS_MAXDC
GND
PGND
DELAY
VR = 2.5V
COMP
FB = 1.23V
OC
ISENSE
SOUT
8
BAT760
12
8V
BIAS
1µF
13
39k
10mΩ
11
10
470Ω
8
CG
3
GND
1
CS+
10k
VCC
CS–
2
10k
SYNC TIMER
7
1nF
15k
1nF
8V
BIAS
560Ω
220pF
16
22k
4
FG
T2
Q4470-B
249k
8V
BIAS
2.2nF
80.6k
18k
VU1
1
L1: PA0713, PULSE ENGINEERING
ALL CAPACITORS X7R, CERAMIC, TDK
T2: COILCRAFT
LT1797
PS2801
270Ω
5
2
–
59k
BLANK
Si7846
15
COUT
100µF
3x
10k
+
0.22µF
9
VIN
1mF
• •
27k
OUT
ROSC
VU1
Q3
PH3230
2x
LTC3900
•
6
SD_VSEC
VOUT
3.3V, 40A
BAS516
12V
14
50
Figure 17. LT1952-Based Synchronous Forward Converter
Efficiency vs Load Current (For Circuit in Figure 18)
370k
3
20
40
30
OUTPUT CURRENT (A)
• •
2.2mF
115k
10
1952 F17
0.1µF
7
0
PA0912.002
18V
13.2k
VIN = 48V
VOUT = 3.3V
fOSC = 300kHz
87
•
+VIN
36V TO 72V
This allows a significant reduction in power component
sizing using the LT1952-based converter.
EFFICIENCY (%)
36V to 72V Input, 3.3V 40A Converter
4
3
10k
10k
1µF
8
0.1µF
4
LT1009
1952 F18
Figure 18. 36V to 72V, 3.3V at 40A Synchronous Forward Converter
19521fe
23
LT1952/LT1952-1
APPLICATIONS INFORMATION
Bus Converter: Optimum Output Voltage Tolerance
The Bus Converter applications shown on page 1 and in
Figure 16, provide semi-regulated isolated outputs without
the need for an optocoupler, optocoupler driver, reference or
feedback network. The LT1952/LT1952-1Volt-Second clamp
adjusts switch duty cycle inversely proportional to input
voltage to provide an output voltage that is regulated against
input line variations. Some bus converters use a switch duty
cycle limit which causes output voltage variation of typically
±33% over a 2:1 input voltage range. The LT1952/LT1952-1
typically provide a ±10% output variation for the same input
variation. Typical output tolerance is further improved for the
LT1952 by inserting a resistor from the system input voltage
to the SS_MAXDC pin (Rx in Figure 19).
The LT1952/LT1952-1 electrical specifications for the OUT
Max Duty Cycle Clamp show typical switch duty cycle to
move from 72% to 33% for a 2x change of input voltage
(SS_MAXDC  pin = 1.84V). Since output voltage regulation
follows VIN • Duty Cycle, a switch duty cycle change of
72% to 36% (for a 2x input voltage change) provides
minimal output voltage variation for the LT1952/LT1952-1
bus converter. To achieve this, an SS_MAXDC pin voltage
increase of 1.09x (36/33) would be required at high input
line. A resistor Rx inserted between the SS_MAXDC pin
and system input voltage (Figure 19) increases SS_MAXDC
voltage as input voltage increases, minimizing output
voltage variation over a 2:1 input voltage change.
The following steps determine values for Rx, RT and RB:
(1)Program switch duty cycle at minimum system input
voltage (VS(MIN))
(a)RT(1) = 10k (minimum allowed to still guarantee softstart pull-down)
Rx
VOLT-SECOND
CLAMP INPUT
VOLT-SECOND
CLAMP ADJUST INPUT
LT1952/
LT1952-1
SD_VSEC
R2
(c)Calculate RB(1) = [SS1/(2.5 – SS1)] • RT(1)
(2)Calculate Rx:
Rx = ([VS(MAX) – VS(MIN)]/[SS1 • (X – 1)]) • RTHEV(1)
RTHEV(1) = RB(1) • RT(1)/(RB(1) + RT(1)), X = ideal duty
cycle (VS(MAX))/actual duty cycle (VS(MAX))
(3)The addition of Rx causes an increase in the original
programmed SS_MAXDC voltage SS1. A new value for
RB(1) should be calculated to provide a lower SS_MAXDC
voltage (SS2) to correct for this offset:
(a)SS2 = SS1 – [(VS(MIN) – SS1) • RTHEV(1)/Rx]
(b)RB(2) = [SS2/(2.5 – SS2)] • RT(1)
(4)The thevinin resistance RTHEV(1) used to calculate Rx
should be re-established for RT and RB:
(a) RB (final value) = RB(2) • (RTHEV(1)/RTHEV(2))
(b) RT (final value) = RT(1) • (RTHEV(1)/RTHEV(2))
where RTHEV(2) = RB(2) • RT(1)/(RB(2) + RT(1))
Example:
For a Bus Converter running from 36V to 72V input,
VS(MIN) = 36V, VS(MAX) = 72V.
choose RT(1) = 10k, SS_MAXDC = SS1 = 1.84V (for 72%
duty cycle at VS(MIN) = 36V)
RB(1) = [1.84V/(2.5V – 1.84V)] • 10k = 28k
RTHEV(1) = [28k • 10k/(28k + 10k)] = 7.4k
SS_MAXDC correction = 36%/33% = 1.09
Rx = [(72V – 36V)/(1.84 • 0.09)] • 7.4k = 1.6M
SYSTEM
INPUT VOLTAGE
R1
(b)Select switch duty cycle for the Bus Converter for a
given output voltage at VS(MIN) and calculate SS_MAXDC
voltage (SS1) (See Applications Information “Programming Maximum Duty Cycle Clamp”)
RT
RB
SS_MAXDC
SS2 = 1.84 – [(36V – 1.84) • 7.4k/1.6M] = 1.682V
RB(2) = [1.682/(2.5 – 1.682)] • 10k = 20.6k
RTHEV(2) = [20.6k • 10k/(20.6k + 10k)] = 6.7k
VREF
1952 F19
Figure 19. Optimal Programming of Maximum Duty
Cycle Clamp for Bus Converter Applications (Adding Rx)
RTHEV(1)/RTHEV(2) = 7.4k/6.7k = 1.104
RB (final value) = 20.6k • 1.104 = 22.7k (choose 22.6k)
RT (final value) = 10k • 1.104 = 11k
19521fe
24
LT1952/LT1952-1
TYPICAL APPLICATIONS
Wide 18V to 72V Input, High Efficiency, 12V at 12A Output, Active Reset Forward Converter Fits in One-Eighth Brick Footprint
+VIN
+VIN
18V TO 72V
+VB
VUL
L2
R1
Q10
1.5mH
2.2Ω
PBSS8110
+VIN
R5
10Ω
VUL
6
VCC BOOST
LTC4440-5
5
2
TG
GND
3
INP
R3 442Ω
TS
C25
10nF
Q1
HAT2173
4
RCSL
0.006Ω
L53
10µH
OUT
D1 BAS516
1
2
Q12
BC856T
R15 115k 3
4
C13 0.47µF
5
6
C10 0.1µF
R22
13.3k
R28
309k
R32
187k
+VB
C33
0.1µF
7
8
COMP
FB
ROSC
SOUT
VIN
OUT
16
T1
G45R2-0405.005
L3
680µH
R54
4.7Ω
C34
0.22µF
14
LT1952-1
13
PGND
SYNC
SS_MAXDC DELAY
VREF
SD_VSEC
GND
OC
ISENSE
BLANK
12
C10
100pF
9
R24 68k
C14
1µF
R10
1k
VUL
CSYS
220µF 16V
APXE
R16
33k
PE-68386
LTC3900
8
•
CS+ SYNC
2
7
R17
CS– TIMER
560Ω
3
6
R21
GND
CG
10k CG
•
C12
4
5
FB 470pF
FB
VCC
1
220pF
R19 47.5k
D11
BAS516
PS2801-1
R31
10Ω
VFB
R30
1.2k
C19
1µF X5R
C15
2.2nF 2kV
10µH
OUT
LT4430
6
VCC OPTO
2
5
GND COMP
3
4
SS
FB
1
C16
0.22µF
10V
C23
1µF
+
Q3
HAT2173
CG
D9
PDZ10B
R26
220Ω
C8
100pF
CUL
4.7µF
11
R23 2k
R18
10k
Q9
BCX55
R45 10k
C9
100pF R20 115k
10
D7
BAS521
C5
0.22µF
Q13
Si2325
+VOUT
R8
2.2Ω
D6
BAS521
D14
BAS516
VUL
15
Q2
HAT2266
FG
•
+VOL
COL
33µF
X7R
9, 10, 11
D17 BAS516
R27
470Ω
C17
15nF
+VOL
R34
12.1k
R35
348k
R38
18.2k
1952 TA02a
C24
22pF
D29
PMEG3002
R2 560k
+VR2
The 12V Output Converter Fits in a One-Eighth “Brick” Footprint and Has a
Very High Efficiency Over 18V to 72V Input Voltage Range
96
95
24V INPUT
94
93
EFFICIENCY (%)
VFB
R14
33k
2, 3
L1
HR-PQA2050-10
• 7, 8
•
4, 5
1
C3
1µF
C21
220pF
1
D3
BAS516 6
+VR2
–VIN
R13
22k
D5
PDZ10B
R11
47k
CIN
2.2µF
×3
D2
BAS516
48V INPUT
92
91
90
89
88
87
86
85
84
0
2
4
6
IOUT (A)
8
10
12
1952 TA02b
19521fe
25
LT1952/LT1952-1
TYPICAL APPLICATIONS
High Efficiency 36V to 72V Input to 3.3V at 30A Output, Active Reset Forward Converter Fits in One-Eighth Brick Footprint
+VIN
+VB
VUL
L2
R1
Q10
1.5mH
2.2Ω
PBSS8110
+VIN
CIN
2.2µF
×2
–VIN
R11
82k
C34
0.22µF
D2
BAS516
9, 10, 11
+VIN
2, 3
•
1
2
Q12
BC856T
R15 115k 3
COMP
FB
VIN
D11
BAS516
C10 0.1µF
5
6
7
R22 13.3k
R32
332k
R28
442k
+VR2
+VB
8
SS_MAXDC DELAY
OC
VREF
SD_VSEC
GND
R29 22k
R33
470k
ISENSE
BLANK
VUL R26
220Ω
15
14
OUT
LT1952-1
4
13
PGND
SYNC
SS
PS2801-1
16
ROSC
D10
BAT760
CUL
4.7µF
C23
1µF
C9
100pF R20 174k
12
CSYS
470µF
6.3V
R8
2.2Ω
VFB
SOUT
+VOUT
R50
2.2Ω
CS
D14 BAS516
VFB
Q3
HAT2165
T1
PA0861.004
Q13
Q1
C25
Si2325 10nF Si7430
RCS1
R45 10k
0.015Ω
R14
33k
COL
100µF
×2 +
R49
2.2Ω
4, 5
D17
BAS516
R13
22k
L1
PA1671.650
• 7, 8
Q2
HAT2165
C33
0.1µF
R53
200Ω
•
D3
BAS516 6
VR2
D5
PDZ10B
R54
4.7Ω
1
R30
1.2k
D6
B0540W
C16
22µF
LT4430
1
6
VCC OPTO
2
5
GND COMP
3
4
SS
FB
C19
1µF
C15
2.2nF 2kV
R27
470Ω
C17
10nF
R38
18.2k
1952 TA03a
R34
4.75k
R35
82.5k
C24
47pF
11
10 R23 1.2k
9
CS
R24 39k
SS
C13
0.47µF
The High Efficiency of 3.3V Output Converter Allows Tight PCB Layout and
Results in Low Component Temperature Rises
94
EFFICIENCY (%)
93
92
91
90
89
88
0
10
20
IOUT (A)
30
1952 TA03b
19521fe
26
LT1952/LT1952-1
(Revision history begins at Rev E)
REV
DATE
DESCRIPTION
PAGE NUMBER
E
5/11
MP-grade parts added, changes reflected throughout the data sheet
1-28
19521fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT1952/LT1952-1
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC®3900
Synchronous Rectifier N-Channel MOSFET Driver
for Forward Converters
Programmable Timeout and Reverse Inductor Current Protection,
Transformer Synchronization, SSOP-16
LT4430
Secondary-Side Opto-Coupler Driver with Reference Overshoot Control Prevents Output Overshoot During Start-up and ShortVoltage
Circuit Recovery
LTC3726/LTC3725
Isolated Synchronous No Opto Forward Controller
Chip Set
Ideal for Medium Power 24V or 48V Input Applications
LTC3705/LTC3726
2-Switch Synchronous Forward No Opto Isolated
Controller Chip Set
Self-Starting Architecture Eliminates Need for a Bias Voltage on
Primary Side
LTC3722/LTC2722-2
Synchronous Isolated Full-Bridge Controllers with
Zero Voltage Switching
Ideal for High Power 24V or 48V Input Applications
LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers
High Efficiency with On-Chip MOSFET Drivers
LTC3721-1/LTC3721-2 Non-Synchronous Push-Pull and Full-Bridge
Controllers
Minimizes External Components, On-Chip MOSFET Drivers
LT3748
100V No Opto Flyback Controller
5V ≤ VIN ≤ 100V, Boundary Mode Operation, MSOP-16 with Extra High
Voltage Pin Spacing
LTC3803/LTC3803-3/
LTC3803-5
Flyback DC/DC Controllers with Fixed 200kHz or
300kHz Operating Frequency
VIN and VOUT Limited Only by External Components, 6-Pin ThinSOT™
Package
19521fe
28 Linear Technology Corporation
LT 0511 REV E • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2004