S i 5 2 1 3 1 - A 11 A PCI-E X P R E S S G EN 1 , G E N 2, & G EN 3 TW O O U T P U T C LOCK G E N E R A T O R W I T H 25 MH Z R E F E RE NCE C LOCK & A C T I V E L OW OE P IN S Features 22 21 20 19 1 18 OE_DIFF1 17 VDD_DIFF REF 2 OE_REF1 3 VSS_REF 4 OE_DIFF01 5 VDD_DIFF 6 16 DIFF1 25 GND 15 DIFF1 14 DIFF0 13 DIFF0 7 8 Note 1. Internal 100 k-ohm pull-down resistor 9 10 11 12 VDD_DIFF Si52131-A11A is a high-performance, PCIe clock generator that can source two PCIe clocks and a buffered 25 MHz reference clock from a 25 MHz crystal or clock input. The PCIe clock outputs are compliant to PCIe Gen 1, Gen 2, and Gen 3 specifications. The device has three active low output enable pins for enabling and disabling each output. The device features two input select pins for frequency selection and spread control. The small footprint and low power consumption makes Si52131A11A the ideal clock solution for consumer and embedded applications. 23 1 1 Description 24 VDD_REF SS0 Network Attached Storage Wireless Access Point Multi-function Printer Routers Ideal for Thunderbolt applications SCLK Applications VDD_CORE Pin Assignments SDATA NC Ordering Information: See page 17 XOUT NC XIN/CLKIN NC I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Extended Temperature –40 to 85oC 3.3 V Power supply 24-pin QFN package SS1 25 MHz Crystal Input or Clock input VSS_CORE PCI-Express Gen1, Gen2 & Gen3 Compliant Supports Serial ATA (SATA) at 100 MHz Low power differential output buffers No termination resistors required Dedicated active low output enable pins for each output Pin selectable spread control Selectable frequencies: 100, 125, and 200 MHz Up two PCI-Express clocks 25 MHz reference clock 1 Patents pending Functional Block Diagram 25MHz XIN/CLKIN XOUT DIFF0 PLL1 (SSC) Divider DIFF1 SCLK SDATA Control & Memory OE#_REF OE#_DIFF [1:0] Control RAM SSC [1:0] Rev 1.0 3/13 Copyright © 2013 by Silicon Laboratories Si52131-A11A Si52131-A11A 2 Rev 1.0 Si52131-A11A TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. SS[1:0] Pins Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Si52131-A11A Pin Descriptions 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Rev 1.0 3 Si52131-A11A 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ±5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH SS1:0 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL SS1:0 VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (SE) VOH IOH = –1 mA 2.4 — — V 3.3 V Output Low Voltage (SE) VOL IOL = 1 mA — — 0.4 V High-impedance Output Current IOZ –10 — 10 A Input Pin Capacitance CIN 1.5 — 5 pF COUT — — 6 pF LIN — — 7 nH Power Down Current IDD_PD — — 1 mA Dynamic Supply Current IDD_3.3V — — 45 mA Output Pin Capacitance Pin Inductance 4 All outputs enabled. Differential clocks with 5” traces and 2 pF load. 25 MHz clock with 5” traces and 4 pF load Rev 1.0 Si52131-A11A Table 2. AC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 47 — 53 % CLKIN Rise/Fall Slew Rate TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 µA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — µA Duty Cycle TDC Measured at 0 V differential 45 — 55 % Cycle to Cycle Jitter TCCJ Measured at 0 V differential — 35 50 ps PCIe Gen 1 Pk-Pk Jitter Pk-Pk PCIe Gen 1 0 40 86 ps PCIe Gen 2 Phase Jitter RMSGEN2 10 kHz < F < 1.5 MHz 0 2 3.0 ps 1.5 MHz < F < Nyquist 0 2 3.1 ps RMSGEN3 Includes PLL BW 2–4 MHz, CDR = 10 MHz 0 0.5 1.0 ps Long Term Accuracy LACC Measured at 0 V differential — — 100 ppm Rise/Fall Slew Rate TR/TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV — –0.5 — % 30 31.5 33 kHz Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle DIFF at 0.7 V PCIe Gen 3 Phase Jitter Crossing Point Voltage at 0.7 V Swing Spread Range SPR-2 Modulation Frequency FMOD Down spread REF at 3.3 V Duty Cycle TDC Measurement at 1.5 V 45 — 55 % Rise/Fall Slew Rate T R / TF Measured between 0.8 and 2.0 V 1.0 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 300 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm TSTABLE — — 1.8 ms TSS 10.0 — — ns Enable/Disable and Setup Clock Stabilization from Power-up Stopclock Setup Time Note: Visit www.pcisig.com for complete PCIe specifications. Rev 1.0 5 Si52131-A11A Table 3. Absolute Maximum Conditions Parameter Symbol Test Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 20 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 60 °C/W ESDHBM JEDEC (JESD 22 - A114) 2000 — — V UL-94 UL (Class) Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating V–0 Note: While using multiple power supplies, the Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6 Rev 1.0 Si52131-A11A 2. Functional Description 2.1. Crystal Recommendations The clock device requires a parallel resonance crystal. Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. Crystal Loading Crystal loading is critical in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. Figure 1. Crystal Capacitive Clarification 2.1.2. Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Rev 1.0 7 Si52131-A11A Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: Crystal load capacitance Actual loading seen by crystal using standard value trim capacitors Ce: External trim capacitors Cs: Stray capacitance (terraced) Ci : Internal capacitance (lead frame, bond wires, etc.) CLe: 2.2. OE Pin Function The OE pin is an active low input used to enable and disable the output clock. To enable the output clock, the OE pin needs to be logic low and the I2C output enable bit needs to be logic high. By default, the OE pin is set to a logic low and the I2C output enable bit is set to a logic high. There are two methods to disable the output clock: the OE pin is pulled to a logic high or the I2C output enable bit is set to a logic low. The OE pin is required to be driven at all times even though it has an internal 100 k resistor. 2.3. OE Assertion The OE pin is an active low input used for synchronous stopping and starting the respective output clock while the rest of the clock generator continues to function. The assertion of the OE function is achieved by pulling the OE pin low and the I2C output enable bit high, which causes the respective stopped output to resume normal operation. No short or stretched clock pulses are produced when the clocks resume. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles. 2.4. OE Deassertion The OE function is de-asserted by pulling the pin high, or setting the I2C output enable bit to a logic low. The corresponding output is stopped and the final output state is driven low. 2.5. SS[1:0] Pins Function SS1 and SS0 are active inputs used to change the frequency and/or to enable –0.5% down spread on all DIFF outputs. When sampled high or low, the appropriate selection of frequency and spread from Table 5 is applied on all differential outputs. These inputs have an internal pull-down though a 100 k resistor. The default state is SS[1:0] = 00, corresponding to 100 MHz outputs with spread spectrum disabled. Table 5. SS0 & SS1 Frequency/Spread Selection 8 SS1 SS0 Differential Frequency Differential Spread 0 0 100 MHz Spread Off 0 1 100 MHz –0.50% 1 0 125 MHz Spread Off 1 1 200 MHz Spread Off Rev 1.0 Si52131-A11A 3. Test and Measurement Setup This diagram shows the test load configuration for differential clock signals. M e a s u re m e n t P o in t L1 O U T+ 5 0 2 pF L1 = 5" M e a s u re m e n t P o in t L1 O U T- 5 0 2 pF Figure 3. 0.7 V Differential Load Configuration Figure 4. Differential Output Signals (for AC Parameters Measurement) Rev 1.0 9 Si52131-A11A Figure 5. Single-Ended Measurement for Differential Output Signals (for AC Parameter Measurement) L1 = 0.5", L2 = 5" Measurement 50 SE Clocks Point L1 33 L2 4 pF Figure 6. Single-Ended Clocks with Single Load Configuration Figure 7. Single-Ended Output Signal (for AC Parameter Measurement) 10 Rev 1.0 Si52131-A11A 4. Control Registers 4.1. I2C Interface To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. One can control various functions through the I2C interface, such as individual enabling or disabling of the clock output buffers. The registers associated with the I2C interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. 4.2. Data Protocol The I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The block write and block read protocol is outlined in Table 6 while Table 7 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 6. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Block Read Protocol Description Bit Start 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 28 36:29 37 45:38 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count–8 bits 20 Repeat start Acknowledge from slave 27:21 Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N–8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Rev 1.0 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop 11 Si52131-A11A Table 7. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Byte Read Protocol Description Bit Start 1 Slave address–7 bits 8:2 Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 Rev 1.0 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop Si52131-A11A Register 1. Byte 0: Control Register 0 Bit D7 D6 D5 D4 D3 D1 D0 R/W R/W R/W 25M_OE Name Type D2 R/W R/W R/W R/W R/W Reset settings = 00000100 Bit Name Function 7:3 Reserved 2 25_OE 1:0 Reserved Output Enable for 25 MHz. 0: Output disabled. 1: Output enabled. Register 2. Byte 1: Control Register 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Name Type Reset settings = 00000000 Bit Name Function 7:0 Reserved Register 3. Byte 2: Control Register 2 Bit D7 D6 Name DIFF0_OE DIFF1_OE Type R/W R/W D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W Reset settings = 11000000 Bit Name Function 7 DIFF0_OE Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 6 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. 5:0 Reserved Rev 1.0 13 Si52131-A11A Register 4. Byte 3: Control Register 3 Bit D7 D6 D5 D4 Name Rev Code Bit 3 Rev Code Bit 2 Rev Code Bit 1 Rev Code Bit 0 Type R/W R/W R/W R/W D3 D2 D1 D0 Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit 3 0 2 1 R/W R/W R/W R/W Reset settings = 00001000 Bit Name Function 7:4 Rev Code Bit 3:0 Program Revision Code 3:0 Vendor ID bit 3:0 Vendor Identification Code Register 5. Byte 4: Control Register 4 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name BC7 BC7 BC5 BC4 BC3 BC2 BC1 BC0 Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 00000110 Bit Name 7:0 BC7:0 Function Byte Count Register. Register 6. Byte 5: Control Register 5 Bit D7 D6 D5 D4 Name DIFF_Am_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W Reset settings = 11011000 14 Bit Name 7 DIFF_Amp_Sel 6:4 DIFF_Amp_Cntl[2:0] 3:0 Reserved Function Amplitude control for DIFF Differential outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV 100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV Rev 1.0 Si52131-A11A VSS_CORE XIN/CLKIN XOUT VDD_CORE SDATA SCLK 5. Si52131-A11A Pin Descriptions: 24-Pin QFN 24 23 22 21 20 19 VDD_REF 1 1 18 OE_DIFF1 REF 2 17 VDD_DIFF OE_REF1 3 VSS_REF 4 OE_DIFF01 5 VDD_DIFF 6 16 DIFF1 25 GND 15 DIFF1 14 DIFF0 9 10 11 12 NC NC VDD_DIFF SS1 1 8 SS0 1 7 NC 13 DIFF0 Note 1. Internal 100 k-ohm pull-down resistor Table 8. Part Number 24-Pin QFN Descriptions Pin # Name Type Description 1 VDD_REF 2 REF 3 OE_REF1 I,PD Active low input pin enables REF (internal 100 k pull-down). 4 VSS_REF GND Ground. 5 OE_DIFF01 I,PD Active low input pin enables DIFF0 (internal 100 k pull-down). 6 VDD_DIFF PWR 3.3 V power supply. 7 SS01 I, PD 8 SS11 I, PD PWR 3.3 V power supply. O, SE 3.3 V, 25 MHz Reference clock output. 3.3 V tolerant input for enabling frequency/spread selection on DIFF0 and DIFF1 outputs (internal 100 k pull-down). SS1 SS0 0 Differential Frequency 100 MHz Differential Spread Spread Off 0 0 1 100 MHz –0.50% 1 0 125 MHz Spread Off 1 1 200 MHz Spread Off Rev 1.0 15 Si52131-A11A Table 8. Part Number 24-Pin QFN Descriptions (Continued) Pin # Name Type 9 NC NC No connect. 10 NC NC No connect. 11 NC NC No connect. 12 VDD_DIFF 13 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 14 DIFF0 O, DIF 0.7 V, 100 MHz differential clock output. 15 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output. 16 DIFF1 O, DIF 0.7 V, 100 MHz differential clock output. 17 VDD_DIFF PWR 3.3 V power supply. 18 OE_DIFF11 I,PD 19 SCLK I 20 SDATA I/O 21 VDD_CORE 22 XOUT O 25.00 MHz Crystal output, Float XOUT if using CLKIN (Clock input). 23 XIN/CLKIN I 25.00 MHz Crystal input or 3.3 V, 25 MHz clock input. 24 VSS_CORE GND Ground for core. 25 GND GND Ground for bottom pad of the IC. 16 Description PWR 3.3 V power supply. Active low input pin enables DIFF1 (internal 100 k pull-down). I2C compatible SCLOCK. I2C compatible SDATA. PWR 3.3 V power supply for core. Rev 1.0 Si52131-A11A 6. Ordering Guide Part Number Package Type Temperature Si52131-A11AGM 24-pin QFN Extended, –40 to 85 C Si52131-A11AGMR 24-pin QFN—Tape and Reel Extended, –40 to 85 C Lead-free Rev 1.0 17 Si52131-A11A 7. Package Outline Figure 8 illustrates the package details. Table 9 lists the values for the dimensions shown in the illustration. Figure 8. 24-Pin Quad Flat No Lead (QFN) Package Table 9. Package Diagram Dimensions Symbol Millimeters Min Nom Max 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.20 0.25 0.30 A D D2 4.00 BSC. 2.60 2.70 e 0.50 BSC. E 4.00 BSC. 2.80 E2 2.60 2.70 2.80 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerances per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components 18 Rev 1.0 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. Trademark Information Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®, EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 USA http://www.silabs.com