T1112P www.vishay.com Vishay Semiconductors Silicon PIN Photodiode FEATURES • Package type: chip • Package form: single chip • Dimensions (L x W x H in mm): 3.05 x 2.1 x 0.28 • Radiant sensitive area (in mm2): 5.5 • Peak sensitivity wavelength: 970 nm • High photo sensitivity • Suitable for visible light and near infrared radiation • Fast response times • Angle of half sensitivity: ϕ = ± 60° • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DESCRIPTION T1112P is a high speed and high sensitive PIN photodiode chip with 5.5 mm2 sensitive area detecting visible and near infrared radiation. Anode and cathode are the bond pads on top. GENERAL INFORMATION The datasheet is based on Vishay optoelectronics sample testing under certain predetermined and assumed conditions, and is provided for illustration purpose only. Customers are encouraged to perform testing in actual proposed packaged and used conditions. Vishay optoelectronics die products are tested using Vishay optoelectronics based quality assurance procedures and are manufactured using Vishay optoelectronics established processes. Estimates such as those described and set forth in this datasheet for semiconductor die will vary depending on a number of packaging, handling, use, and other factors. Therefore sold die may not perform on an equivalent basis to standard package products. PRODUCT SUMMARY Ira (μA) ϕ (deg) λ0.5 (nm) 44 ± 60 640 to 1070 PACKAGING REMARKS PACKAGE FORM Wafer sawn on foil with disco frame MOQ: 11 000 pcs Chip COMPONENT T1112P Note • Test conditions see table “Basic Characteristics” ORDERING INFORMATION ORDERING CODE T1112P-SD-F Note • MOQ: minimum order quantity ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL VALUE Reverse voltage VR 60 V Junction temperature Tj 100 °C Operating temperature range Tamb -40 to +100 °C Storage temperature range Tstg1 -40 to +100 °C Storage temperature range on foil Tstg2 -40 to +50 °C Rev. 1.1, 05-Nov-14 TEST CONDITION UNIT Document Number: 84260 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T1112P www.vishay.com Vishay Semiconductors BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. Breakdown voltage IR = 100 μA, E = 0 V(BR) 60 Reverse dark current Diode capacitance Reverse light current Iro 0.1 42 VR = 3 V, f = 1 MHz, E = 0 CD 19 pF Ee = 1 mW/cm2, λ = 890 nm, VR = 5 V Ira 40 μA Ee = 1 mW/cm2, λ = 950 nm, VR = 5 V Ira 44 μA ϕ ± 60 deg VR = 5 V, RL = 50 Ω, λ = 870 nm VR = 5 V, RL = 50 Ω, λ = 950 nm Fall time V CD Wavelength of peak sensitivity Rise time UNIT VR = 10 V, E = 0 Range of spectral bandwidth Fall time MAX. VR = 0 V, f = 1 MHz, E = 0 Angle of half sensitivity Rise time TYP. 5 nA pF λp 970 nm λ0.5 640 to 1070 nm tr 130 ns tf 130 ns tr 7 μs tf 7 μs Note • The measurements are based on samples of die which are mounted on a TO18-header without resin coating f = 1 MHz, E = 0 Cp - Capacitance (pF) 40.0 30.0 20.0 10.0 0 0.1 1 10 100 VR - Reverse Voltage (V) Fig. 1 - Diode Capacitance vs. Reverse Voltage Rev. 1.1, 05-Nov-14 S(λ)rel - Relative Spectral Sensitivity BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 900 1000 1100 λ - Wavelength (nm) Fig. 2 - Relative Spectral Sensitivity vs. Wavelength without Epoxy Coating Document Number: 84260 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T1112P www.vishay.com Vishay Semiconductors DIMENSIONS in millimeters MECHANICAL DIMENSIONS PARAMETER SYMBOL MIN. TYP. MAX. UNIT Length of chip edge (x-direction) Lx 3.05 Length of chip edge (y-direction) Ly 2.1 mm Sensitive area AS 5.5 mm2 Wafer diameter D Die height H Bond pad anode Bond pad cathode Rev. 1.1, 05-Nov-14 mm 150 0.27 0.28 mm 0.29 mm 0.1 x 0.1 mm2 0.15 x 0.175 mm2 Document Number: 84260 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 T1112P www.vishay.com Vishay Semiconductors ADDITIONAL INFORMATION Frontside metallization, anode AlSi Frontside metallization, cathode AlSi Dicing Die bonding technology Sawing Epoxy bonding Note • All chips are checked in accordance with the Vishay Semiconductor, specification of visual inspection FVOV6870. The visual inspection shall be made in accordance with the “specification of visual inspection as referenced”. The visual inspection of chip backside is performed with stereo microscope with incident light and 40x to 80x magnification. The quality inspection (final visual inspection) is performed by production. An additional visual inspection step as special release procedure by QM is not installed. HANDLING AND STORAGE CONDITIONS • The hermetically sealed shipment lots shall be opened in temperature and moisture controlled cleanroom environment only. It is mandatory to follow the rules for disposition of material that can be hazardous for humans and environment. • Product must be handled only at ESD safe workstations. Standard ESD precautions and safe work environments are as defined in MIL-HDBK-263. • Singulated die are not to be handled with tweezers. A vacuum wand with non metallic ESD protected tip should be used. PACKING Chips are fixed on adhesive foil. Upon request the foils can be mounted on plastic frame or disco frame. For shipment, the wafers are arranged to stacks and hermetically sealed in plastic bags to ensure protection against environmental influence (humidity and contamination). Use for recycling reliable operators only. We can help getting in touch with your nearest sales office. By agreement we will take back packing material, if it is sorted. You will have to bear the costs of transport. We will invoice you for any costs incurred for packing material that is returned unsorted or which we are not obliged to accept. Rev. 1.1, 05-Nov-14 Document Number: 84260 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000